Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/008—Reliability or availability analysis
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits

Definitions

• the present disclosure relates to sophisticated integrated circuits, such as CPUs including highly scaled transistor elements, and compensation techniques for enhancing product performance.
• MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency.
• a field effect transistor typically comprises so-called pn- junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
• the conductivity of the channel region i.e., the drive current capability of the conductive channel
• a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer.
• the conductivity of the channel region upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode depends on the dopant concentration, the mobility of the charge carriers, and - for a given extension of the channel region in the transistor width direction - on the distance between the source and drain regions, which is also referred to as channel length.
• the conductivity of the channel region substantially affects the performance of MOS transistors.
• the scaling of the channel length - and associated therewith the reduction of channel resistivity and increase of gate resistivity - is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
• silicon will likely remain the material of choice for future circuit generations designed for mass products.
• One reason for the dominant importance of silicon in fabricating semiconductor devices, has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other.
• the silicon/silicon dioxide interface is stable at high temperatures and thus, allows the performance of subsequent high temperature processes, as are required for example for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
• silicon dioxide is preferably used as a gate insulation layer in field effect transistors that separates the gate electrode, frequently comprised of polysilicon or other metal containing materials, from the silicon channel region.
• the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation.
• the short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length.
• Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region.
• the thickness of the silicon dioxide layer has to be correspondingly decreased to provide for the required capacitance between the gate and the channel region.
• a channel length of approximately O.O ⁇ m may require a gate dielectric made of silicon dioxide as thin as approximately 1.2nm.
• the relatively high leakage current caused by direct tunneling of charge carriers through an ultra thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1 -2nm that may represent limitations for performance driven circuits. That is, product reliability and lifetime are strongly correlated with short channel effects, i.e., impact ionization and hot carrier injection (HCI) in combination with gate dielectric leakage. Moreover, other effects, such as Negative Bias Temperature Instability (NBTI), which substantially affects p- channel transistors, is increasingly becoming problematic as CMOS scaling continues to involve.
• NBTI Negative Bias Temperature Instability
• any improvements with respect to power consumption may translate into improved performance only, if the power envelope, that is, the area defined by the allowable maximum supply voltage and the maximum thermal power, remains substantially unchanged.
• further device scaling may be correlated with increased operating speed of the product under consideration, while nevertheless increased power consumption may exceed the allowable design power, thereby not enabling to take significant advantage of the reduced dimensions of the components.
• a product manufactured by highly sophisticated technologies may still have to be considered as a product of the same specification category irrespective of the advanced manufacturing technologies, which may possibly come along with increased production costs.
• a generally increased degradation of product performance over operating time may be observed, which may have to be taken into consideration when grouping the various products into specific categories, since the respective product has to meet the specifications over the entire lifetime of the product. For example, in advanced microprocessors this kind of performance degradation manifests itself in a strong degradation of the maximum operating frequency with increasing operating time.
• Fig 1 a schematically illustrates the temporal progression of product performance, for instance in the form of the maximum operating frequency Fmax of microprocessor products, over the lifetime, such as 10 years, wherein an initial state of the product, indicated as I 1 may correspond to a certain maximum operating frequency, which decreases or degrades over time so as to arrive at a significantly lower state F representing the performance at the guaranteed lifetime of the product.
• I 1 an initial state of the product
• Fmax the maximum operating frequency
• Fig 1 b schematically illustrates a power envelope representation in which the design power of an integrated circuit is plotted against a performance parameter, such as the maximum operating frequency Fmax of microprocessors, wherein an upper limit for the thermal design power is indicated by TPL.
• a performance parameter such as the maximum operating frequency Fmax of microprocessors
• an upper limit for the thermal design power is indicated by TPL.
• an area A is illustrated in which products are included having a certain maximum operating speed or frequency as determined after fabrication of the devices while also respecting the upper limit TPL of the thermal design power.
• a lower frequency limit is determined that indicates the lowest allowable Fmax so as to specify an actual product speed, indicated as "product speed" for a product segment A. That is, the product speed represents the required performance of the product in actual applications, which is, however, significantly lower than the lower "Fmax" limit of the area A due to the time dependent performance degradation.
• the product degradation over time may conventionally be taken into consideration by a corresponding "performance guard band".
• a product having the maximum operating frequency I after fabrication may have the status F after the lifetime, wherein the state F has to be above the product speed, thereby requiring a moderately wide guard band. Consequently, any products having an initial maximum frequency which is located within the guard band may have to be grouped into a lower product speed segment, thereby reducing the profitability of the entire manufacturing process, as high speed products may typically be sold at higher prices.
• guard band as much as possible may be highly desirable in view of increasing the profitability of the corresponding manufacturing process.
• an improvement in technology for instance the advance to a next technology generation or an improvement in overall product design may be required but may be associated with significant process modifications resulting in increased research and engineering efforts, thereby contributing to increased production costs.
• peripheral components may have to be implemented into the circuit system, such as sophisticated voltage regulators, in order to precisely adjust the supply voltage on the basis of the operational status of the integrated system.
• a control of the externally supplied voltage within several mV may be required, which may thus add to overall complexity of the entire electronic circuit system.
• the present disclosure relates to methods and devices for reducing or compensating performance degradation of complex integrated circuits while avoiding or at least reducing the effects of one or more of the problems identified above.
• duty cycle of the clock signal is to be understood as the ratio of a high level with respect to the entire period of one block cycle, wherein corresponding fall times and rise times may be neglected.
• a duty cycle of 50% relates to a high level of the clock signal of 50% of the total period.
• a duty cycle of 48% for instance, relates to a high level of 48% and correspondingly to a low level of 52%.
• the variation of the duty cycle may thus affect speed critical device portions without actually modifying the clock signal frequency.
• the modification of the duty cycle may thus result in a shift of the overall performance of the integrated circuit, due to a corresponding shift of performance of speed critical signal paths, while at the same time the clock frequency of the device may be maintained.
• a corresponding compensation mechanism based on an adaptation of the duty cycle may therefore be considered as "neutral" with respect to any power limitations, as are typically encountered in conventional strategies in which the supply voltage may be increased in order to compensate for performance degradation.
• a highly efficient control mechanism may be provided since, for instance, the duty cycle of the clock signal may efficiently be modified compared to extremely sensitive adaptations of a corresponding supply voltage used in conventional strategies.
• One illustrative method disclosed herein relates to the stabilization of performance of an integrated circuit device.
• the method comprises determining an updated value of a parameter that indicates performance of the integrated circuit.
• the method comprises controlling a duty cycle of a clock signal of the integrated circuit device on the basis of the updated value so as to stay within a specified range.
• a still further illustrative method disclosed herein relates to the operation of an integrated circuit.
• the method comprises establishing a correlation between a performance characteristic of the integrated circuit and a duty cycle of a clock signal used in the integrated circuit.
• the method further comprises controlling the duty cycle during operation of the integrated circuit at least several times within an operational lifetime of the integrated circuit on the basis of the correlation.
• One illustrative electronic circuit system disclosed herein comprises an integrated circuit comprising an internal clock signal generator and a functional circuit portion connected to receive a clock signal of the clock signal generator. Moreover, the electronic circuit system comprises a duty cycle control unit that is operatively connected to the clock signal generator and is configured to initiate a change of a duty cycle of the clock signal several times during an operational lifetime of the integrated circuit.
• Figs 1 a and 1 b schematically illustrate graphical representations of the performance behaviour over lifetime of conventional advanced integrated circuits including CMOS transistors operated on the basis of a substantially constant supply voltage;
• Fig 2a schematically illustrates a time diagram of a clock signal of a given frequency with different duty cycles, as may be used for a duty cycle based compensation of less degradation according to illustrative embodiments;
• Fig 2b schematically illustrates a diagram for demonstrating the operational behaviour and a corresponding technique for compensating device degradation on the basis of applying an appropriate duty cycle over lifetime of an integrated circuit according to illustrative embodiments.
• Fig 2c schematically illustrates an electronic system comprising an integrated circuit in combination with a duty cycle control unit that is configured to compensate device degradation of the integrated circuit over lifetime, wherein the duty cycle control unit may be provided as external component or an internal component according to illustrative embodiments.
• the present disclosure relates to electronic circuit systems and methods for operating the same, wherein performance degradation of integrated circuits may be reduced or compensated for on the basis of appropriately adapting the duty cycle of a clock signal wherein, in some illustrative embodiments, the supply voltage and also the clock signal frequency may remain non-modified over the operational lifetime of the integrated circuit.
• an efficient control mechanism for compensating the natural aging of an integrated circuit may be provided without being restricted by the overall power consumption, which may be a critical factor in conventional control strategies based on an increase of the supply voltage.
• the dynamic power consumption may not increase during the compensation of the performance degradation based on the duty cycle mechanism, since the clock frequency may not be increased.
• the compensation mechanism of the present disclosure may also be combined with other mechanisms, such as a moderate increase of supply voltage, if the range of the compensating effect based on an appropriate adaptation of the duty cycle may have to be increased, for instance in a very advanced stage of the accumulated operational lifetime of the integrated circuit under consideration. Since the performance degradation, for instance in terms of maximum operating speed, may dynamically be reduced during the entire lifetime of the device on the basis of an appropriate adaptation of the duty cycle, the corresponding guard bands used for specifying a certain performance class of a product may be reduced, the products may be assigned to a specific performance segment, which would conventionally have been grouped into a less sophisticated product segment.
• the distribution of products in the high performance area may be accomplished on the basis of less narrow tolerance ranges, thereby increasing the number of products that may be assigned to a specific high performance product segment.
• the overall performance of the products may be enhanced since the integrated circuits may be operated with reduced performance loss over the entire lifetime, while not unduly increasing the overall total power consumption.
• Corresponding parameter values for estimating the current performance characteristic may readily be obtained during the operation of the device under consideration, for instance by actually measuring the duty cycle and/or by appropriately reading out the status of a corresponding block signal generator or a corresponding structure controlling the duty cycle of the clock signal generator.
• the duty cycle setting for the generation of a corresponding clock signal in sophisticated integrated circuits may be "hardwired” or may be adjusted during a final test phase of the integrated circuit by setting corresponding electronic fuses.
• the duty cycle may dynamically be adapted, for instance by replacing a corresponding hardwired control regime for the duty cycle setting by a control circuitry that may dynamically vary a corresponding control setting.
• a plurality of corresponding "hardwired" configurations may be provided as a "switchable" array so that a plurality of different duty cycle values may be selected by enabling a respective one of the hardwired array components.
• the clock signal generator may directly be controlled by an electronic circuit portion, the momentary setting of which may be stored in a nonvolatile memory area if the integrated circuit is de-activated.
• a corresponding correlation between the duty cycle and the performance of the integrated circuit may be established in advance, for instance by performing accelerated aging tests of similar products operated on the basis of different duty cycles.
• a corresponding set of performance data and associated duty cycles may be implemented into a corresponding control team in order to appropriately adapt the duty cycle for reducing any performance degradation over the accumulated lifetime of the integrated circuit.
• a control strategy may include a corresponding adaptation of the duty cycle on the basis of the accumulated operational lifetime of the device without actually requiring a measurement of the momentary performance of the integrated circuit.
• different duty cycle values may be "enabled” at predefined times of the accumulated lifetime, which may be determined on the basis of the device internal timer or on the basis of an external circuit portion used in combination with the integrated circuit.
• a corresponding correlation between the duty cycle and the performance of the device may be established on demand, that is, a corresponding correlation may be established at various points in time, for instance when a certain degree of performance degradation has been identified.
• an appropriate duty cycle value maybe selected and may be used for the further operation of the device in order to maintain the performance characteristic thereof within a specified range.
• the evaluation of the momentary performance of the integrated circuit may be accomplished on the basis of a dedicated circuit portion of the integrated device, which may be strongly correlated with the performance of speed critical signal paths within a functional portion of the integrated circuit.
• ring oscillators and the like may be implemented into a test circuit portion and may thus efficiently be used for quantitatively estimating the momentary performance of the integrated circuit.
• the correlation between the momentary performance values and the duty cycle may be established on the basis of corresponding "library" data obtained in advance or the duty cycle may be varied during operation of the integrated circuit in order to obtain various performance data that are associated to corresponding duty cycle values.
• a desired initial performance of the integrated circuit may be "re-established", at least within a specified range, by storing an initial value indicative of the initial performance behavior of the integrated circuit and comparing the momentary performance and the associated duty cycles with the initial value.
• an appropriate duty cycle may be identified which may reestablish the initial performance behaviour or which may at least maintain performance of the device within a specified range centred around the initial performance value.
• FIG. 2a - 2c further illustrative embodiments will now be described in more detail, wherein also reference to Figs 1 a and 1 b may be made, if appropriate.
• Fig 2a schematically illustrates a time diagram illustrating a clock signal provided at a predefined frequency wherein, however, the duty cycle may be varied.
• three different duty cycles, represented by curves A, B and C, for a block signal are illustrated. That is, the horizontal axis represents the time wherein for a given frequency a certain interval G may thus represent a full period or cycle of each of the clock signals A, B, C.
• the vertical axis represents the signal amplitude in arbitrary units. For example, the amplitude of the clock signal may substantially swing between the lower and the upper limit of a corresponding supply voltage.
• curve A may represent the clock signal with a duty cycle of 50%, that is, the time interval of the higher level of signal A may be equal to the time interval of the low level within one block cycle T.
• a corresponding duty cycle may also be referred to as a clock signal having a "zero skew". It should be appreciated that typically rising and falling of the clock signal may have a duration that is significantly less compared to the full period T.
• Curve B represents the clock signal of the same frequency, however with a "negative skew", that is, the duty cycle thereof is less compared to curve A. Consequently, the duration of the high level is less compared to the duration of the low level.
• the duty cycle may be 45%, indicating that during the full time period T the signal B may be 45% at the high signal level, including half of the rise and fall time while on the other hand 55% may correspond to the low level state of the signal B, also including half of the corresponding rise and fall times.
• Curve C represents the clock signal having a "positive skew" since the corresponding time duration of the high level state is increased with respect to curve A, while the corresponding low level time interval is shorter.
• the duty cycle of the clock signal may have an influence on the overall performance of speed critical signal paths within an integrated circuit.
• the corresponding limiting circuit or speed path and thus the entire integrated circuit may have a preference for increasing performance on the basis of a negative or positive duty cycle. That is, due to the complexity of modern integrated circuits, the clock signals may have to be provided to very different circuit portions, wherein different signal propagation delays and the like may result in a more or less pronounced deformation of the clock signal.
• the functional behaviour of certain circuit portions may be influenced, thereby resulting in overall increase or decrease of the performance, for instance the maximum operating speed of the device under consideration.
• the response of the integrated circuit to a variation of the duty cycle may change over time due to the natural aging of the device, for instance with respect to a shift of important device parameters, such as threshold voltage, leakage and drive current of the transistor elements. Consequently, the corresponding correlation between the duty cycle and a corresponding response of the circuit in view of overall performance characteristics may efficiently be used in compensating the natural performance degradation.
• Fig 2b schematically illustrates a diagram representing a strategy for compensating device degradation on the basis of an appropriate adaptation of the duty cycle of a clock signal.
• the horizontal axis may represent the accumulated operating time of integrated circuits, while the vertical axis may represent one or more parameters indicative of the performance of the device, for instance the maximum operating speed, indicated as FMAX, and the like may be used for quantitatively evaluating the behaviour of the integrated circuit under consideration.
• the operational lifetime of the device under consideration may "start", ie. the device may be implemented in a corresponding electronic system and may be operated in accordance with system specific operating conditions.
• the performance behaviour of the device under consideration may be determined by a corresponding value, for instance representing the maximum operating speed and the like.
• Curve D in Fig 2b may represent a corresponding degradation of the performance of the device when operated under substantially constant conditions, that is, by using a substantially constant supply voltage at a stable clock frequency.
• the behaviour of curve D may represent a corresponding device behaviour, as is also previously discussed with reference to Fig 1 a.
• the quantitatively estimated performance device at the initial time To may be measured and may be used in order to determine a desired or target performance or performance range to be maintained during the entire operational lifetime of the integrated circuit.
• a specified range indicated as R may be selected on the basis of the initial performance which may, for instance, allow significantly reduced guard bands since a corresponding performance degradation may be maintained within the range R.
• the duty cycle of the corresponding clock signal may be appropriately adapted so as to increase the performance characteristic, which may have degraded along curve D.
• an appropriate correlation between the duty cycle and performance of the device may be established in advance, for instance on the basis of corresponding accelerated aging tests and the like so that according to some illustrative embodiments a specific duty cycle value may be applied at the accumulated time Ti in order to maintain the performance reliably within the range R.
• the momentary performance characteristic of the device under consideration may be tested or measured, for instance on the basis of a device internal circuit portion, such as a ring oscillator and the like, which may be strongly correlated to the actual performance of a functional circuit portion. For example at time interval U a corresponding parameter value may be determined, such as the value indicative of FMAX and may be assessed in view of its allowability. That is, it may be determined whether or not a momentary performance characteristic is within the allowable range R and whether or not a compensation is required so as to maintain performance within the range R before updating of the performance characteristics is performed.
• a momentary performance characteristic is within the allowable range R and whether or not a compensation is required so as to maintain performance within the range R before updating of the performance characteristics is performed.
• the controller strategy may be based on the concept of maintaining the current performance closely to the initial performance, which may be accomplished by selecting an appropriate duty cycle value that provides for the required degree of compensation.
• respective performance values may be determined for different duty cycles.
• corresponding performance values 200 such as values 200a, ... , 20Of, may be determined wherein each of these performance values may be associated with a corresponding dedicated duty cycle value.
• the value 20Od may represent the performance value when operating the device with a duty cycle that is 1 % higher compared to the initially used duty cycle.
• the value 200c may be associated with a duty cycle that is increased by 2% and the like.
• the values 20Oe, 20Of may represent the performance characteristic for a reduced duty cycle compared to the initially used duty cycle.
• the performance values 200 and the associated duty cycle values may be obtained on a "real time basis", which may be accomplished by causing a clock signal generator of the device so as to operate with different duty cycle values within specific short time intervals, while the corresponding performance parameter values may be measured, for instance on the basis of a device internal test portion, as previously explained.
• the values 200 may be obtained in advance, for instance on the basis of test measurements in which a plurality of respective integrated circuits may be operated under accelerated test conditions. Consequently, a corresponding control system may select an appropriate one of the values 200 and further operation of the device under consideration may be continued by using the newly selected duty cycle.
• the duty cycle corresponding to the performance value 200c may be selected so as to maintain the performance value at the initially determined performance of the device.
• corresponding control strategy may also provide any intermediate values, for instance by interpolating a corresponding correlation between performance characteristic values and the associated duty cycles. It should further be appreciated that also any desired time resolution may be selected so as to further reduce device variability.
• a later time t 2 of the above-described procedure may be repeated in order to further compensate for a corresponding device degradation.
• the degradation of the device under consideration may proceed along curve E that may correspond to the duty cycle associated with the performance value 200c. Consequently, the duty cycle may appropriately be adapted, for instance using the duty cycle associated with the performance value 200a at time T 1 thereby maintaining overall performance of the device closely to the initial performance.
• corresponding performance characteristic values may be determined independently of the values 200a 20Of related to the time t 1 f which may be accomplished by obtaining corresponding performance values and associated duty cycle values in advance during corresponding test runs, as previously explained, or by real time measurement using device internal resources.
• the further operation of the device under consideration may be continued by using an updated duty cycle value, thereby maintaining overall performance of the device within the range R.
• Fig 2c schematically illustrates an electronic circuit system 250 comprising an integrated circuit 210, the operation of which is to be compensated for on the basis of a duty cycle adaptation, as previously discussed.
• the system 250 may comprise a duty cycle control unit 220 that is operatively connected to the integrated circuit 210, and which may be provided as a device internal component of the integrated circuit 210, or which may be represented by an external device.
• the electronic circuit system 250 may comprise a supply voltage source 230 that may provide a supply voltage at least for the integrated circuit 210.
• the integrated circuit 210 may comprise a clock signal generator 213 that is configured to provide a clock signal at least at a specified frequency, while a duty cycle of the clock signal may be adjustable, for instance on the basis of a control signal supplied by the duty cycle control circuit 220.
• the integrated circuit 210 may comprise at least one functional circuit block, such as a CPU core 212, a memory portion 214 connected to the block 212, and an input/output (I/O) interface 211. It should be appreciated however that any other functional circuit block may be provided in the integrated circuit 210, depending on the overall device requirements, as long as at least one speed critical circuit portion or signal path may be operated on the basis of the clock signal provided by the generator 213.
• the integrated circuit 210 may further comprise a test circuit portion 215, which may include appropriate circuit elements and the like in order to enable the monitoring of the actual performance characteristics of the integrated circuit 210.
• the test circuit portion 215 may comprise a ring oscillator and the like which may be formed on the basis of similar circuit elements as a corresponding speed critical circuit portion or signal path, for instance the portion 212, so that performance of the test circuit portion 215 may strongly be related to the actual performance of a speed critical portion 212, which in turn may substantially determine the overall operating performance of the integrated circuit 210. Consequently, performance data may be obtained by the control unit 220 from the test circuit portion 215 according to any appropriate time schedule.
• a control unit 220 may communicate with the clock signal generator 213 and the test circuit portion 215 by device internal communication, such as dedicated signal buses and the like, when the unit 220 may be a device internal component of the integrated circuit 210.
• the unit 220 may be provided within the same package 217, which may also accommodate the other functional components of the integrated circuit 210.
• the integrated circuit 210 may represent a single chip system in which the various circuit portions may be implemented in a single semiconductor die, thereby providing for a highly efficient manufacturing process. In other cases two or more portions of the integrated circuit 210 including the control unit 220 may be provided on different semiconductor chips which, however, may be combined in a three-dimensional chip configuration in a common package.
• the unit 220 may be provided as an external component which may communicate with the integrated circuit 210 via the interface 21 1.
• appropriate control signals for the generator 213 and respective data from the test portion 215 may be communicated via the interface 21 1 , which may provide for corresponding recesses for interfacing with the unit 220.
• an appropriate control strategy may be implemented into the unit 220 and/or a corresponding non-volatile memory, such as a memory 216, wherein all specific data may be stored such as an initial performance value or corresponding performance values and associated duty cycle values for a plurality of different accumulated operational lifetimes, as previously explained.
• a corresponding control strategy may be implemented so as to continuously or discretely monitor the performance of the device 210 during operation and select an appropriate duty cycle value, which may result in the generation of an appropriate control signal for causing the block signal generator 213 to update the corresponding duty cycle.
• the unit 220 may monitor the momentary performance of the integrated circuit 210 and may select an appropriate duty cycle value in order to compensate a corresponding device degradation. For this purpose any of the above-identified strategies may be used.
• a corresponding adaptation of the duty cycle may be accomplished by enabling respective circuit components in the generator 213, such as hardwired components, each of which may provide for a specific duty cycle, or corresponding electronic fuses may be used for this purpose.
• the clock signal generator 213 may be configured so as to be responsive to a more or less continuous control signal in order to substantially continuously vary the duty cycle of the clock signal based on the control signal supplied by the unit 220.
• an initial value or performance characteristic of the device 210 may be stored, for instance in the non-volatile memory 216 and may be used for substantially reestablishing the initial performance characteristic on the basis of an appropriately selected duty cycle value.
• system 250 may be operated on the basis of a substantially constant supply voltage provided by the voltage source 230, thereby not unduly increasing the static power consumption.
• the clock signal generator 213 may be operated so as to provide the clock signal with a specific constant clock frequency, thereby also avoiding an increase of dynamic power consumption.
• the present disclosure provides control strategies and electronic circuit systems in which product degradation may be recovered or compensated during normal field operation of the electronic circuit system by adjusting the clock duty cycle using a corresponding duty cycle control unit.
• a reduced product frequency guard banding system is necessary thereby providing for additional product performance margins, which may also translate into enhanced profitability since corresponding integrated circuits may be assigned to more sophisticated product segments, such as higher speed grades.
• the total power consumption may not have to be increased since an efficient compensation may be obtained at a substantially constant supply voltage at a single clock frequency.

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