JP2012134379A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP2012134379A JP2012134379A JP2010286152A JP2010286152A JP2012134379A JP 2012134379 A JP2012134379 A JP 2012134379A JP 2010286152 A JP2010286152 A JP 2010286152A JP 2010286152 A JP2010286152 A JP 2010286152A JP 2012134379 A JP2012134379 A JP 2012134379A
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- fuse
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 230000002950 deficient Effects 0.000 claims description 23
- 230000004044 response Effects 0.000 claims description 3
- 238000003491 array Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 101150013030 FAN1 gene Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
- G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
- G11C2229/76—Storage technology used for the repair
- G11C2229/766—Laser fuses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
【解決手段】 ヒューズ露出窓を介して外部に露出して互いに並置された複数のヒューズ片を各々が含む複数のヒューズブロックがゲートアレイの近傍において縦列に配置され、電源配線と接地配線とが当該ヒューズ片の並置方向に沿って延在しており、ヒューズブロックの配置のために当該ゲートアレイの近傍のスペースを活用した半導体記憶装置。
【選択図】図3
Description
3 チップ
5、6 メモリセルアレイ
10 ゲートアレイ
21〜26 論理回路
31〜36 ヒューズブロック
40 VSS配線
50 VDD配線
41〜46、51〜56 電源配線
60−1〜60−n、65−1〜65−n 供給配線
70 トランジスタ
75 VSS接続用配線
81〜86 付加パターン
91〜93 供給配線
FA、FB、FA0〜FAn、FA0B〜FAnB ヒューズ片
B、A0〜An 端子
Claims (7)
- 複数のメモリセルからなるメモリセルアレイと、
電源配線及び接地配線に各々が接続され且つヒューズ露出窓を介して外部に露出して互いに並置された複数のヒューズ片を各々が含み、前記ヒューズ片の選択的な切断の態様によって定まる不良メモリアドレスを各々が記憶する複数のヒューズブロックと、
前記メモリセルの1つへのアクセス信号が示すメモリアドレスと前記不良メモリアドレスとの比較に基づいて前記メモリセルの1つを選択する選択回路と、
電源電位及び接地電位の供給を受けて前記選択回路によって選択されたメモリセルに対応するデータを処理するゲートアレイと、を含む半導体記憶装置であって、
前記複数のヒューズブロックは、前記ゲートアレイの近傍において縦列に配置され、
前記電源配線と前記接地配線とは、前記ヒューズ片の並置方向に沿って延在しており、
前記電源配線及び前記接地配線のうちの、前記ゲートアレイから遠い側の配線と同電位に接続され且つ前記ヒューズ露出窓を回避する付加パターンと、
前記付加パターンの電位を前記ゲートアレイに供給する供給配線と、を含むことを特徴とする半導体記憶装置。 - 前記付加パターンは、前記ゲートアレイに近い側の配線の近傍において延在していることを特徴とする請求項1に記載の半導体記憶装置。
- 複数のメタル層を含み、
前記付加パターンは、前記電源配線及び前記接地配線が形成されているメタル層とは別のメタル層に形成されていることを特徴とする請求項1に記載の半導体記憶装置。 - 前記付加パターンは、前記電源配線及び前記接地配線のうちの前記ゲートアレイに近い側にある配線と互いに重畳位置関係にあることを特徴とする請求項2に記載の半導体記憶装置。
- 前記付加パターンは、前記ヒューズブロックの少なくとも1つ毎に設けられた複数のパターン片であることを特徴とする請求項1に記載の半導体記憶装置。
- 複数のメモリセルからなるメモリセルアレイと、
電源配線及び接地配線に各々が接続され且つヒューズ露出窓を介して外部に露出して互いに並置された複数のヒューズ片を各々が含み、前記ヒューズ片の選択的な切断の態様によって定まる不良メモリアドレスを各々が記憶する複数のヒューズブロックと、
前記メモリセルの1つへのアクセス信号が示すメモリアドレスと前記不良メモリアドレスとの比較に基づいて前記メモリセルの1つを選択する複数の選択回路と、
電源電位及び接地電位の供給を受けて前記選択回路によって選択されたメモリセルに対応するデータを処理するゲートアレイと、を含む半導体記憶装置であって、
前記複数の選択回路は、前記ゲートアレイの近傍において縦列に配置され、
前記複数のヒューズブロックは、前記複数の選択回路と前記ゲートアレイとの間に縦列に配置され、
前記電源配線と前記接地配線とは、前記複数の選択回路と前記ゲートアレイとの間において前記ヒューズ片の並置方向に沿って延在しており、
前記ゲートアレイは、前記電源配線から前記電源電位の供給を受け且つ前記接地配線から前記接地電位の供給を受けることを特徴とする半導体記憶装置。 - 前記電源配線と前記接地配線とは、前記ヒューズ露出窓を避けて前記複数のヒューズブロック上に配置されることを特徴とする請求項6に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010286152A JP5743057B2 (ja) | 2010-12-22 | 2010-12-22 | 半導体記憶装置 |
US13/331,451 US8848416B2 (en) | 2010-12-22 | 2011-12-20 | Semiconductor storage device with wiring that conserves space |
CN201110432441.5A CN102543201B (zh) | 2010-12-22 | 2011-12-21 | 半导体存储装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010286152A JP5743057B2 (ja) | 2010-12-22 | 2010-12-22 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
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JP2012134379A true JP2012134379A (ja) | 2012-07-12 |
JP5743057B2 JP5743057B2 (ja) | 2015-07-01 |
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JP2010286152A Active JP5743057B2 (ja) | 2010-12-22 | 2010-12-22 | 半導体記憶装置 |
Country Status (3)
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US (1) | US8848416B2 (ja) |
JP (1) | JP5743057B2 (ja) |
CN (1) | CN102543201B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5743057B2 (ja) * | 2010-12-22 | 2015-07-01 | ラピスセミコンダクタ株式会社 | 半導体記憶装置 |
US9122830B2 (en) * | 2013-06-03 | 2015-09-01 | Globalfoundries Inc. | Wide pin for improved circuit routing |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0964310A (ja) * | 1995-08-21 | 1997-03-07 | Hitachi Ltd | 半導体集積回路装置 |
JPH1117016A (ja) * | 1997-06-25 | 1999-01-22 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH1117018A (ja) * | 1997-06-27 | 1999-01-22 | Hitachi Ltd | フューズ装置および半導体記憶装置 |
WO2004013909A1 (ja) * | 2002-08-02 | 2004-02-12 | Hitachi, Ltd. | メモリを内蔵した半導体集積回路 |
JP2005268403A (ja) * | 2004-03-17 | 2005-09-29 | Matsushita Electric Ind Co Ltd | 半導体装置のレイアウト方法 |
US20050221539A1 (en) * | 1999-08-31 | 2005-10-06 | Samsung Electronics Co., Ltd. | Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3099802B2 (ja) | 1998-04-09 | 2000-10-16 | 日本電気株式会社 | 半導体記憶装置 |
JP5743057B2 (ja) * | 2010-12-22 | 2015-07-01 | ラピスセミコンダクタ株式会社 | 半導体記憶装置 |
-
2010
- 2010-12-22 JP JP2010286152A patent/JP5743057B2/ja active Active
-
2011
- 2011-12-20 US US13/331,451 patent/US8848416B2/en not_active Expired - Fee Related
- 2011-12-21 CN CN201110432441.5A patent/CN102543201B/zh not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0964310A (ja) * | 1995-08-21 | 1997-03-07 | Hitachi Ltd | 半導体集積回路装置 |
JPH1117016A (ja) * | 1997-06-25 | 1999-01-22 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH1117018A (ja) * | 1997-06-27 | 1999-01-22 | Hitachi Ltd | フューズ装置および半導体記憶装置 |
US20050221539A1 (en) * | 1999-08-31 | 2005-10-06 | Samsung Electronics Co., Ltd. | Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area |
WO2004013909A1 (ja) * | 2002-08-02 | 2004-02-12 | Hitachi, Ltd. | メモリを内蔵した半導体集積回路 |
JP2005268403A (ja) * | 2004-03-17 | 2005-09-29 | Matsushita Electric Ind Co Ltd | 半導体装置のレイアウト方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102543201A (zh) | 2012-07-04 |
JP5743057B2 (ja) | 2015-07-01 |
CN102543201B (zh) | 2016-03-16 |
US8848416B2 (en) | 2014-09-30 |
US20120163105A1 (en) | 2012-06-28 |
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