JP2012129337A5 - - Google Patents

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Publication number
JP2012129337A5
JP2012129337A5 JP2010278926A JP2010278926A JP2012129337A5 JP 2012129337 A5 JP2012129337 A5 JP 2012129337A5 JP 2010278926 A JP2010278926 A JP 2010278926A JP 2010278926 A JP2010278926 A JP 2010278926A JP 2012129337 A5 JP2012129337 A5 JP 2012129337A5
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JP
Japan
Prior art keywords
bit line
memory cells
data
word line
complementary
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JP2010278926A
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English (en)
Japanese (ja)
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JP2012129337A (ja
JP5648460B2 (ja
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Priority to JP2010278926A priority Critical patent/JP5648460B2/ja
Priority claimed from JP2010278926A external-priority patent/JP5648460B2/ja
Publication of JP2012129337A publication Critical patent/JP2012129337A/ja
Publication of JP2012129337A5 publication Critical patent/JP2012129337A5/ja
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Publication of JP5648460B2 publication Critical patent/JP5648460B2/ja
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JP2010278926A 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器 Active JP5648460B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010278926A JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010278926A JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Publications (3)

Publication Number Publication Date
JP2012129337A JP2012129337A (ja) 2012-07-05
JP2012129337A5 true JP2012129337A5 (enExample) 2014-01-30
JP5648460B2 JP5648460B2 (ja) 2015-01-07

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ID=46646074

Family Applications (1)

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JP2010278926A Active JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Country Status (1)

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JP (1) JP5648460B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12073919B2 (en) * 2021-06-25 2024-08-27 Advanced Micro Devices, Inc. Dual read port latch array bitcell

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2821063B2 (ja) * 1991-07-18 1998-11-05 富士通株式会社 半導体集積回路装置
US5966317A (en) * 1999-02-10 1999-10-12 Lucent Technologies Inc. Shielded bitlines for static RAMs
US6504246B2 (en) * 1999-10-12 2003-01-07 Motorola, Inc. Integrated circuit having a balanced twist for differential signal lines
JP3835220B2 (ja) * 2001-08-31 2006-10-18 セイコーエプソン株式会社 半導体記憶装置
JP4052192B2 (ja) * 2003-03-14 2008-02-27 セイコーエプソン株式会社 半導体集積回路
JP4914034B2 (ja) * 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
JP5217042B2 (ja) * 2007-07-06 2013-06-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5549079B2 (ja) * 2009-01-14 2014-07-16 セイコーエプソン株式会社 半導体集積回路

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