JP2012044180A - 微細ピッチバンプを備えた基板及びその製造方法 - Google Patents
微細ピッチバンプを備えた基板及びその製造方法 Download PDFInfo
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- JP2012044180A JP2012044180A JP2011178356A JP2011178356A JP2012044180A JP 2012044180 A JP2012044180 A JP 2012044180A JP 2011178356 A JP2011178356 A JP 2011178356A JP 2011178356 A JP2011178356 A JP 2011178356A JP 2012044180 A JP2012044180 A JP 2012044180A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 108
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000010949 copper Substances 0.000 claims abstract description 23
- 239000012792 core layer Substances 0.000 claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052802 copper Inorganic materials 0.000 claims abstract description 22
- 238000007747 plating Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000005553 drilling Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
【解決手段】本発明の実施形態による微細ピッチバンプを備えた基板製造方法は、回路パターンが形成されたコア層にソルダーレジストを積層してソルダーレジスト層を形成する段階と、ソルダーレジスト層の上面にシード層(Seed Layer)を形成する段階と、シード層の上面にドライフィルムを積層してドライフィルム層を形成する段階と、ソルダーレジスト層、シード層及びドライフィルム層を同時に加工してホールを形成する段階と、前記ホールに銅充填メッキを行い、シード層及びドライフィルム層を除去して銅ポストバンプを形成する段階と、を含み、ソルダーレジスト層とドライフィルム層に同一のサイズのホールを同時に加工するため、銅ポストバンプの整合度を向上させることができ、これにより、バンプの微細ピッチの形成を実現できるという効果を期待することができる。
【選択図】図5
Description
さらに、前記ソルダーレジストは、コア層の上面または下面に積層されることが好ましい。
110 コア層
130 回路パターン
150 ソルダーレジスト層
170 シード層
190 ドライフィルム層
210 ホール
Claims (8)
- 回路パターンが形成されたコア層にソルダーレジストを積層してソルダーレジスト層を形成する段階と、
ソルダーレジスト層の上面にシード層を形成する段階と、
シード層の上面にドライフィルムを積層してドライフィルム層を形成する段階と、
ソルダーレジスト層、シード層及びドライフィルム層を同時に加工してホールを形成する段階と、
前記ホールに銅充填メッキを行い、シード層及びドライフィルム層を除去して銅ポストバンプを形成する段階と、
を含む微細ピッチバンプを備えた基板製造方法。 - 前記ソルダーレジスト層、シード層及びドライフィルム層に形成されたホールの幅が互いに同一であるようにホールを形成することを特徴とする請求項1に記載の微細ピッチバンプを備えた基板製造方法。
- 前記回路パターンは、コア層の上面または下面に形成されることを特徴とする請求項2に記載の微細ピッチバンプを備えた基板製造方法。
- 前記ソルダーレジストは、コア層の上面または下面に積層されることを特徴とする請求項3に記載の微細ピッチバンプを備えた基板製造方法。
- 回路パターンが形成されたコア層と、
コア層の上面または下面に積層されたソルダーレジスト層と、
前記ソルダーレジスト層の上面に形成されたシード層と、
前記シード層の上面に形成されたドライフィルム層と、
前記ソルダーレジスト層、シード層及びドライフィルム層を貫通するホールと、
前記ホールに銅充填メッキによって形成される銅ポストバンプと、
を含む微細ピッチバンプを備えた基板。 - 前記ソルダーレジスト層、シード層及びドライフィルム層に形成されたホールの幅が互いに同一であるようにホールを形成することを特徴とする請求項5に記載の微細ピッチバンプを備えた基板。
- 前記回路パターンは、コア層の上面または下面に形成されることを特徴とする請求項6に記載の微細ピッチバンプを備えた基板。
- 前記ソルダーレジスト層は、コア層の上面または下面に積層されることを特徴とする請求項7に記載の微細ピッチバンプを備えた基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0079832 | 2010-08-18 | ||
KR1020100079832A KR101138592B1 (ko) | 2010-08-18 | 2010-08-18 | 미세 피치 범프를 구비한 기판과 이의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012044180A true JP2012044180A (ja) | 2012-03-01 |
JP5558432B2 JP5558432B2 (ja) | 2014-07-23 |
Family
ID=45593175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2011178356A Expired - Fee Related JP5558432B2 (ja) | 2010-08-18 | 2011-08-17 | 微細ピッチバンプを備えた基板製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20120043122A1 (ja) |
JP (1) | JP5558432B2 (ja) |
KR (1) | KR101138592B1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101422524B1 (ko) * | 2012-12-24 | 2014-07-24 | 주식회사 심텍 | 미세 피치의 접속부를 구비하는 인쇄회로기판 및 이의 제조 방법 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002016096A (ja) * | 2000-06-27 | 2002-01-18 | Citizen Watch Co Ltd | 半導体装置とその製造方法 |
JP2003124246A (ja) * | 2001-10-12 | 2003-04-25 | Sharp Corp | 半導体装置及びその製造方法 |
JP2004028185A (ja) * | 2002-06-25 | 2004-01-29 | Yazaki Corp | トランスミッション |
JP2004281835A (ja) * | 2003-03-18 | 2004-10-07 | Sumitomo Bakelite Co Ltd | プリント配線板及びその製造方法 |
JP2008218540A (ja) * | 2007-03-01 | 2008-09-18 | Matsushita Electric Ind Co Ltd | 配線基板の製造方法 |
JP2008311592A (ja) * | 2007-06-18 | 2008-12-25 | Shinko Electric Ind Co Ltd | 電子装置の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4259774B2 (ja) | 2001-07-16 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
KR20100060968A (ko) * | 2008-11-28 | 2010-06-07 | 삼성전기주식회사 | 메탈 포스트를 구비한 기판 및 그 제조방법 |
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2010
- 2010-08-18 KR KR1020100079832A patent/KR101138592B1/ko not_active IP Right Cessation
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2011
- 2011-08-17 JP JP2011178356A patent/JP5558432B2/ja not_active Expired - Fee Related
- 2011-08-18 US US13/212,651 patent/US20120043122A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002016096A (ja) * | 2000-06-27 | 2002-01-18 | Citizen Watch Co Ltd | 半導体装置とその製造方法 |
JP2003124246A (ja) * | 2001-10-12 | 2003-04-25 | Sharp Corp | 半導体装置及びその製造方法 |
JP2004028185A (ja) * | 2002-06-25 | 2004-01-29 | Yazaki Corp | トランスミッション |
JP2004281835A (ja) * | 2003-03-18 | 2004-10-07 | Sumitomo Bakelite Co Ltd | プリント配線板及びその製造方法 |
JP2008218540A (ja) * | 2007-03-01 | 2008-09-18 | Matsushita Electric Ind Co Ltd | 配線基板の製造方法 |
JP2008311592A (ja) * | 2007-06-18 | 2008-12-25 | Shinko Electric Ind Co Ltd | 電子装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR101138592B1 (ko) | 2012-05-10 |
JP5558432B2 (ja) | 2014-07-23 |
US20120043122A1 (en) | 2012-02-23 |
KR20120017246A (ko) | 2012-02-28 |
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