JP2012044080A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2012044080A JP2012044080A JP2010185802A JP2010185802A JP2012044080A JP 2012044080 A JP2012044080 A JP 2012044080A JP 2010185802 A JP2010185802 A JP 2010185802A JP 2010185802 A JP2010185802 A JP 2010185802A JP 2012044080 A JP2012044080 A JP 2012044080A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element connection
- connection pad
- semiconductor
- welded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
熱容量の異なる半導体素子接続パッドに半田バンプを介して半導体素子の電極を接続する際、半田バンプ同士の短絡を防ぎ半導体素子の正常作動が可能な配線基板を提供すること。
【解決手段】
ビア導体2aが充填された多数のビアホール1cを有する絶縁層1bの表面にビア導体2aと一体的に形成された導体層2から成る第1の半導体素子接続パッド3aと、絶縁層1b上に形成された導体層2のみから成る第2の半導体素子接続パッド3bとが、第1の半導体素子接続パッド3aの配列中に第2の半導体素子接続パッド3bが分散して配設されるとともに第1および第2の半導体素子接続パッド3aおよび3bに半田バンプ5が溶着されて成る配線基板10であって、第2の半導体素子接続パッド3bに溶着された半田バンプ5の体積が第1の半導体素子接続パッド3aに溶着された半田バンプ5の体積より小さい配線基板10である。
【選択図】図2
Description
1c ビアホール
2 導体層
2a ビア導体
3a 第1の半導体素子接続パッド
3b 第2の半導体素子接続パッド
5 半田バンプ
10 配線基板
Claims (2)
- ビア導体が充填された多数のビアホールを有する絶縁層の表面に、前記ビア導体と一体的に形成された導体層から成る多数の第1の半導体素子接続パッドと、前記絶縁層上に形成された導体層のみから成る第2の半導体素子接続パッドとが、前記第1の半導体素子接続パッドの配列の中に前記第2の半導体素子接続パッドが分散して配設されているとともに、前記第1および第2の半導体素子接続パッドに半田バンプが溶着されて成る配線基板であって、前記第2の半導体素子接続パッドに溶着された半田バンプの体積が前記第1の半導体素子接続パッドに溶着された半田バンプの体積よりも小さいことを特徴とする配線基板。
- 前記第2の半導体素子接続パッドに溶着された半田バンプの体積が前記第1の半導体素子接続パッドに溶着された半田バンプの体積よりも5〜20%小さいことを特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010185802A JP5461342B2 (ja) | 2010-08-23 | 2010-08-23 | 配線基板 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2010185802A JP5461342B2 (ja) | 2010-08-23 | 2010-08-23 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012044080A true JP2012044080A (ja) | 2012-03-01 |
JP5461342B2 JP5461342B2 (ja) | 2014-04-02 |
Family
ID=45900028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010185802A Active JP5461342B2 (ja) | 2010-08-23 | 2010-08-23 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5461342B2 (ja) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637143A (ja) * | 1992-07-15 | 1994-02-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JPH07263449A (ja) * | 1994-03-18 | 1995-10-13 | Hitachi Ltd | 半導体装置及びその製法 |
JPH09172020A (ja) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | 半導体装置 |
JP2007281369A (ja) * | 2006-04-11 | 2007-10-25 | Shinko Electric Ind Co Ltd | 半田接続部の形成方法、配線基板の製造方法、および半導体装置の製造方法 |
JP2008140868A (ja) * | 2006-11-30 | 2008-06-19 | Toppan Printing Co Ltd | 多層配線基板および半導体装置 |
JP2008258380A (ja) * | 2007-04-04 | 2008-10-23 | Shinko Electric Ind Co Ltd | 半導体装置およびそれに用いる配線基板 |
WO2010079542A1 (ja) * | 2009-01-07 | 2010-07-15 | パナソニック株式会社 | 半導体装置及びその製造方法 |
-
2010
- 2010-08-23 JP JP2010185802A patent/JP5461342B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637143A (ja) * | 1992-07-15 | 1994-02-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JPH07263449A (ja) * | 1994-03-18 | 1995-10-13 | Hitachi Ltd | 半導体装置及びその製法 |
JPH09172020A (ja) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | 半導体装置 |
JP2007281369A (ja) * | 2006-04-11 | 2007-10-25 | Shinko Electric Ind Co Ltd | 半田接続部の形成方法、配線基板の製造方法、および半導体装置の製造方法 |
JP2008140868A (ja) * | 2006-11-30 | 2008-06-19 | Toppan Printing Co Ltd | 多層配線基板および半導体装置 |
JP2008258380A (ja) * | 2007-04-04 | 2008-10-23 | Shinko Electric Ind Co Ltd | 半導体装置およびそれに用いる配線基板 |
WO2010079542A1 (ja) * | 2009-01-07 | 2010-07-15 | パナソニック株式会社 | 半導体装置及びその製造方法 |
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