JP2011518440A - ２つのマスクを用いる磁気トンネル接合素子の製造方法 - Google Patents

２つのマスクを用いる磁気トンネル接合素子の製造方法 Download PDF

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Publication number
JP2011518440A
JP2011518440A JP2011505157A JP2011505157A JP2011518440A JP 2011518440 A JP2011518440 A JP 2011518440A JP 2011505157 A JP2011505157 A JP 2011505157A JP 2011505157 A JP2011505157 A JP 2011505157A JP 2011518440 A JP2011518440 A JP 2011518440A
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electrode
mtj
layer
mask
configuration
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Japanese (ja)
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カン、スン・エイチ．
リ、シャ
グ、シチン
ノーウォク、マシュー・エム．
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
JP2011505157A 2008-04-18 2009-04-15 ２つのマスクを用いる磁気トンネル接合素子の製造方法 Withdrawn JP2011518440A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US4616708P 2008-04-18 2008-04-18
US61/046,167 2008-04-18
US12/405,461 2009-03-17
US12/405,461 US8125040B2 (en) 2008-04-18 2009-03-17 Two mask MTJ integration for STT MRAM
PCT/US2009/040612 WO2009129283A1 (en) 2008-04-18 2009-04-15 Manufacturing method of a magnetic tunnel junction element using two masks

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JP2014077077A Division JP2014160839A (ja) 2008-04-18 2014-04-03 ２つのマスクを用いる磁気トンネル接合素子の製造方法

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JP2011518440A true JP2011518440A (ja) 2011-06-23

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JP2011505157A Withdrawn JP2011518440A (ja) 2008-04-18 2009-04-15 ２つのマスクを用いる磁気トンネル接合素子の製造方法
JP2014077077A Withdrawn JP2014160839A (ja) 2008-04-18 2014-04-03 ２つのマスクを用いる磁気トンネル接合素子の製造方法
JP2015029705A Pending JP2015144287A (ja) 2008-04-18 2015-02-18 ２つのマスクを用いる磁気トンネル接合素子の製造方法

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JP2014077077A Withdrawn JP2014160839A (ja) 2008-04-18 2014-04-03 ２つのマスクを用いる磁気トンネル接合素子の製造方法
JP2015029705A Pending JP2015144287A (ja) 2008-04-18 2015-02-18 ２つのマスクを用いる磁気トンネル接合素子の製造方法

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US (1) US8125040B2 (enExample)
EP (2) EP2800159A1 (enExample)
JP (3) JP2011518440A (enExample)
KR (1) KR101200008B1 (enExample)
CN (1) CN102007614B (enExample)
TW (1) TW201007730A (enExample)
WO (1) WO2009129283A1 (enExample)

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JP2011238679A (ja) * 2010-05-07 2011-11-24 Fujitsu Semiconductor Ltd 磁気記憶装置の製造方法及び磁気記憶装置
JP2013513255A (ja) * 2009-12-08 2013-04-18 クアルコム，インコーポレイテッド 磁気トンネル接合デバイス
JP2017510995A (ja) * 2014-04-02 2017-04-13 クアルコム，インコーポレイテッド マルチステップ磁気トンネル接合（ｍｔｊ）エッチングのための置換導電性ハードマスク
JP2023086085A (ja) * 2021-12-09 2023-06-21 台湾積體電路製造股▲ふん▼有限公司 磁気トンネル接合装置及びその形成方法

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US8547736B2 (en) 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
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US8921959B2 (en) * 2011-07-26 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM device and fabrication method thereof
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CN104882538B (zh) * 2014-02-28 2017-09-22 中芯国际集成电路制造(上海)有限公司 环型磁性随机存取存储器单元结构的制造方法
KR102149195B1 (ko) 2014-03-04 2020-08-28 에스케이하이닉스 주식회사 전자 장치 및 그 제조 방법
CN105206741B (zh) * 2014-06-23 2019-02-12 中芯国际集成电路制造(上海)有限公司 磁性隧道结单元和制备磁性隧道结单元的方法
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US10134981B1 (en) 2017-10-20 2018-11-20 Headway Technologies, Inc. Free layer sidewall oxidation and spacer assisted magnetic tunnel junction (MTJ) etch for high performance magnetoresistive random access memory (MRAM) devices
US10879077B2 (en) 2017-10-30 2020-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Planarization apparatus and planarization method thereof
US10325639B2 (en) 2017-11-20 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Initialization process for magnetic random access memory (MRAM) production
US10153427B1 (en) 2017-12-28 2018-12-11 Headway Technologies, Inc. Magnetic tunnel junction (MTJ) performance by introducing oxidants to methanol with or without noble gas during MTJ etch
CN109994476B (zh) * 2017-12-29 2021-03-16 上海磁宇信息科技有限公司 一种制备磁性随机存储器阵列单元的方法
US10475991B2 (en) 2018-02-22 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of large height top metal electrode for sub-60nm magnetoresistive random access memory (MRAM) devices
US10790002B2 (en) 2018-06-21 2020-09-29 Samsung Electronics Co., Ltd. Giant spin hall-based compact neuromorphic cell optimized for differential read inference
US11296277B2 (en) 2018-10-16 2022-04-05 Samsung Electronics Co., Ltd. Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same
US10971176B2 (en) 2019-02-21 2021-04-06 International Business Machines Corporation Tunnel magnetoresistive sensor with adjacent gap having chromium alloy seed layer and refractory material layer
US11805704B2 (en) * 2020-05-08 2023-10-31 International Business Machines Corporation Via interconnects for a magnetoresistive random-access memory device
US11569442B2 (en) 2020-06-17 2023-01-31 International Business Machines Corporation Dielectric retention and method of forming memory pillar

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
JP2013513255A (ja) * 2009-12-08 2013-04-18 クアルコム，インコーポレイテッド 磁気トンネル接合デバイス
JP2014103420A (ja) * 2009-12-08 2014-06-05 Qualcomm Inc 磁気トンネル接合デバイス
JP2011238679A (ja) * 2010-05-07 2011-11-24 Fujitsu Semiconductor Ltd 磁気記憶装置の製造方法及び磁気記憶装置
JP2017510995A (ja) * 2014-04-02 2017-04-13 クアルコム，インコーポレイテッド マルチステップ磁気トンネル接合（ｍｔｊ）エッチングのための置換導電性ハードマスク
JP2023086085A (ja) * 2021-12-09 2023-06-21 台湾積體電路製造股▲ふん▼有限公司 磁気トンネル接合装置及びその形成方法
JP7476271B2 (ja) 2021-12-09 2024-04-30 台湾積體電路製造股▲ふん▼有限公司 磁気トンネル接合装置及びその形成方法
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Publication number Publication date
KR20110002864A (ko) 2011-01-10
US20090261437A1 (en) 2009-10-22
JP2015144287A (ja) 2015-08-06
WO2009129283A1 (en) 2009-10-22
CN102007614A (zh) 2011-04-06
KR101200008B1 (ko) 2012-11-12
US8125040B2 (en) 2012-02-28
JP2014160839A (ja) 2014-09-04
EP2277211B1 (en) 2014-10-08
CN102007614B (zh) 2014-07-16
EP2800159A1 (en) 2014-11-05
EP2277211A1 (en) 2011-01-26
TW201007730A (en) 2010-02-16

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