JP2011512029A - 溶液処理型高移動度無機薄膜トランジスタ - Google Patents
溶液処理型高移動度無機薄膜トランジスタ Download PDFInfo
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- JP2011512029A JP2011512029A JP2010545028A JP2010545028A JP2011512029A JP 2011512029 A JP2011512029 A JP 2011512029A JP 2010545028 A JP2010545028 A JP 2010545028A JP 2010545028 A JP2010545028 A JP 2010545028A JP 2011512029 A JP2011512029 A JP 2011512029A
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- ITMCEJHCFYSIIV-UHFFFAOYSA-M triflate Chemical compound [O-]S(=O)(=O)C(F)(F)F ITMCEJHCFYSIIV-UHFFFAOYSA-M 0.000 claims description 2
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- BSHXYEOKVHYGGK-UHFFFAOYSA-N trichloro(1-trichlorosilyloctyl)silane Chemical compound CCCCCCCC([Si](Cl)(Cl)Cl)[Si](Cl)(Cl)Cl BSHXYEOKVHYGGK-UHFFFAOYSA-N 0.000 description 1
- CLXMTJZPFVPWAX-UHFFFAOYSA-N trichloro-[dichloro(trichlorosilyloxy)silyl]oxysilane Chemical compound Cl[Si](Cl)(Cl)O[Si](Cl)(Cl)O[Si](Cl)(Cl)Cl CLXMTJZPFVPWAX-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/0256—Selenides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
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- Formation Of Insulating Films (AREA)
Abstract
【選択図】 図1
Description
Ids=(W/2L)μCi(Vg−Vth)2 (1)
ここで、Lはチャネルの長さ、Wはチャネルの幅、Ciは誘電体膜の単位面積当りのキャパシタンス、μは半導体の電界効果移動度、Vthは閾値電圧、Vgはゲート電圧である。図2には代表的な転移及び出力I−Vプロットを示す。SiO2におけるデバイスを制御するために、CdSe膜は真空中及び雰囲気中で300℃で5分間アニール処理し、平均μFET値〜1.3(±1.1)cm2/Vs、最大μFET値〜3.0cm2/Vsを示すTFTを作成した。同じ条件の下で400℃でアニール処理したCdSe膜は、平均μFET値〜4.0(±2.0)cm2/Vs、最大μFET値〜6.7cm2/Vsを示すデバイスを提供する(図2A及び図2C)。400℃でアニール処理したデバイスの平均値Vth、サブ閾値勾配(S)、及びSiO2に基づくIon/Ioffはそれぞれ+25V、3.4V/dec及び106であった。これらのμFET値は、Alソース及びドレーン電極を備えたCBD CdSe/SiO2について前に述べた値より低い大きさの程度である。これらはnチャネルTFTであるので、Al対Auの低い仕事関数は、金属−半導体接触抵抗を低減でき、電子注入を高め、従って実測移動度を高める。それにもかかわらず、これらの移動度値は、1cm2/Vsの最大移動度を示したインクジェットで形成したCdSe膜を用いて製作したTFTの移動度より大きい。半導体成長領域は、次に、Ion/Ioff比及びデバイスの歩留まりを高めるために、ポリスチレン又はポリメチルメタクリル酸塩マスキングでパターン形成した。この方法は、適度な移動度をもってSiO2/CdSe TFT Ion/Ioff比を107に高め、そしてデバイスの歩留まりを>70%に高める。異なるチャネルの長さ/幅を利用する場合には、実測ドレーン電流はデバイスの寸法と線形に対応し、卓越した膜の一様性及び低い寄生漏れ電流を示す。
[実施例1a]
試薬CdCl2、Se、及びNa2SO3は、Aldrich Chemicals社から購入し、さらに精製することなく使用した。水性アンモニア(28〜30%)溶液はMallinckrodt Baker社から購入した。全ての堆積段階で使用した水はMilliporeナノ純水システムを用いて精製した。Na2SeSO3溶液は、0.2M(7.9ミリモル)のNa2SO3溶液40mL中の0.37g(4.7ミリモル)のSeを用い、水槽で1.5時間60℃に加熱してNa2SeSO3を作った。その後、溶解してないSeはろ紙でろ過して除去し、結果として、CBD溶液において用いられるのろ液を得た。CBD溶液は20mLの〜0.1M水性CdCl2、6.0mLの濃縮NH4OH、及び20mLの〜0.1M水性Na2SeSO3溶液から作った。その後この溶液は水槽を用いて80℃に加熱した。溶液がオレンジ色になった後、基板(7×2.5cm)をガラスホルダーに装着し、そしてCBD溶液に浸漬した。基板は最初に1分間溶液に入れ、そして脱イオン水で洗浄し、この段階を二回繰り返した。これらの初期表面状態調節段階の後、基板を再び〜15分間溶液に浸漬した。膜の堆積後、基板を新鮮な脱イオン水で5分間にわたって三回超音波処理し、その後空気乾燥してからアニール処理した。代表的なCdSe膜の厚さは160〜200nmであった。
[実施例1b]
[実施例2]
2−メトキシ−エタノール中、酢酸亜鉛(Zn(OAC)2)の0.1M溶液を作った。Zn(OAC)2と1:1の比率で溶液に化合物2−アミノ−エタノールを添加し、Zn(OAC)2の溶解度を高めて溶液濃度を0.1Mにした。また2−メトキシ−エタノール中、InCl3の0.1M溶液を作った。0.5mlのInCl3溶液と0.5mlのZn(OAC)2溶液とを混ぜてスピンキャスティング溶液を作った。そして前駆体膜を1500rpmでスピンキャストした。その後、前駆体膜を180℃で10分間予備アニール処理し、そしてZIOの第2の被覆をスピンキャストし、予備アニール処理し、その後ZIO膜を400℃で30分間アニール処理した。
[実施例3]
原子間力顕微鏡画像を、シリコン片持ばりを備えたIEOL−5200走査型プローブ顕微鏡を用いてタッピングモードで記録した。WinSPMソフトウエアを用いて像を処理した。Iencor model P10表面プロフィルメータを用いて膜の厚さを測定した。Niフィルタ付きCuKα放射線を用いたRigaku DMAX−A回折計で、CdSe膜の広角θ−2θX線回折(WAXRD)を行った。電気的測定は、ローカル的に書き込んだLABVIEWプログラム及び汎用インターフェースバス通信を用いたKeithley6430Sub−Femtoamp Remoteソースメータ及びKeithley 2400ソースメータで行った。インピーダンス分光分析測定はHewlett−Packard 4192Aインピーダンス分光計で行った。TFT特性決定は雰囲気条件の下で秘密に行った。飽和移動度は本文中の式(1)を用いて評価した。飽和移動度の計算は、デバイス転移プロットから誘導したIds 1/2のVGに対する勾配で行った。底部ゲート/頂部接点TFTアーキテクチュアを利用した。Au(50nm)ソース/ドレーン接点は、所望のチャネル寸法にするためにシャドーマスクを介して熱的蒸発によって堆積した。SAND膜は、上記の組み込まれた参照文献に記載されたような従来知られた方法に従って堆積した。
[実施例4a]
[実施例4b]
[実施例4c]
[実施例4d]
[実施例4e]
[実施例5]
[実施例6]
[実施例7]
[実施例7a]
[実施例7b]
[実施例7c]
[実施例7d]
[実施例8]
[実施例9]
アニール温度が200℃から250℃に上昇するにつれて移動度が増加することが観察された(図17A〜図17D及び図17F)。さらに、特に、移動度は、200℃での0.04cm2/Vsから250℃での2.11cm2/Vsに徐々に増加する。値は下記表9にまとめて示す。
[実施例10]
Claims (48)
- 少なくとも部分的に溶解できる無機半導体成分を含み、前記無機半導体成分が、金属セレン化物、硫化物、酸化物、テルル化物、プニクチド、リン化物、窒化物、炭化物、ヒ化物、及びそれらの組合せから選択された化合物を含んでいて、金属が12族〜15族金属から選択される、第1流体媒体を作ること、
前記第1流体媒体を基板成分と接触させること、
前記無機半導体成分をアニール処理して半導体膜を形成すること、
少なくとも部分的に溶解できる誘電体成分を含む第2流体媒体を作ること、及び
前記誘電体成分を前記無機半導体膜に結合すること
を含む薄膜トランジスタデバイス製造用の溶液相方法。 - 前記第1流体媒体と接触する前に、薄膜組成物を作るように基板成分に前記第2流体媒体を堆積することを含む請求項1記載の方法。
- 前記堆積処理が印刷処理又はスピンコート処理を含む請求項2記載の方法。
- 前記薄膜組成物が第1流体媒体内に配されることを特徴とする請求項2記載の方法。
- 前記半導体成分が、前記第1流体媒体内に少なくとも部分的に溶解できる前駆体試薬の反応生成物である請求項4記載の方法。
- 前記半導体成分が金属セレン化物である請求項5記載の方法。
- 半導体膜上に前記第2流体媒体を堆積することを含む請求項1記載の方法。
- 前記堆積処理が印刷処理又はスピンコート処理を含む請求項7記載の方法。
- 前記第1流体媒体の前記基板成分との接触が印刷法及びキャスティング法から選択した処理法を含む請求項1記載の方法。
- 前記接触が、インクジェット印刷法、スクリーン印刷法、グラビア印刷法、オフセット印刷法、パッド印刷法、リソグラフ印刷法、フレキソ印刷法、マイクロコンタクト印刷法、スピンコート法、ドロップ成形法、ゾーン成形法、浸漬コーティング法、ナイフコーティング法、及び噴霧法から選択した処理法を含む請求項1記載の方法。
- 前記半導体成分が、前記第1流体媒体内に少なくとも部分的に溶解できる前駆体試薬の反応生成物である請求項9記載の方法。
- 前記第1流体媒体が、溶媒中の塩基及び一つ以上の三価の金属塩を含む請求項11記載の方法。
- 前記第1流体媒体が、一つ以上の金属塩を含み、一つ以上の金属塩の金属がインジウム、スズ、亜鉛及びガリウムから選択される請求項12記載の方法。
- 前記塩基が、エタノールアミン、プロパノールアミン及びジエタノールアミンから選択したアミノアルコールである請求項12記載の方法。
- 前記塩基の前記一つ以上の三価の金属塩に対する比が、約1〜約15である請求項12記載の方法。
- 前記媒体が、二価の金属塩又は四価の金属塩から選択した第2の金属塩を含む請求項12記載の方法。
- 前記塩基と前記一つ以上の金属塩との比が、約1〜約15である請求項16記載の方法。
- 一つ以上の金属塩が、ハロゲン化物、オキサレート、カーボネート、アセテート、ホルメート、プロピオネート、サルファイト、サルフェート、アセチルアセトネート、水酸化物、ニトレート、過塩素酸塩、トリフルオロアセテート、トリフルオロアセチルアセトネート、トリフルオロメタンスルホネート、トシレート、メシレート、及びそれらの水和物から選択される請求項12記載の方法。
- 前記半導体成分が金属酸化物である請求項9記載の方法。
- 前記半導体成分が、400℃以下又は約400℃の温度でアニール処理される請求項9記載の方法。
- 前記半導体成分が、250℃以下又は約250℃の温度でアニール処理される請求項9記載の方法。
- 前記半導体成分が、100℃以下又は約100℃の温度でアニール処理される請求項9記載の方法。
- 前記誘電体成分が無機材料である請求項1記載の方法。
- 前記誘電体成分が、誘電体ポリマーと、π分極可能な部分を含む少なくとも一つの有機双極子層を備える成分とのうちから選択され、前記層がシロキサン結合連鎖で架橋されている請求項1記載の方法。
- 前記誘電体ポリマーが、ポリ(ビニルフェノール)、ポリスチレン、ポリ(メチルメタクリレート)、及びそれらの共重合体から選択される請求項24記載の方法。
- 前記誘電体成分が、少なくとも一つの前記双極子層にシリコン−酸素結合で結合した炭化水素層を含む請求項24記載の方法。
- 前記誘電体成分が、少なくとも一つの前記双極子層にシリコン−酸素結合で結合した少なくとも一つのシロキサンキャッピング層を含む請求項26記載の方法。
- 前記シロキサンキャッピング層の一つが、一つの前記双極子層と一つの前記炭化水素層との間にあり、シリコン−酸素結合で前記層の各々に結合される請求項27記載の方法。
- 前記双極子層が非線形光学発色団を含んでいる請求項24記載の方法。
- 前記発色団がスチルバゾリウム部分を含んでいる請求項29記載の方法。
- 前記誘電体成分が、実質的に透明な基板に結合される請求項24記載の方法。
- デバイスが透明な薄膜トランジスタである請求項31記載の方法。
- 基板成分に結合した誘電体成分を備えるデバイス構造を作ること、
前記半導体成分は金属セレン化物、硫化物、酸化物、テルル化物、プニクチド、リン化物、窒化物、炭化物、ヒ化物、及びそれらの組合せから選択された化合物を含んでいる無機半導体成分を含み、前記金属が12族〜15族金属から選択される、流体媒体を作ること、及び
前記半導体成分を前記誘電体成分に活性結合するのに少なくとも部分的に十分であるように前記流体媒体を前記デバイス構造と接触させること
を含むトランジスタデバイスの製造方法。 - 前記接触が印刷法及びキャスティング法から選択した処理法を含む請求項33記載の方法。
- 前記接触が、インクジェット印刷法、スクリーン印刷法、グラビア印刷法、オフセット印刷法、パッド印刷法、リソグラフ印刷法、フレキソ印刷法、マイクロコンタクト印刷法、スピンコート法、ドロップ成形法、ゾーン成形法、浸漬コーティング法、ナイフコーティング法、及び噴霧法から選択した処理法を含む請求項34記載の方法。
- 誘電体成分及び誘電体成分に結合した無機半導体成分を有し、前記結合した半導体成分が、前記誘電体成分と前記無機半導体成分を含む流体媒体とを接触させる方法により得ることができ、前記半導体成分が、金属セレン化物、硫化物、酸化物、テルル化物、プニクチド、リン化物、窒化物、炭化物、ヒ化物、及びそれらの組合せから選択した化合物を含み、前記金属が12族〜15族金属から選択され、前記接触が、前記半導体成分を前記誘電体成分に活性結合するのに少なくとも部分的に十分であること
を特徴とする薄膜トランジスタデバイス。 - 前記半導体成分が、400℃以下又は約400℃の温度でアニール処理される請求項36記載のデバイス。
- 前記誘電体成分が、溶液相処理法で得られる請求項36記載のデバイス。
- 前記誘電体成分が無機材料である請求項38記載のデバイス。
- 前記誘電体成分が、誘電体ポリマーと、π分極可能な部分を含む少なくとも一つの有機双極子層を備える成分とのうちから選択され、前記層がシロキサン結合連鎖で架橋されている請求項38記載のデバイス。
- 前記誘電体ポリマーが、ポリ(ビニルフェノール)、ポリスチレン、及びそれらの共重合体から選択される請求項40記載のデバイス。
- 前記誘電体成分が、少なくとも一つの前記双極子層にシリコン−酸素結合で結合した炭化水素層を含む請求項40記載のデバイス。
- 前記誘電体成分が、少なくとも一つの前記双極子層にシリコン−酸素結合で結合した少なくとも一つのシロキサンキャッピング層を含む請求項42記載のデバイス。
- 前記シロキサンキャッピング層の一つが、一つの前記双極子層と一つの前記炭化水素層との間にあり、シリコン−酸素結合で前記層の各々に結合される請求項43記載のデバイス。
- 前記双極子層が非線形光学発色団を含んでいる請求項36記載のデバイス。
- 前記発色団がスチルバゾリウム部分を含んでいる請求項45記載のデバイス。
- 前記誘電体成分が、実質的に透明な基板に結合される請求項36記載のデバイス。
- デバイスが透明な薄膜トランジスタである請求項47記載のデバイス。
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US8513646B2 (en) | 2013-08-20 |
JP5647900B2 (ja) | 2015-01-07 |
US20090206341A1 (en) | 2009-08-20 |
KR101614789B1 (ko) | 2016-04-22 |
WO2009097150A3 (en) | 2010-10-14 |
EP2245669A4 (en) | 2015-05-06 |
US20120223314A1 (en) | 2012-09-06 |
US8017458B2 (en) | 2011-09-13 |
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