JP2011508329A5 - - Google Patents

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Publication number
JP2011508329A5
JP2011508329A5 JP2010540184A JP2010540184A JP2011508329A5 JP 2011508329 A5 JP2011508329 A5 JP 2011508329A5 JP 2010540184 A JP2010540184 A JP 2010540184A JP 2010540184 A JP2010540184 A JP 2010540184A JP 2011508329 A5 JP2011508329 A5 JP 2011508329A5
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JP
Japan
Prior art keywords
memory
interface
bridge circuit
storage device
external storage
Prior art date
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Granted
Application number
JP2010540184A
Other languages
English (en)
Japanese (ja)
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JP2011508329A (ja
JP4972212B2 (ja
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Publication date
Priority claimed from US12/333,854 external-priority patent/US7870323B2/en
Application filed filed Critical
Publication of JP2011508329A publication Critical patent/JP2011508329A/ja
Publication of JP2011508329A5 publication Critical patent/JP2011508329A5/ja
Application granted granted Critical
Publication of JP4972212B2 publication Critical patent/JP4972212B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010540184A 2007-12-26 2008-12-23 ブリッジ回路 Active JP4972212B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1667007P 2007-12-26 2007-12-26
US61/016,670 2007-12-26
US12/333,854 2008-12-12
US12/333,854 US7870323B2 (en) 2007-12-26 2008-12-12 Bridge circuit for interfacing processor to main memory and peripherals
PCT/IB2008/003613 WO2009081271A1 (en) 2007-12-26 2008-12-23 Bridge circuit interfacing a processor to external devices via memory address mapping

Publications (3)

Publication Number Publication Date
JP2011508329A JP2011508329A (ja) 2011-03-10
JP2011508329A5 true JP2011508329A5 (enExample) 2012-02-16
JP4972212B2 JP4972212B2 (ja) 2012-07-11

Family

ID=40799980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010540184A Active JP4972212B2 (ja) 2007-12-26 2008-12-23 ブリッジ回路

Country Status (6)

Country Link
US (1) US7870323B2 (enExample)
EP (1) EP2225653A1 (enExample)
JP (1) JP4972212B2 (enExample)
CN (1) CN101911035B (enExample)
TW (1) TWI451262B (enExample)
WO (1) WO2009081271A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013028827A1 (en) * 2011-08-24 2013-02-28 Rambus Inc. Methods and systems for mapping a peripheral function onto a legacy memory interface
US11048410B2 (en) 2011-08-24 2021-06-29 Rambus Inc. Distributed procedure execution and file systems on a memory interface
US9098209B2 (en) 2011-08-24 2015-08-04 Rambus Inc. Communication via a memory interface
JP5876017B2 (ja) * 2013-08-30 2016-03-02 株式会社ソニー・コンピュータエンタテインメント 周辺機器制御装置および情報処理装置
JP6924026B2 (ja) * 2016-12-19 2021-08-25 シナプティクス インコーポレイテッド 半導体装置、ヒューマンインターフェース装置及び電子機器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822550A (en) * 1994-12-22 1998-10-13 Texas Instruments Incorporated Split data path fast at-bus on chip circuits systems and methods
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
JP3061106B2 (ja) * 1996-02-28 2000-07-10 日本電気株式会社 バスブリッジおよびそれを備えた計算機システム
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6145029A (en) * 1998-03-13 2000-11-07 Compaq Computer Corporation Computer system with enhanced docking support
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20030191730A1 (en) * 2002-04-05 2003-10-09 Compaq Information Technologies Group, L.P. Unobtrusive rule-based computer usage enhancement system
US20050177829A1 (en) * 2003-10-10 2005-08-11 Vipul Vishwanath Method of applying constraints against discovered attributes in provisioning computers
US7293153B2 (en) * 2003-10-14 2007-11-06 Freescale Semiconductor, Inc. Method and system for direct access to a non-memory mapped device memory
JP4472426B2 (ja) * 2004-05-24 2010-06-02 パナソニック株式会社 バスブリッジ回路
JP2007200169A (ja) * 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法

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