TWI451262B - 橋接電路 - Google Patents

橋接電路 Download PDF

Info

Publication number
TWI451262B
TWI451262B TW097150740A TW97150740A TWI451262B TW I451262 B TWI451262 B TW I451262B TW 097150740 A TW097150740 A TW 097150740A TW 97150740 A TW97150740 A TW 97150740A TW I451262 B TWI451262 B TW I451262B
Authority
TW
Taiwan
Prior art keywords
memory
interface
address
bridge circuit
control module
Prior art date
Application number
TW097150740A
Other languages
English (en)
Chinese (zh)
Other versions
TW200935239A (en
Inventor
Matsumoto Munehisa
Kuno Shinichiro
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200935239A publication Critical patent/TW200935239A/zh
Application granted granted Critical
Publication of TWI451262B publication Critical patent/TWI451262B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
TW097150740A 2007-12-26 2008-12-25 橋接電路 TWI451262B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1667007P 2007-12-26 2007-12-26
US12/333,854 US7870323B2 (en) 2007-12-26 2008-12-12 Bridge circuit for interfacing processor to main memory and peripherals

Publications (2)

Publication Number Publication Date
TW200935239A TW200935239A (en) 2009-08-16
TWI451262B true TWI451262B (zh) 2014-09-01

Family

ID=40799980

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097150740A TWI451262B (zh) 2007-12-26 2008-12-25 橋接電路

Country Status (6)

Country Link
US (1) US7870323B2 (enExample)
EP (1) EP2225653A1 (enExample)
JP (1) JP4972212B2 (enExample)
CN (1) CN101911035B (enExample)
TW (1) TWI451262B (enExample)
WO (1) WO2009081271A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9098209B2 (en) 2011-08-24 2015-08-04 Rambus Inc. Communication via a memory interface
US11048410B2 (en) 2011-08-24 2021-06-29 Rambus Inc. Distributed procedure execution and file systems on a memory interface
WO2013028854A1 (en) 2011-08-24 2013-02-28 Rambus Inc. Methods and systems for mapping a peripheral function onto a legacy memory interface
JP5876017B2 (ja) * 2013-08-30 2016-03-02 株式会社ソニー・コンピュータエンタテインメント 周辺機器制御装置および情報処理装置
JP6924026B2 (ja) * 2016-12-19 2021-08-25 シナプティクス インコーポレイテッド 半導体装置、ヒューマンインターフェース装置及び電子機器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6145029A (en) * 1998-03-13 2000-11-07 Compaq Computer Corporation Computer system with enhanced docking support

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822550A (en) * 1994-12-22 1998-10-13 Texas Instruments Incorporated Split data path fast at-bus on chip circuits systems and methods
JP3061106B2 (ja) * 1996-02-28 2000-07-10 日本電気株式会社 バスブリッジおよびそれを備えた計算機システム
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20030191730A1 (en) * 2002-04-05 2003-10-09 Compaq Information Technologies Group, L.P. Unobtrusive rule-based computer usage enhancement system
US20050177829A1 (en) * 2003-10-10 2005-08-11 Vipul Vishwanath Method of applying constraints against discovered attributes in provisioning computers
US7293153B2 (en) * 2003-10-14 2007-11-06 Freescale Semiconductor, Inc. Method and system for direct access to a non-memory mapped device memory
JP4472426B2 (ja) * 2004-05-24 2010-06-02 パナソニック株式会社 バスブリッジ回路
JP2007200169A (ja) * 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6145029A (en) * 1998-03-13 2000-11-07 Compaq Computer Corporation Computer system with enhanced docking support

Also Published As

Publication number Publication date
US20090172238A1 (en) 2009-07-02
CN101911035A (zh) 2010-12-08
TW200935239A (en) 2009-08-16
WO2009081271A1 (en) 2009-07-02
JP4972212B2 (ja) 2012-07-11
CN101911035B (zh) 2014-02-19
EP2225653A1 (en) 2010-09-08
JP2011508329A (ja) 2011-03-10
US7870323B2 (en) 2011-01-11

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MM4A Annulment or lapse of patent due to non-payment of fees