WO2018113026A1 - 接口兼容电路 - Google Patents

接口兼容电路 Download PDF

Info

Publication number
WO2018113026A1
WO2018113026A1 PCT/CN2016/113538 CN2016113538W WO2018113026A1 WO 2018113026 A1 WO2018113026 A1 WO 2018113026A1 CN 2016113538 W CN2016113538 W CN 2016113538W WO 2018113026 A1 WO2018113026 A1 WO 2018113026A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
interface
sata
main control
control circuit
Prior art date
Application number
PCT/CN2016/113538
Other languages
English (en)
French (fr)
Inventor
李祥明
钟伟文
Original Assignee
广州炒米信息科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州炒米信息科技有限公司 filed Critical 广州炒米信息科技有限公司
Publication of WO2018113026A1 publication Critical patent/WO2018113026A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3802—Harddisk connected to a computer port

Definitions

  • the present invention relates to the field of computer interface technologies, and in particular, to an interface compatible circuit.
  • SATA Serial Advanced Technology Attachment
  • SATA Serial Advanced Technology Attachment
  • the new hard disk interface type of Technology Attachment is named after the serial transmission of data.
  • the SATA bus uses an embedded clock signal and has a stronger error correction capability. Compared with the past, the biggest difference is that it can check the transmission instructions (not just the data). If the error is found, it will be automatically corrected. This is very large. To a certain extent, the reliability of data transmission is improved, and the structure is simple and the hot plugging is supported.
  • the mSATA interface (mini-SATA, mini version SATA interface) is a new type of interface standard released by the SATA international interface standard organization.
  • the solid state drive with mSATA interface has a wide range of applications in the fields of tablet computers, mobile phones, set-top boxes and printers.
  • a logical interface is not compatible with an access device that recognizes a SATA interface and an access device that is an mSATA interface, and is designed separately for an access device of a SATA interface and an access device of an mSATA interface, so that space is occupied. Large, and occupy system resources, the cost is also high.
  • An interface compatible circuit comprising a SATA connector circuit, an mSATA connector circuit, a logic interface of a main control circuit, and an access device type for identifying a logical interface of the main control circuit and configured to be a main control circuit of a corresponding read/write mode, wherein
  • the device types include a mechanical hard disk with a SATA interface, a mechanical solid state hybrid hard disk with a SATA interface, a solid state hard disk with a SATA interface, and a solid state hard disk with an mSATA interface;
  • the SATA connector circuit and the mSATA connector circuit are respectively connected with the logic interface of the main control circuit, and the logic interface of the main control circuit is connected with the main control circuit;
  • the corresponding read and write modes are sequential read and cache write; when the access device type is a mechanical solid state hybrid hard disk of the SATA interface, the corresponding read and write settings are set.
  • the mode is sequential reading and load balancing writing.
  • the access device type is a solid state hard disk with a SATA interface or a solid state hard disk with an mSATA interface, the corresponding read and write modes are random read and load balanced write.
  • the above interface compatible circuit includes a SATA connector circuit, an mSATA connector circuit, a main control circuit logic interface, and an access device type for identifying a logical interface of the main control circuit and is set to a corresponding read/write mode main control circuit; a SATA connector circuit And the mSATA connector circuit is respectively connected with the logic interface of the main control circuit, and the logical interface of the main control circuit is connected with the main control circuit.
  • the access device type is a mechanical hard disk of the SATA interface
  • the corresponding read and write modes are set to read sequentially.
  • the corresponding read/write mode is set to read sequentially and load balance is written; when the access device type is SATA interface solid state hard disk or mSATA interface In the case of a solid state drive, the corresponding read/write mode is random read and load balanced write.
  • the compatible circuit of the interface is compatible with the access device that recognizes the SATA interface and the access device of the mSATA interface, and is set according to the type of the access device.
  • the corresponding read and write mode does not need to separately design the access device for identifying the SATA interface and the access for identifying the mSATA interface. Prepared logical interface control circuit, so that small space, and saving system resources, reducing costs.
  • 1 is a schematic structural diagram of an interface compatible circuit in an embodiment
  • FIG. 2 is a circuit schematic diagram of a SATA connector circuit in an interface compatible circuit in an embodiment
  • FIG. 3 is a circuit schematic diagram of an mSATA connector circuit in an interface compatible circuit in one embodiment.
  • the hard disk interface is the connection between the hard disk and the host system. It is used to transfer data between the hard disk cache and the host memory. From a holistic point of view, the hard disk interface is divided into IDE (Integrated Drive Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), and optical fiber. There are five types of channels and SAS (Serial Attached SCSI). IDE interface hard disk is mostly used in household products, and is also partially applied to servers; SCSI interface is hard Disks are mainly used in the server market, while Fibre Channel is only expensive on high-end servers. SATA is a new type of hard disk interface, which is in the market stage and has broad prospects in the home market.
  • the mSATA interface (mini-SATA, mini version SATA interface) is a new type of interface standard released by the SATA international interface standard organization.
  • the solid state drive with mSATA interface has a wide range of applications in the fields of tablet computers, mobile phones, set-top boxes and printers.
  • the mechanical hard disk is a traditional ordinary hard disk, which mainly includes a disk, a magnetic head, a disk rotating shaft and a control motor, a head controller, a data converter, an interface, a cache, and the like.
  • the magnetic head can move along the radial direction of the disc, and with the high-speed rotation of the disc thousands of revolutions per minute, the magnetic head can be positioned at a specified position of the disc for reading and writing data.
  • the information is written to the magnetic disk by the magnetic flow to change the polarity by the electromagnetic flow.
  • the information can be read by the opposite way. As a precision device, the dust is its enemy and must be completely sealed. All the discs in the mechanical hard disk are mounted on a rotating shaft, and each disc is parallel.
  • the mechanical hard disk has a magnetic head on the storage surface of each disc, and the distance between the magnetic head and the disc is longer than the hair.
  • the diameter of the wire is still small, and all the heads are connected to a head controller, and the head controller is responsible for the movement of each head.
  • the solid state hard disk is referred to as a solid disk, and the solid state hard disk is made of a solid electronic storage chip array, and includes a control unit and a storage unit (FLASH chip and DRAM chip).
  • SSD Solid State Drives
  • Solid state drives do not have any mechanical parts inside, so that even at high speeds and even with tilting tilt, it will not affect normal use, and can lose data in the event of collisions and shocks. The possibility is minimized.
  • the flash-based solid-state hard disk is the main category of solid-state hard disk. Its internal structure is very simple.
  • the main body of the solid-state hard disk is actually a PCB (Printed Circuit Board) board, and the most basic accessory on this PCB board is control.
  • the main control chip is the brain of the solid-state hard disk. Its role is to properly allocate the load of data on each flash memory chip, and the second is to undertake the entire data transfer, connect the flash memory chip and the external SATA interface.
  • the ability of different masters is very different. There will be very different data processing capabilities, algorithms, and read and write control of flash chips, which will directly lead to a tens of times the performance difference of SSD products.
  • hybrid hard disk is a combination of a solid state hard disk and a general mechanical hard disk.
  • a hybrid hard disk is not a combination of a solid state hard disk and a conventional mechanical hard disk.
  • the hybrid hard disk is a new hard disk based on the traditional mechanical hard disk.
  • NAND flash memory particles are also built in. The granules store data that users frequently access, and can achieve read performance such as SSD solid state hard disk effects.
  • SSHD Solid State Hybrid Drive
  • SSHD Solid State Hybrid Drive
  • an interface compatible circuit includes a SATA connector circuit 100, an mSATA connector circuit 200, a main control circuit logic interface 300, and an access device type that identifies the main control circuit logical interface 300.
  • the main control circuit 400 is configured as a corresponding read/write mode, wherein the access device type includes a mechanical hard disk of a SATA interface, a mechanical solid state hybrid hard disk of a SATA interface, a solid state hard disk of a SATA interface, and a solid state hard disk of an mSATA interface;
  • the SATA connector circuit 100 and the mSATA connector circuit 200 are respectively connected to the main control circuit logic interface 300, and the main control circuit logic interface 300 is connected to the main control circuit 400;
  • the corresponding read and write modes are sequential read and cache write; when the access device type is a mechanical solid state hybrid hard disk of the SATA interface, the corresponding read and write settings are set.
  • the mode is sequential reading and load balancing writing.
  • the access device type is a solid state hard disk with a SATA interface or a solid state hard disk with an mSATA interface, the corresponding read and write modes are random read and load balanced write.
  • the main control circuit can determine the type of the access device of the logical interface of the main control circuit by setting a parameter identifying the type of the access device, for example, 1 means a mechanical hard disk whose access device type is a SATA interface, and 2 represents access.
  • the device is a mechanical solid-state hybrid hard disk with a SATA interface
  • 3 represents a solid-state hard disk with the access device type SATA interface
  • 4 represents a solid-state hard disk with the access device type mSATA interface.
  • the main control circuit detects the parameter identifying the access device type. When 1, it indicates that the current input device is a mechanical hard disk of the SATA interface.
  • the read/write efficiency of the access device is higher and the service life is longer.
  • the mechanical hard disk is a SATA interface
  • the corresponding read/write mode is sequential read and cache write
  • the access device type is a mechanical solid state hybrid hard disk with SATA interface
  • the corresponding read/write mode is set to read sequentially.
  • Load balancing writes when the access device type is a solid state drive of the SATA interface or a solid state drive of the mSATA interface, the corresponding read and write modes are random read and load balanced write.
  • the SATA connector circuit 100 includes a SATA connector, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor.
  • One end of the first capacitor is connected to the first differential receiving pin of the SATA connector, and the other end of the first capacitor is Connecting a first differential receiving pin of the main control circuit; one end of the second capacitor is connected to the second differential receiving pin of the SATA connector, and the other end of the second capacitor is connected to the second differential receiving pin of the main control circuit;
  • the third capacitor One end of the SATA connector a first differential transmission pin, the other end of the third capacitor is connected to the first differential transmission pin of the main control circuit;
  • one end of the fourth capacitor is connected to the second differential transmission pin of the SATA connector, and the other end of the fourth capacitor is connected to the main The second differential transmit pin of the control circuit.
  • the interface compatible circuit further includes a first circuit board, and the SATA connector, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are sequentially disposed on the first circuit board.
  • the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are all 10 nF capacitors.
  • FIG. 2 is a circuit schematic diagram of the SATA connector, wherein the first capacitor is C315, the second capacitor is C316, the third capacitor is C317, and the fourth capacitor is C318.
  • the mSATA connector circuit 200 includes an mSATA connector, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor.
  • One end of the fifth capacitor is connected to the first differential receiving pin of the mSATA connector, and the fifth capacitor is The other end is connected to the first differential receiving pin of the main control circuit;
  • one end of the sixth capacitor is connected to the second differential receiving pin of the mSATA connector, and the other end of the sixth capacitor is connected to the second differential receiving pin of the main control circuit;
  • One end of the seventh capacitor is connected to the first differential transmitting pin of the mSATA connector, and the other end of the seventh capacitor is connected to the first differential transmitting pin of the main control circuit;
  • one end of the eighth capacitor is connected to the second differential transmitting pin of the mSATA connector.
  • the interface compatible circuit further includes a second circuit board, and the mSATA connector, the fifth capacitor, the sixth capacitor, the seventh capacitor, and the eighth capacitor are sequentially disposed on the second circuit board.
  • the fifth capacitor, the sixth capacitor, the seventh capacitor, and the eighth capacitor are all 10 nF capacitors. More specifically, FIG. 3 is a circuit schematic diagram of the mSATA connector, wherein the fifth capacitor is C323, the sixth capacitor is C325, the seventh capacitor is C326, and the eighth capacitor is C327.
  • the main control circuit 400 includes a GL830 main control chip, and the GL830 is a highly compatible, low-cost USB (Universal Serial Bus) 2.0-pair SATA bridge controller.
  • USB Universal Serial Bus
  • the above interface compatible circuit includes a SATA connector circuit, an mSATA connector circuit, a main control circuit logic interface, and an access device type for identifying a logical interface of the main control circuit and is set to a corresponding read/write mode main control circuit; a SATA connector circuit And the mSATA connector circuit is respectively connected with the logic interface of the main control circuit, and the logical interface of the main control circuit is connected with the main control circuit.
  • the access device type is a mechanical hard disk of the SATA interface
  • the corresponding read and write modes are set to read sequentially.
  • the corresponding read and write modes are sequential read and load balanced write; when the access device type is SATA interface solid state hard disk or mSATA interface
  • the corresponding read/write mode is random read and load balanced write.
  • the compatible circuit of the interface is compatible with the access device that recognizes the SATA interface and the access device of the mSATA interface, and according to the type of the access device. Set the corresponding read and write mode, without separately designing the access device for identifying the SATA interface and for identifying The main control circuit logic interface of the access device of the mSATA interface, which occupies small space, saves system resources, and reduces the cost.
  • the solid state hard disk has no mechanical structure and limited number of reading and writing times
  • the solid state of the SATA interface is
  • the time interval for reading and writing data between the hard disk or the mSATA interface is set to 0 to improve the read and write life of the access device. Specifically, this is because when the data needs to be read again, the mechanical hard disk needs to rotate the stopped motor and reach the rated speed before reading and writing data. It takes time to accelerate from 0 to the rated speed. The delay time is said, and the SSD has no speed and can perform read and write operations immediately.
  • the main control circuit in the interface compatible circuit acquires the capacity and the cache value of the access device of the logical interface of the main control circuit, and determines the frequency of the read and write operations according to the size of the capacity and the size of the cache value, and the capacity is large, and the read/write operation is more Frequent; the smaller the cache value, the more frequent the read and write operations to ensure higher read and write efficiency.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Debugging And Monitoring (AREA)

Abstract

一种接口兼容电路，包括SATA连接器电路（100）、mSATA连接器电路（200）、主控电路逻辑接口（300）以及识别主控电路逻辑接口（300）的接入设备类型并设置成相应的读写方式的主控电路（400），其中，接入设备类型包括SATA接口的机械硬盘、SATA接口的机械固态混合硬盘、SATA接口的固态硬盘以及mSATA接口的固态硬盘；SATA连接器电路（100）和mSATA连接器电路（200）分别与主控电路逻辑接口（300）连接，主控电路逻辑接口（300）与主控电路（400）连接；当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式为顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入。

Description

接口兼容电路 技术领域
本发明涉及计算机接口技术领域，特别是涉及一种接口兼容电路。
背景技术
SATA(Serial Advanced Technology Attachment，串行硬盘接口技术)是一种电脑总线，主要用作主板和大量存储设备(如硬盘及光盘驱动器)之间的数据传输，是一种完全不同于并行ATA(Advanced Technology Attachment，硬盘接口技术)的新型硬盘接口类型，由于采用串行方式传输数据而得名。SATA总线使用嵌入式时钟信号，具备了更强的纠错能力，与以往相比其最大的区别在于能对传输指令(不仅仅是数据)进行检查，如果发现错误会自动矫正，这在很大程度上提高了数据传输的可靠性，还具有结构简单、支持热插拔的优点。mSATA接口(mini-SATA，迷你版本SATA接口)是SATA国际接口标准组织发布的一种新型的接口标准，带mSATA接口的固态硬盘在平板计算机、手机、机上盒以及打印机等领域有着广泛的应用。
现有技术至少存在如下问题：一个逻辑接口不能兼容识别处理SATA接口的接入设备和mSATA接口的接入设备，针对SATA接口的接入设备和mSATA接口的接入设备，分开设计，这样占用空间大，且占用系统资源，成本也高。
发明内容
基于此，有必要针对现有技术中一个逻辑接口不能兼容识别处理SATA接口的接入设备和mSATA接口的接入设备，SATA接口的接入设备和mSATA接口的接入设备分开设计，占用空间大，且占用系统资源，成本也高的问题，提供一种可以兼容识别处理SATA接口的接入设备和mSATA接口的接入设备的接口兼容电路。
一种接口兼容电路，包括SATA连接器电路、mSATA连接器电路、主控电路逻辑接口以及识别主控电路逻辑接口的接入设备类型并设置成相应的读写方式的主控电路，其中，接入设备类型包括SATA接口的机械硬盘、SATA接口的机械固态混合硬盘、SATA接口的固态硬盘以及mSATA接口的固态硬盘；
SATA连接器电路和mSATA连接器电路分别与主控电路逻辑接口连接，主控电路逻辑接口与主控电路连接；
当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式为顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入。
上述接口兼容电路，包括SATA连接器电路、mSATA连接器电路、主控电路逻辑接口以及识别主控电路逻辑接口的接入设备类型并设置成相应的读写方式的主控电路；SATA连接器电路和mSATA连接器电路分别与主控电路逻辑接口连接，主控电路逻辑接口与主控电路连接，当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入，该接口兼容电路可兼容识别SATA接口的接入设备和mSATA接口的接入设备，并根据接入设备的类型设置相应的读写方式，无需分开独立设计用于识别SATA接口的接入设备以及用于识别mSATA接口的接入设备的主控电路逻辑接口，这样占用空间小，且节省了系统资源，降低了成本。
附图说明
图1为一个实施例中接口兼容电路的结构示意图；
图2为一个实施例中接口兼容电路中的SATA连接器电路的电路原理图；
图3为一个实施例中接口兼容电路中的mSATA连接器电路的电路原理图。
具体实施方式
硬盘接口是硬盘与主机系统间的连接部件，作用是在硬盘缓存和主机内存之间传输数据。从整体的角度上，硬盘接口分为IDE(Integrated Drive Electronics，即电子集成驱动器)、SATA(Serial Advanced Technology Attachment，串行硬盘接口技术)、SCSI(Small Computer System Interface，小型计算机系统接口)、光纤通道和SAS(Serial Attached SCSI，串行连接SCSI)五种。IDE接口硬盘多用于家用产品中，也部分应用于服务器；SCSI接口的硬 盘则主要应用于服务器市场，而光纤通道只在高端服务器上，价格昂贵；SATA是一种新生的硬盘接口类型，正处于市场普及阶段，在家用市场中有着广泛的前景。mSATA接口(mini-SATA，迷你版本SATA接口)是SATA国际接口标准组织发布的一种新型的接口标准，带mSATA接口的固态硬盘在平板计算机、手机、机上盒以及打印机等领域有着广泛的应用。
机械硬盘即传统普通硬盘，主要包括盘片、磁头、盘片转轴及控制电机、磁头控制器、数据转换器、接口、缓存等。磁头可沿盘片的半径方向运动，加上盘片每分钟几千转的高速旋转，磁头就可以定位在盘片的指定位置上进行数据的读写操作。信息通过离磁性表面很近的磁头，由电磁流来改变极性方式被电磁流写到磁盘上，信息可以通过相反的方式读取，作为精密设备，尘埃是其大敌，必须完全密封。机械硬盘中所有的盘片都装在一个旋转轴上，每张盘片之间是平行的，机械硬盘在每个盘片的存储面上有一个磁头，磁头与盘片之间的距离比头发丝的直径还小，所有的磁头连在一个磁头控制器上，由磁头控制器负责各个磁头的运动。
固态硬盘简称固盘，固态硬盘用固态电子存储芯片阵列而制成的硬盘，包括控制单元和存储单元(FLASH芯片和DRAM芯片)。SSD(Solid State Drives，固态硬盘)固态硬盘内部不存在任何机械部件，这样即使在高速移动甚至伴随翻转倾斜的情况下也不会影响到正常使用，而且在发生碰撞和震荡时能够将数据丢失的可能性降到最小。固态硬盘的存储介质分为两种，一种是采用闪存(FLASH芯片)作为存储介质，另外一种是采用DRAM作为存储介质。基于闪存的固态硬盘是固态硬盘的主要类别，其内部构造十分简单，固态硬盘内主体其实就是一块PCB(Printed Circuit Board，印制线路板)板，而这块PCB板上最基本的配件就是控制芯片、缓存芯片(部分低端硬盘无缓存芯片)和用于存储数据的闪存芯片。主控芯片是固态硬盘的大脑，其作用一是合理调配数据在各个闪存芯片上的负荷，二则是承担了整个数据中转，连接闪存芯片和外部SATA接口。不同的主控之间能力相差非常大，在数据处理能力、算法，对闪存芯片的读取写入控制上会有非常大的不同，直接会导致固态硬盘产品在性能上差距高达数十倍。
不少用户把混合硬盘看成是固态硬盘与一般的机械硬盘混合使用，其实混合硬盘并非是将固态硬盘与传统的机械硬盘混合使用的称呼。混合硬盘是一块基于传统机械硬盘诞生出来的新硬盘，除了机械硬盘必备的碟片、马达、磁头等等，还内置了NAND闪存颗粒， 该颗粒将用户经常访问的数据进行储存，可以达到如SSD固态硬盘效果的读取性能。SSHD(Solid State Hybrid Drive，固态混合硬盘)是把磁性硬盘和闪存集成到一起的一种硬盘，是处于磁性硬盘和固态硬盘中间的一种解决方案。
在一个实施例中，如图1所示，一种接口兼容电路，包括SATA连接器电路100、mSATA连接器电路200、主控电路逻辑接口300以及识别主控电路逻辑接口300的接入设备类型并设置成相应的读写方式的主控电路400，其中，所述接入设备类型包括SATA接口的机械硬盘、SATA接口的机械固态混合硬盘、SATA接口的固态硬盘以及mSATA接口的固态硬盘；
SATA连接器电路100和mSATA连接器电路200分别与主控电路逻辑接口300连接，主控电路逻辑接口300与主控电路400连接；
当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式为顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入。
具体的，主控电路可以通过设置一个识别接入设备类型的参数来判断主控电路逻辑接口接入设备的类型，比如说用1代表接入设备类型为SATA接口的机械硬盘，2代表接入设备类型为SATA接口的机械固态混合硬盘，3代表接入设备类型为SATA接口的固态硬盘，4代表接入设备类型为mSATA接口的固态硬盘，当主控电路检测到识别接入设备类型的参数为1时，说明当前的输入设备是SATA接口的机械硬盘。从接入设备的读写效率和使用寿命两方面综合考虑，结合不同类型的接入设备本身的特性，为使对接入设备的读写效率更高，使用寿命更长，当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式为顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入。
SATA连接器电路100，包括SATA连接器、第一电容、第二电容、第三电容以及第四电容，第一电容的一端连接SATA连接器的第一差分接收引脚，第一电容的另一端连接主控电路的第一差分接收引脚；第二电容的一端连接SATA连接器的第二差分接收引脚，第二电容的另一端连接主控电路的第二差分接收引脚；第三电容的一端连接SATA连接器的 第一差分发送引脚，第三电容的另一端连接主控电路的第一差分发送引脚；第四电容的一端连接SATA连接器的第二差分发送引脚，第四电容的另一端连接主控电路的第二差分发送引脚。接口兼容电路还包括第一电路板，SATA连接器、第一电容、第二电容、第三电容以及第四电容依次设置于第一电路板。具体的，第一电容、所述第二电容、第三电容以及第四电容均为10nF的电容。更为具体的，图2为SATA连接器的电路原理图，其中，第一电容为C315，第二电容为C316，第三电容为C317，第四电容为C318。
mSATA连接器电路200，包括mSATA连接器、第五电容、第六电容、第七电容以及第八电容，第五电容的一端连接所述mSATA连接器的第一差分接收引脚，第五电容的另一端连接主控电路的第一差分接收引脚；第六电容的一端连接mSATA连接器的第二差分接收引脚，第六电容的另一端连接主控电路的第二差分接收引脚；第七电容的一端连接mSATA连接器的第一差分发送引脚，第七电容的另一端连接主控电路的第一差分发送引脚；第八电容的一端连接mSATA连接器的第二差分发送引脚，第八电容的另一端连接主控电路的第二差分发送引脚。接口兼容电路还包括第二电路板，mSATA连接器、第五电容、第六电容、第七电容以及第八电容依次设置于第二电路板。具体的，第五电容、第六电容、第七电容以及第八电容均为10nF的电容。更为具体的，图3为mSATA连接器的电路原理图，其中，第五电容为C323，第六电容为C325，第七电容为C326，第八电容为C327。
主控电路400包括GL830主控芯片，GL830是一个高相容性、低成本的USB(Universal Serial Bus，通用串行总线)2.0对SATA桥接控制器。
上述接口兼容电路，包括SATA连接器电路、mSATA连接器电路、主控电路逻辑接口以及识别主控电路逻辑接口的接入设备类型并设置成相应的读写方式的主控电路；SATA连接器电路和mSATA连接器电路分别与主控电路逻辑接口连接，主控电路逻辑接口与主控电路连接，当接入设备类型为SATA接口的机械硬盘时，设置的相应的读写方式为顺序读取、缓存写入；当接入设备类型为SATA接口的机械固态混合硬盘时，设置的相应的读写方式为顺序读取、负载均衡写入；当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的相应的读写方式为随机读取、负载均衡写入，该接口兼容电路可兼容识别SATA接口的接入设备和mSATA接口的接入设备，并根据接入设备的类型设置相应的读写方式，无需分开独立设计用于识别SATA接口的接入设备以及用于识别 mSATA接口的接入设备的主控电路逻辑接口，这样占用空间小，且节省了系统资源，降低了成本。
在一个实施例中，接口兼容电路中，当接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，基于固态硬盘无机械结构、读写次数有限的特性，将对SATA接口的固态硬盘或mSATA接口的固态硬盘相邻两次读写数据的时间间隔设置为0，以此提高接入设备的读写寿命。具体来说，这是因为当需再次读取数据时，机械硬盘需要把已停止的马达转动并达到额定的转速后才会进行数据读写，从0加速到额定的转速需要时间，这就是所说的延迟时间，而固态硬盘没有转速，可以立刻执行读写操作。此外，接口兼容电路中的主控电路获取主控电路逻辑接口的接入设备的容量和缓存值，根据容量大小和缓存值的大小，确定读写操作频繁程度，容量大的，读写操作越频繁；缓存值越小，读写操作越频繁，以确保较高的读写效率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种接口兼容电路，其特征在于，包括SATA连接器电路、mSATA连接器电路、主控电路逻辑接口以及识别所述主控电路逻辑接口的接入设备类型并设置成相应的读写方式的主控电路，其中，所述接入设备类型包括SATA接口的机械硬盘、SATA接口的机械固态混合硬盘、SATA接口的固态硬盘以及mSATA接口的固态硬盘；
    所述SATA连接器电路和所述mSATA连接器电路分别与所述主控电路逻辑接口连接，所述主控电路逻辑接口与所述主控电路连接；
    当所述接入设备类型为SATA接口的机械硬盘时，设置的所述相应的读写方式为顺序读取、缓存写入；当所述接入设备类型为SATA接口的机械固态混合硬盘时，设置的所述相应的读写方式为顺序读取、负载均衡写入；当所述接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，设置的所述相应的读写方式为随机读取、负载均衡写入。
  2. 根据权利要求1所述的接口兼容电路，其特征在于，所述SATA连接器电路包括SATA连接器、第一电容、第二电容、第三电容以及第四电容，所述第一电容的一端连接所述SATA连接器的第一差分接收引脚，所述第一电容的另一端连接所述主控电路的第一差分接收引脚；所述第二电容的一端连接所述SATA连接器的第二差分接收引脚，所述第二电容的另一端连接所述主控电路的第二差分接收引脚；所述第三电容的一端连接所述SATA连接器的第一差分发送引脚，所述第三电容的另一端连接所述主控电路的第一差分发送引脚；所述第四电容的一端连接所述SATA连接器的第二差分发送引脚，所述第四电容的另一端连接所述主控电路的第二差分发送引脚。
  3. 根据权利要求2所述的接口兼容电路，其特征在于，还包括第一电路板，所述SATA连接器、所述第一电容、所述第二电容、所述第三电容以及所述第四电容依次设置于所述第一电路板。
  4. 根据权利要求2所述的接口兼容电路，其特征在于，所述第一电容、所述第二电容、所述第三电容以及所述第四电容均为10nF的电容。
  5. 根据权利要求1所述的接口兼容电路，其特征在于，所述mSATA连接器电路包括mSATA连接器、第五电容、第六电容、第七电容以及第八电容，所述第五电容的一端连接所述mSATA连接器的第一差分接收引脚，所述第五电容的另一端连接所述主控电路的第一差分接收引脚；所述第六电容的一端连接所述mSATA连接器的第二差分接收引脚，所 述第六电容的另一端连接所述主控电路的第二差分接收引脚；所述第七电容的一端连接所述mSATA连接器的第一差分发送引脚，所述第七电容的另一端连接所述主控电路的第一差分发送引脚；所述第八电容的一端连接所述mSATA连接器的第二差分发送引脚，所述第八电容的另一端连接所述主控电路的第二差分发送引脚。
  6. 根据权利要求5所述的接口兼容电路，其特征在于，还包括第二电路板，所述mSATA连接器、所述第五电容、所述第六电容、所述第七电容以及所述第八电容依次设置于所述第二电路板。
  7. 根据权利要求5所述的接口兼容电路，其特征在于，所述第五电容、所述第六电容、所述第七电容以及所述第八电容均为10nF的电容。
  8. 根据权利要求1-7中任意一项所述的接口兼容电路，其特征在于，所述主控电路包括GL830主控芯片。
  9. 根据权利要求1-7中任意一项所述的接口兼容电路，其特征在于，当所述接入设备类型为SATA接口的固态硬盘或mSATA接口的固态硬盘时，所述SATA接口的固态硬盘或所述mSATA接口的固态硬盘相邻两次读写数据的时间间隔为0。
  10. 根据权利要求1-7中任意一项所述的接口兼容电路，其特征在于，所述主控电路获取所述主控电路逻辑接口的接入设备的容量和缓存值。
PCT/CN2016/113538 2016-12-21 2016-12-30 接口兼容电路 WO2018113026A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611190730.8 2016-12-21
CN201611190730.8A CN106776412B (zh) 2016-12-21 2016-12-21 接口兼容电路

Publications (1)

Publication Number Publication Date
WO2018113026A1 true WO2018113026A1 (zh) 2018-06-28

Family

ID=58893513

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/113538 WO2018113026A1 (zh) 2016-12-21 2016-12-30 接口兼容电路

Country Status (2)

Country Link
CN (1) CN106776412B (zh)
WO (1) WO2018113026A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN206370051U (zh) * 2016-12-21 2017-08-01 广州炒米信息科技有限公司 接口兼容电路
CN107229428A (zh) * 2017-06-26 2017-10-03 长沙开雅电子科技有限公司 一种新型mSATA存储缓存加速方法
CN110568905A (zh) * 2019-08-09 2019-12-13 苏州浪潮智能科技有限公司 一种硬盘背板、信号处理方法及介质
CN111010357B (zh) * 2020-03-09 2020-06-16 中国人民解放军国防科技大学 一种基于hdd硬盘的数据摆渡方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101751338A (zh) * 2008-12-15 2010-06-23 中芯国际集成电路制造(上海)有限公司 数据存取控制装置及数据存取方法
US20140136750A1 (en) * 2012-11-15 2014-05-15 Qualcomm Incorporated Operating m-phy based communications over serial advanced technology attachment (sata)-based interface, and related cables, connectors, systems and methods
CN204463822U (zh) * 2015-01-09 2015-07-08 特科芯有限公司 SATA和mSATA双接口并存的固态硬盘
CN205176831U (zh) * 2015-11-02 2016-04-20 深圳华北工控股份有限公司 一种自动sata储存设备侦测切换电路
CN206370051U (zh) * 2016-12-21 2017-08-01 广州炒米信息科技有限公司 接口兼容电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101751338A (zh) * 2008-12-15 2010-06-23 中芯国际集成电路制造(上海)有限公司 数据存取控制装置及数据存取方法
US20140136750A1 (en) * 2012-11-15 2014-05-15 Qualcomm Incorporated Operating m-phy based communications over serial advanced technology attachment (sata)-based interface, and related cables, connectors, systems and methods
CN204463822U (zh) * 2015-01-09 2015-07-08 特科芯有限公司 SATA和mSATA双接口并存的固态硬盘
CN205176831U (zh) * 2015-11-02 2016-04-20 深圳华北工控股份有限公司 一种自动sata储存设备侦测切换电路
CN206370051U (zh) * 2016-12-21 2017-08-01 广州炒米信息科技有限公司 接口兼容电路

Also Published As

Publication number Publication date
CN106776412A (zh) 2017-05-31
CN106776412B (zh) 2018-07-03

Similar Documents

Publication Publication Date Title
US10769059B2 (en) Apparatus and system for object-based storage solid-state device
US9811407B2 (en) System is applied to control indicator lights for non-volatile memory express solid state disk
US7970919B1 (en) Apparatus and system for object-based storage solid-state drive and method for configuring same
WO2018113026A1 (zh) 接口兼容电路
WO2018113029A1 (zh) 接口兼容装置
TWI747321B (zh) 混合式記憶碟，電腦系統，及用於操作多重模式混合式碟之相關方法
US20170161165A1 (en) System is applied to control indicator lights for non-volatile memory express solid state disk
US8140724B1 (en) SATA pass through port
US20140317339A1 (en) Data access system, data accessing device, and data accessing controller
US20220164145A1 (en) Apparatus and system for object-based storage solid-state device
TWI451262B (zh) 橋接電路
WO2009038257A1 (en) Main board including ssd disk controllers
US20100235559A1 (en) Solid-state disk
TW201816622A (zh) 電腦系統
US20150370487A1 (en) Storage device and address-corresponding method, data-accessing method, and identifying and accessing method thereof
CN105989867A (zh) 一种独立硬盘的应用

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16924407

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16924407

Country of ref document: EP

Kind code of ref document: A1