JP4972212B2 - ブリッジ回路 - Google Patents

ブリッジ回路 Download PDF

Info

Publication number
JP4972212B2
JP4972212B2 JP2010540184A JP2010540184A JP4972212B2 JP 4972212 B2 JP4972212 B2 JP 4972212B2 JP 2010540184 A JP2010540184 A JP 2010540184A JP 2010540184 A JP2010540184 A JP 2010540184A JP 4972212 B2 JP4972212 B2 JP 4972212B2
Authority
JP
Japan
Prior art keywords
memory
interface
bridge circuit
storage device
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010540184A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011508329A5 (enExample
JP2011508329A (ja
Inventor
宗久 松本
眞一郎 久野
Original Assignee
マーベル ワールド トレード リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by マーベル ワールド トレード リミテッド filed Critical マーベル ワールド トレード リミテッド
Publication of JP2011508329A publication Critical patent/JP2011508329A/ja
Publication of JP2011508329A5 publication Critical patent/JP2011508329A5/ja
Application granted granted Critical
Publication of JP4972212B2 publication Critical patent/JP4972212B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
JP2010540184A 2007-12-26 2008-12-23 ブリッジ回路 Active JP4972212B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1667007P 2007-12-26 2007-12-26
US61/016,670 2007-12-26
US12/333,854 2008-12-12
US12/333,854 US7870323B2 (en) 2007-12-26 2008-12-12 Bridge circuit for interfacing processor to main memory and peripherals
PCT/IB2008/003613 WO2009081271A1 (en) 2007-12-26 2008-12-23 Bridge circuit interfacing a processor to external devices via memory address mapping

Publications (3)

Publication Number Publication Date
JP2011508329A JP2011508329A (ja) 2011-03-10
JP2011508329A5 JP2011508329A5 (enExample) 2012-02-16
JP4972212B2 true JP4972212B2 (ja) 2012-07-11

Family

ID=40799980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010540184A Active JP4972212B2 (ja) 2007-12-26 2008-12-23 ブリッジ回路

Country Status (6)

Country Link
US (1) US7870323B2 (enExample)
EP (1) EP2225653A1 (enExample)
JP (1) JP4972212B2 (enExample)
CN (1) CN101911035B (enExample)
TW (1) TWI451262B (enExample)
WO (1) WO2009081271A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9098209B2 (en) 2011-08-24 2015-08-04 Rambus Inc. Communication via a memory interface
WO2013028854A1 (en) 2011-08-24 2013-02-28 Rambus Inc. Methods and systems for mapping a peripheral function onto a legacy memory interface
US11048410B2 (en) 2011-08-24 2021-06-29 Rambus Inc. Distributed procedure execution and file systems on a memory interface
JP5876017B2 (ja) * 2013-08-30 2016-03-02 株式会社ソニー・コンピュータエンタテインメント 周辺機器制御装置および情報処理装置
JP6924026B2 (ja) * 2016-12-19 2021-08-25 シナプティクス インコーポレイテッド 半導体装置、ヒューマンインターフェース装置及び電子機器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822550A (en) 1994-12-22 1998-10-13 Texas Instruments Incorporated Split data path fast at-bus on chip circuits systems and methods
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
JP3061106B2 (ja) * 1996-02-28 2000-07-10 日本電気株式会社 バスブリッジおよびそれを備えた計算機システム
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6145029A (en) * 1998-03-13 2000-11-07 Compaq Computer Corporation Computer system with enhanced docking support
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20030191730A1 (en) * 2002-04-05 2003-10-09 Compaq Information Technologies Group, L.P. Unobtrusive rule-based computer usage enhancement system
US20050177829A1 (en) * 2003-10-10 2005-08-11 Vipul Vishwanath Method of applying constraints against discovered attributes in provisioning computers
US7293153B2 (en) * 2003-10-14 2007-11-06 Freescale Semiconductor, Inc. Method and system for direct access to a non-memory mapped device memory
JP4472426B2 (ja) * 2004-05-24 2010-06-02 パナソニック株式会社 バスブリッジ回路
JP2007200169A (ja) * 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法

Also Published As

Publication number Publication date
CN101911035A (zh) 2010-12-08
CN101911035B (zh) 2014-02-19
WO2009081271A1 (en) 2009-07-02
US20090172238A1 (en) 2009-07-02
EP2225653A1 (en) 2010-09-08
US7870323B2 (en) 2011-01-11
JP2011508329A (ja) 2011-03-10
TWI451262B (zh) 2014-09-01
TW200935239A (en) 2009-08-16

Similar Documents

Publication Publication Date Title
CN101266829B (zh) 存储卡、包含存储卡的存储系统及存储卡的操作方法
JP6196447B2 (ja) 読み取りデータ・ストローブ信号を含む低減ピン・カウント（ｒｐｃ）メモリ・バス・インターフェースのための装置及び方法
KR100909119B1 (ko) 집적 ｄｍａ 엔진을 사용하는 고성능 휘발성 디스크드라이브 메모리 액세스 장치 및 방법
US7788427B1 (en) Flash memory interface for disk drive
CN102063267A (zh) 包括用于使主机块大小与数据存储装置的物理块大小匹配的映射桥的数据存储系统
JP4972212B2 (ja) ブリッジ回路
US8161214B2 (en) System and method for data transfer using ATA interface
US9990311B2 (en) Peripheral interface circuit
US11526454B2 (en) Data storage device with an exclusive channel for flag checking of read data, and non-volatile memory control method
US9734117B2 (en) Data storage device and method for integrated bridge firmware to be retrieved from a storage system on chip (SOC)
US20050198425A1 (en) Combined optical storage and flash card reader using single ide or sata port and method thereof
JP2012063875A (ja) データ記憶装置、コマンド制御装置及び電子機器
US6757775B2 (en) Batch method for accessing IDE device task registers
JP2002366509A (ja) ダイレクトメモリアクセスコントローラおよびそのアクセス制御方法
TWI587139B (zh) 驅動裝置及其取得資料之方法
JP2006146817A (ja) メモリ制御システム及びメモリ制御装置
CN102141895A (zh) 驱动装置及其取得数据的方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111222

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111222

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20111222

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20120123

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120131

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120403

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120406

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150413

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4972212

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250