JP2011249599A - Semiconductor packaging substrate and package structure using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor packaging substrate and a package structure using the same, which allows a fine bump to be formed and achieves strong adhesiveness of a seal material.SOLUTION: The semiconductor packaging substrate includes an electrode having at least two regions having different surface roughness such as a peripheral part 2a with larger surface roughness and a central part 2b with smaller surface roughness, which allows fine bumps to be formed with high accuracy on the central part 2b with smaller surface roughness and obtains strong adhesiveness between the periphery part 2a with large surface roughness and a seal material.

Description

  The present invention relates to a semiconductor mounting substrate and a mounting structure using the same.

  As a method for mounting an electronic component such as a semiconductor element on a substrate such as ceramic or polyimide, a method using metal nanoparticles as a bonding material has attracted attention. Metal nanoparticles are metal particles having a size of less than 100 nm, such as Au, Ag, Cu, and Sn. The metal nanoparticles have high surface activity and low melting point due to miniaturization, and can be sintered at a low temperature (for example, 150 to 350 ° C.).

  In addition, when the metal nanoparticles are bonded to each other and have a large size, the metal nanoparticles have a high melting point equivalent to that of a metal material of a normal size having a thickness of millimeter units or more. For this reason, joining using metal nanoparticles is suitable for application to a wide range of products that require reduction of thermal stress during mounting of electronic components and improvement of heat-resistant temperature after mounting. Compared to bonding using resin conductive paste (for example, epoxy-based conductive adhesive), bonding using metal nanoparticles is performed by melting metal instead of resin. Is called. Therefore, a more excellent bonding with a low resistivity and a high bonding strength is realized.

  As a method of applying a metal nanoparticle paste (hereinafter also referred to as “nanoparticle paste”), an inkjet method may be used. The ink jet method is excellent in that the amount of paste consumed is small because there is no problem that a paste that is not used for printing, such as screen printing, is generated and the paste is consumed in large quantities.

  However, the ink jet method has a problem in that a fine pattern cannot be formed with high accuracy because the landed ink jet droplets become larger than the ejected ink particle diameter.

  A pattern forming method by an ink jet method that solves such a problem has already been proposed (see, for example, Patent Document 1). FIG. 8A shows a plan view of a conventional substrate described in Patent Document 1, and FIG. 8B shows a cross-sectional view taken along line AA of FIG.

  In the method described in Patent Document 1, a high wettability region 200a having a large surface roughness and a low wettability region 200b having a small surface roughness are formed on a substrate prior to application of a paste by an inkjet method. The landed ink is drawn into the high wettability region due to the difference in wettability, and the wetting spread to the low wettability region is suppressed. Therefore, patterning can be performed with high accuracy.

JP 2009-71037 A

  The conventional method described above increases the wettability of the portion where the electrode is to be formed on the substrate side, reduces the wettability of the portion where the electrode is not formed, and suppresses the spread of the paste to other than the necessary portion. According to technical thought.

  However, this conventional method has the following problems when a fine bump pattern is formed on an electrode to join a semiconductor element and further seal with a sealing material. In other words, when the conventional method is applied when bumps are formed on the electrodes, the surface roughness of the portions where the bumps are formed is increased, and the surface roughness of the portions where the bumps are not formed is decreased. That is, the surface roughness of the region where no bump is formed on the electrode is small.

  For this reason, if the sealing is performed after the semiconductor element and the electrode substrate are bonded together to protect the semiconductor element and reinforce the bump, the adhesion between the sealing material and the electrode is lowered. This is because the wettability of the region having a small surface roughness and the sealing material is low. As a result, there is a problem that a sufficient mechanical fastening force cannot be obtained between the electrode and the sealing material.

  On the other hand, when the surface roughness on the electrode is increased and the wettability is increased, it becomes difficult not only to form a fine bump pattern due to the wet spread of the paste, but also the sealing material is formed between the semiconductor element and the substrate. Get in. This is because the sealing material also spreads on the electrode. As a result, there is a problem that the reliability of the conductivity between the electrode and the semiconductor element is lowered due to expansion / contraction of the sealing material due to heat.

  The present invention has been made in view of the above problems, and provides a semiconductor mounting substrate that can form fine bumps and that can achieve strong adhesion of a sealing material, and a mounting structure using the same. The purpose is to provide.

  In order to achieve the above object, the present invention provides a semiconductor mounting substrate having an electrode having at least two regions having different surface roughnesses, a peripheral portion having a large surface roughness and a central portion having a small surface roughness. .

More specifically, the semiconductor mounting substrate of the present invention is
A central portion where the semiconductor element is mounted;
A semiconductor mounting substrate having an electrode composed of a peripheral portion surrounding the periphery of the central portion,
Provided is a semiconductor mounting substrate in which the peripheral portion has a surface roughness larger than that of the central portion.

  In the semiconductor mounting substrate according to a preferred embodiment of the present invention, the arithmetic average roughness (Ra) of the region having the largest surface roughness is the arithmetic average roughness (Ra) of the region having the smallest surface roughness on the same electrode surface. ) Larger than 50 nm.

  In another preferred embodiment of the semiconductor mounting substrate of the present invention, the central portion is a region where a semiconductor element is mounted, and the peripheral portion is a region surrounding the periphery of the central portion.

  In another preferred embodiment of the semiconductor mounting substrate of the present invention, the electrode is made of Au, Au alloy, Ag, Ag alloy, Cu, or Cu alloy.

  In another preferred embodiment of the semiconductor mounting substrate of the present invention, the base material is made of alumina or aluminum nitride.

  The present invention also provides a mounting structure using a semiconductor mounting substrate having electrodes having at least two regions having different surface roughnesses, a peripheral portion having a large surface roughness and a central portion having a small surface roughness. .

  In a mounting structure according to a preferred embodiment of the present invention, bumps for electrically joining the electrodes of the semiconductor mounting substrate and the semiconductor elements are formed of paste, and the semiconductor elements are sealed with a sealing material.

  In another preferred embodiment of the mounting structure of the present invention, a region where the sealing material does not exist is provided between the central portion of the electrode of the semiconductor mounting substrate and the semiconductor element.

  In another preferred embodiment of the mounting structure of the present invention, substantially the entire periphery of the electrode of the semiconductor mounting substrate is covered with the sealing material.

  In a mounting structure according to a preferred embodiment of the present invention, the paste includes metal particles of Au, Au alloy, Ag, Ag alloy, Cu, or Cu alloy.

  In another preferred embodiment of the mounting structure of the present invention, the paste is a metal nanoparticle paste.

  In another preferred embodiment of the mounting structure of the present invention, the semiconductor element is an LED element.

  According to the semiconductor mounting substrate of the present invention, since the surface roughness of the bump forming region in the substrate electrode is small, the spread of wetting when the paste lands on the electrode can be suppressed, so that fine bumps can be formed with high accuracy. it can. Moreover, since the surface roughness of the area | region where a board | substrate electrode and a sealing material contact | connect is large, the strong mechanical fastening force, ie, adhesiveness, can be achieved between a board | substrate electrode and a sealing material.

  Further, at the time of sealing, the sealing material easily spreads in a region having a large surface roughness, and hardly spreads in a region having a small surface roughness on which bumps are formed. As a result, the sealing material can be prevented from entering between the semiconductor element and the substrate, and the reliability of the electrical connection due to the deformation of the bump accompanying the expansion and contraction of the sealing material can be prevented.

The top view which shows schematic structure of the semiconductor mounting substrate which concerns on embodiment of this invention. The top view which shows schematic structure of the semiconductor mounting board | substrate which concerns on the more preferable form of the said embodiment. The top view which shows schematic structure of the semiconductor mounting board | substrate which concerns on another more preferable form of the said embodiment. Sectional drawing which shows the procedure of the manufacturing method of the semiconductor mounting board of this invention. Sectional drawing which shows the procedure of another manufacturing method of the semiconductor mounting substrate of this invention. Sectional drawing which shows schematic structure of the mounting structure which concerns on embodiment of this invention. Sectional drawing which shows the manufacturing method of the mounting structure which concerns on embodiment of this invention. The figure which shows schematic structure of the conventional board | substrate described in patent document 1. FIG.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a semiconductor mounting substrate 100 according to an embodiment of the present invention. FIG. 1 (a) is a plan view of the semiconductor mounting substrate 100, and FIG. 1 (b) is FIG. FIG. 1C is a cross-sectional view taken along the line AA of FIG. 1B, showing a state in which a paste is applied to the semiconductor mounting substrate 100 and bumps 8 are formed. Here, it is assumed that an LED element is mounted on the semiconductor mounting substrate 100. The semiconductor mounting substrate 100 is also simply referred to as a substrate 100.

  As the base material 1 of the substrate 100, a material having good heat dissipation such as an alumina substrate or an aluminum nitride substrate is preferably used. In addition, a high heat dissipation substrate such as a metal core substrate and a metal base substrate can be used. On the base material 1 of the substrate 100, electrodes 2 (2p and 2n) are formed. Hereinafter, the electrodes 2p and 2n are also referred to simply as “electrode 2”.

  The LED element has two electrodes, a P-type electrode and an N-type electrode, and the area of the P-type electrode is configured to be larger than the area of the N-type electrode in order to increase the light extraction efficiency. Therefore, when the semiconductor element mounted on the substrate is an LED element, two electrodes 2 having different areas are formed on the base material 1 of the substrate 100 for one LED element, as shown in FIG.

  The electrode 2 can be formed from, for example, Au (gold), Ag (silver), Cu (copper), Al (aluminum), or an alloy thereof. However, considering the bonding property with the bumps 8 to be formed on the electrode 2 later, the electrode 2 is formed of Au or an Au alloy which is not easily oxidized, or a metal whose surface is coated with Au or an Au alloy. It is preferable to do this. The electrode 2 can be formed by, for example, a plating method or a vapor deposition method.

  Referring to FIG. 1A, an electrode 2p to which a P-type electrode is connected is composed of a peripheral portion 2pa having a large surface roughness and a central portion 2pb having a small surface roughness. Similarly, the electrode 2n to which the N-type electrode is connected is composed of a peripheral portion 2na and a central portion 2nb. Hereinafter, when the peripheral part and the central part are expressed without distinguishing between the P-type electrode and the N-type electrode, they are simply referred to as the peripheral part 2a and the central part 2b. The central portion 2b is a region where a bump is formed and a semiconductor element is mounted, and the peripheral portion 2a is a region surrounding the central portion 2b. A peripheral edge 2b having a large surface roughness is formed around the central part 2a having a small surface roughness. An insulating region 2i is formed between the electrode 2p and the electrode 2n.

Next, the effect of surface roughness will be described in detail. The effect of surface roughness on wettability is expressed by the following Wenzel equation.
cos θ ′ = r cos θ
Here, θ is a smooth surface, and θ ′ is a value of a contact angle of a solid surface having minute unevenness. In addition, r is the ratio of the actual surface area to the apparent surface area, and r ≧ 1 because the actual surface area is larger on the surface with minute irregularities due to roughness or the like than on the smooth surface. This equation teaches that a liquid having a contact angle of θ on a smooth surface will contact at an angle θ ′ on a surface with minute irregularities. Since r ≧ 1, clearly θ ′ <θ.

  That is, according to this formula, when the chemical composition of the surface is the same, if the contact angle between a liquid and a smooth surface is 90 ° or less, the surface with minute irregularities is wetted by the liquid rather than the smooth surface. Teach it easy. That is, a liquid that easily wets a solid surface becomes more easily wet as the solid surface has a larger roughness. Conversely, if the roughness of the solid surface is small, it is difficult to spread.

  Therefore, by applying the paste to the region 2b where the surface roughness of the electrode is small, it is possible to prevent the paste from spreading when applied, and a fine pattern such as a stripe shape or a dot shape can be formed. Moreover, by increasing the surface roughness of the electrode peripheral portion, the mechanical fastening force between the sealing material and the substrate electrode is increased, and the strong adhesion of the sealing material can be achieved.

  Further, by increasing the surface roughness of the peripheral edge 2a, the sealing material wets and spreads to the peripheral edge 2a having a large surface roughness during sealing. However, the sealing material is difficult to wet and spread in the central portion 2b having a small surface roughness. Thereby, the entrapment of the sealing material between the semiconductor element and the substrate can be suppressed, and the reliability of the electrical connection due to the expansion and contraction of the sealing resin can be prevented.

  In order to suppress the entry of the sealing material between the semiconductor element and the substrate at the time of sealing, it is preferable to increase the difference between the surface roughness of the peripheral portion and the surface roughness of the central portion. Specifically, it is preferable that the arithmetic average roughness (Ra) of the peripheral portion is 50 nm or more larger than the arithmetic average roughness (Ra) of the central portion.

  Next, the configuration of the electrode 2 will be described in detail. Referring to FIG. 1 again, the area of the small surface roughness (central portion 2b) is preferably wider than the semiconductor element electrode area. Here, the “semiconductor element electrode region” means a region surrounded by an outer edge including all the bumps connected to the electrodes of the semiconductor element. For example, the central portion 2pb is wider than the region surrounded by the outer edge including all the bumps 8 connected to the P-type electrode on the LED element side. The central portion 2nb is wider than a region surrounded by an outer edge including all the bumps connected to the N-type electrode on the LED element side.

  Thus, by making the central portion 2b wider than the semiconductor element electrode region, the area of the bump 8 can be increased, and sufficient bonding strength can be ensured between the electrode and the semiconductor element. If the central portion 2b is wider than the semiconductor element electrode region, the sealing material disposed on the peripheral edge portion 2a is less likely to spread between the semiconductor element and the electrode 2b.

  Moreover, it is preferable that the center part 2b is narrow to such an extent that the peripheral part 2a can be ensured sufficiently wide on the base material 1 having a determined width. This is because the bonding area between the electrode (peripheral portion 2a) and the sealing material is widened to ensure the bonding strength. As a result, the reliability when using a semiconductor element is improved.

  The peripheral edge 2a does not need to be entirely covered with the sealing material, and the peripheral edge 2a may be exposed on the outer side sealed with the sealing material. This is because the unsealed peripheral edge 2a may be used as an external energization path.

  With reference to FIG. 2, the other form of the center part 2b and the peripheral part 2a is demonstrated. In FIG. 2, there is a portion where the peripheral portion 2a is not present in a part of the central portion 2pb where the P-type electrode is joined and the central portion 2nb where the N-type electrode is joined. This is because the insulating region 2i exists between the P-type electrode and the N-type electrode. Since the base material 1 or the insulating material is exposed in the insulating region 2i, the wettability of the paste is remarkably different because the chemical composition of the surface is different from that of the electrode surface. That is, a short circuit between the electrodes due to the paste protruding is prevented. In the embodiment of FIG. 2, it can be said that the presence of an insulating material (having a surface chemical composition different from that of the electrode) plays a role of the peripheral edge 2a.

  From the embodiments described above, it can be said that the central portion 2b is surrounded by the peripheral edge portion 2a even when there is a portion not surrounded by the peripheral edge portion 2a when the surface chemical composition is different from that of the electrode. This is because the region surrounded by the outer edge including all of the bumps connected to the semiconductor electrode not only means each electrode having a different polarity but also an outer edge including all of the bumps connected to the electrode having different polarities. In other words, it may mean an enclosed area. Also, in other words, no contradiction occurs with the embodiment of FIG.

  Next, another embodiment will be described with reference to FIG. In FIGS. 3A and 3B, regions 3 having the same surface roughness as the bumps to be formed are formed in the central portions 2pb and 2nb. A portion where a bump for the P-type electrode is formed is referred to as a region 3p, and a portion where the bump for the N-type electrode is formed is referred to as a region 3n. Further, when the regions 3p and 3n are expressed together, they are simply referred to as region 3.

  By increasing the surface roughness of the part where the bumps are formed, the wettability of the paste at this part is increased, and the spread of wetting to areas other than the bump pattern is suppressed by being blocked by the part with a small surface roughness. . Bumps according to the result pattern can be formed.

  Thus, there may be a portion having a large surface roughness inside the central portion 2b. Further, the region 3 formed inside the central portion 2b needs to be surrounded by an electrode having a small surface roughness. This is to prevent the sealing material from spreading from the peripheral edge 2a. However, as described with reference to FIG. 2, when adjacent to the insulating region 2 i, it may not be adjacent to a region having a small surface roughness.

  Next, a method for forming regions having different surface roughness on the electrode will be described. In order to form a region having different roughness on the substrate electrode, a region having a small roughness may be formed on an electrode having a large roughness, or a region having a large roughness may be formed on an electrode having a small roughness. Good.

  Examples of a method of forming a region having a large roughness on an electrode having a small roughness include, for example, ultraviolet irradiation, plasma or corona discharge treatment, and processing to press the jig 4a as shown in FIGS. Is mentioned.

  Referring to FIG. 4A, an electrode base 20b having a small surface roughness is formed on the substrate 1 in advance by vapor deposition, sputtering, plating, or the like. Then, a jig 4a whose surface is processed to a predetermined roughness corresponding to the peripheral edge 2a is prepared.

  With reference to FIG.4 (b), the jig 4a is pressed and pressed from the electrode base 20b. Then, the surface of the jig 4a is transferred onto the electrode base 20b, and a portion having a large surface roughness is formed as the peripheral edge 2a. The portion where the jig 4a is not pressed remains as the central portion 2b.

  Moreover, as a method of forming a region having a small roughness on an electrode having a large roughness, for example, cutting or polishing, a process of pressing the jig 4b as shown in FIGS.

  With reference to Fig.5 (a), the electrode base 20a with a large surface roughness is previously formed in the base material 1. FIG. Specifically, it can be realized by forming the surface roughness of the substrate 1 large and forming electrodes thereon by vapor deposition, sputtering, plating or the like.

  Next, a jig 4b corresponding to the central portion is prepared. Since the jig 4b is a jig for forming the central portion, the surface roughness thereof is sufficiently small. Then, the jig 4b is pressed against the surface of the electrode base 20a (FIG. 5B).

  On the electrode base 20a to which the surface of the jig 4b is transferred, a portion where the jig 4b is pressed is formed as the central portion 2b, and a portion where the jig 4b is not pressed remains as the peripheral portion 2a.

  In addition, when a low roughness region is formed on a high roughness electrode, as shown in FIG. 5C, the height of the region of the central portion 2b, which is a region where the paste is applied, is high. It becomes lower than the height of the region 2a. As a result, compared with the case where a region having a large surface roughness is formed on the region having a small surface roughness shown in FIG. 4, it is possible to prevent the paste from spreading and protruding into the region of the peripheral edge 2a. In other words, it is preferable to form a region with a small roughness on an electrode with a large roughness rather than a region with a large roughness on an electrode with a small roughness.

  As described above, one electrode 2 has been described with respect to the form constituted by the peripheral portion 2a having a large surface roughness and the central portion 2b having a small surface roughness. However, in a range not departing from the gist of the present invention. The invention is not limited to the above embodiment. For example, although not illustrated, it goes without saying that the present invention includes a case where one electrode 2 is composed of three or more regions having different roughnesses.

  Next, a mounting structure according to the present invention will be described. FIG. 6 is a cross-sectional view showing a schematic configuration of the mounting structure 5 according to the embodiment of the present invention. The semiconductor element 6 is arranged so that the terminal 7 faces the electrodes 2a and 2b of the substrate 1, and in this state, the bumps 8 made of a conductor form a region (central portion 2b) where the surface roughness of the terminals 7 and the electrodes is small. ) And are joined.

  The terminal 7 can be formed from, for example, Au (gold), Ag (silver), Cu (copper), Al (aluminum), or an alloy thereof. However, considering the bondability with the bump 8, it is preferable that the terminal 7 is made of Au or an Au alloy which is not easily oxidized, or a metal whose surface is coated with Au or an Au alloy.

  The semiconductor element 6 is sealed with a sealing material 9. The sealing material 9 is made of a translucent resin, and the phosphor can be dispersed in the translucent resin. Examples of the permeable resin include a silicone resin and an epoxy resin. Among these, a silicone resin is preferable because it has good light resistance and high fluidity before curing, and can be easily filled in a manufacturing process described later. In addition, as a silicone resin, Shin-Etsu Chemical Co., Ltd. LED silicone material LPS-3412 (trade name) can be suitably used.

  In the present specification, the case where the semiconductor element 6 is an LED element is described. However, when the semiconductor element is not an LED element, the sealing material may not be a transmissive resin.

  Since the mounting structure 5 according to the present invention uses the semiconductor mounting substrate according to the present invention, there is no sealing resin between the terminal 7 and the substrate electrode 2 b at the center of the terminal 7 of the semiconductor element 6. At least in the central portion of the substrate electrode 2b, there is no sealing resin, and the sealing resin may exist up to the bumps 8 located in the peripheral portion. As a result, it is possible to prevent a decrease in the reliability of the electrical connection due to the deformation of the bump accompanying expansion and contraction of the sealing material.

  Next, a method for manufacturing the mounting structure 5 of the present embodiment will be described. 7A to 7C are views for explaining a method for manufacturing the mounting structure 5 according to the present embodiment.

  Referring to FIG. 7A, bumps 8 are formed on substrate electrode 2b (center portion 2b) formed on base material 1. The bumps 8 are formed by applying or printing a paste. If the specific method of application | coating or printing of a paste is given, the inkjet method, screen printing, etc. will be mentioned, for example. In the ink jet method, a paste that is not used for printing, such as screen printing, is generated, and there is no problem of consuming a large amount of paste. Therefore, it is preferable to use the ink jet method in that the amount of paste consumed is small.

  The paste is preferably a nanoparticle paste containing metal particles of Au, Au alloy, Ag, Ag alloy, Cu, or Cu alloy. Thereby, the bump 8 having a high electric conductivity can be obtained.

  Moreover, it is preferable that the said nanoparticle paste contains the metal particle (metal nanoparticle) with an average particle diameter of 0.5-100 nm. Since the metal nanoparticles have a high surface activity and a low melting point due to miniaturization, the particles are fused together by heating through the substrate 1 from, for example, 150 ° C. to 300 ° C. for 15 to 60 minutes. To do. After the particles are fused, the melting point is as high as that of a normal size metal material. For this reason, it is suitable for application to a wide range of products that require reduction of thermal stress during mounting of electronic components and improvement of heat-resistant temperature after mounting. An example of such a paste is NP Series nanopaste (trade name) manufactured by Harima Kasei Co., Ltd., having a metal particle size of 3 to 7 nm.

  Next, as shown in FIG. 7B, the semiconductor element 6 is held by the flip chip bonder mounting tool 10 (not shown) so that the terminal 7 and the substrate electrode 2b face each other. The semiconductor element 6 is pressed toward the substrate 1 by the mounting tool 10 so as to press the terminals 7 of the semiconductor element 6 against the bumps 8. Thereby, the terminal 7 of the semiconductor element 6 and the board | substrate electrode 2b are temporarily joined by the bump 8. FIG.

  Next, by heating through the substrate 1, the metal particles in the bumps 8 are welded together to cure the bumps 8.

  Here, the curing of the bumps 8 may be performed by heating the terminals 7 of the semiconductor element 6 and the bumps 8 at the same time. Thereby, the number of processes can be reduced.

  The curing of the bumps 8 is not limited to the method of heating through the substrate 1, and the entire mounted substrate may be put into a heating atmosphere using a furnace or the like. Further, for example, the bump 8 may be cured by applying energy such as ultrasonic waves or electromagnetic waves to the bump 8.

  Next, as shown in FIG. 7C, sealing is performed with a sealing material 9 so as to cover the semiconductor element 6. Examples of the sealing method include molding using a mold and coating using a dispenser. After the application, the sealing material is cured by heat treatment or the like. Here, the sealing material 9 is sealed so as to cover substantially the entire surface of the semiconductor element 6. This is because by covering the entire surface with a sealing material, it is possible to secure the joint and protect the entire semiconductor element from the substrate. Further, by covering the entire surface of the semiconductor element, entry of moisture or the like into the bonded portion can be prevented, and reliability can be further improved. As described above, the mounting structure 5 of the present embodiment can be obtained.

  Hereinafter, an example of the effect of the present invention will be described based on examples.

(Example)
Arithmetic average roughness (Ra) of the electrode peripheral part is 346 nm, and the arithmetic average roughness (Ra) of the electrode central part of □ 0.79 mm is 296 nm on a substrate (roughness difference = 50 nm), □ 0.8 mm The semiconductor element was bonded with bumps so that the electrode of the semiconductor element and the electrode central part of the substrate faced each other. After that, when a sealing material was applied so as to cover the semiconductor element, the sealing resin spreads wet without large voids on the peripheral edge of the electrode, and between the semiconductor element and the substrate reached a maximum of 105 μm from the edge of the semiconductor element. I was in. Since the bump does not exist within 110 μm from the edge of the semiconductor element, it was confirmed that the sealing material does not enter the periphery of the bump.

(Comparative example)
On the other hand, when a difference in arithmetic average roughness (Ra) is not provided, or when a substrate having an arithmetic average roughness (Ra) of the electrode peripheral portion of 343 nm and an arithmetic average roughness (Ra) of the electrode central portion of 305 nm is used. (Difference in roughness = 38 nm) The entry of the sealing material can be confirmed around the bumps between the semiconductor element and the substrate, and the reliability of the electrical connection due to the deformation of the bumps caused by the expansion and contraction of the sealing material There was concern about the decline.

  As described above, according to the semiconductor mounting substrate of the present invention, the sealing material does not enter between the semiconductor element and the substrate, and a highly reliable mounting structure can be obtained.

  According to the semiconductor mounting substrate of the present invention and the mounting structure using the same, fine bumps can be formed with high accuracy and highly reliable sealing can be achieved. Therefore, it is effective for application to mounting of semiconductor elements.

DESCRIPTION OF SYMBOLS 1 Substrate base material 2 Electrode 2a Peripheral part (area | region with large surface roughness)
2b Center (region with small surface roughness)
2i Insulating region 2p P-type electrode 2n N-type electrode 3 Region with large surface roughness surrounded by region with small surface roughness 4a Jig 4b Jig 5 Mounting structure 6 Semiconductor element 7 Terminal 8 Bump 9 Sealing material 10 Mounting tool 20a Electrode ground having a large surface roughness 20b Electrode ground having a small surface roughness 100 Semiconductor mounting substrate (substrate)

Claims (11)

A central portion where the semiconductor element is mounted;
A semiconductor mounting substrate having an electrode composed of a peripheral portion surrounding the periphery of the central portion,
The semiconductor mounting board whose surface roughness of the said peripheral part is larger than the said center part.   The semiconductor mounting substrate according to claim 1, wherein a surface roughness of the peripheral edge portion is 50 nm or more larger than a surface roughness of the central portion. The electrode is Au, or an Au alloy,
Or Ag or an Ag alloy,
Alternatively, the semiconductor mounting substrate according to claim 1, wherein the semiconductor mounting substrate is made of Cu or a Cu alloy. The semiconductor mounting substrate according to any one of claims 1 to 3, wherein a base material of the semiconductor mounting substrate is made of alumina or aluminum nitride. 5. A mounting structure comprising a semiconductor element mounted on the electrode of the semiconductor mounting substrate according to claim 1. A bump for electrically bonding the electrode of the semiconductor mounting substrate and the semiconductor element is formed of a paste,
The mounting structure according to claim 5, wherein the semiconductor element is sealed with a sealing material. The mounting structure according to claim 5, wherein a region where the sealing material does not exist is provided between a central portion of an electrode of the semiconductor mounting substrate and the semiconductor element. The mounting structure according to claim 6 or 7, wherein a substantially entire surface of a peripheral portion of an electrode of the semiconductor mounting substrate is covered with the sealing material. The paste is Au, or an Au alloy,
Or Ag or an Ag alloy,
Alternatively, the mounting structure according to any one of claims 6 to 8, comprising metal particles of Cu or Cu alloy. The mounting structure according to claim 6, wherein the paste is a paste of metal nanoparticles. The mounting structure according to claim 6, wherein the semiconductor element is an LED element.