JP2011249599A5 - - Google Patents

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Publication number
JP2011249599A5
JP2011249599A5 JP2010121789A JP2010121789A JP2011249599A5 JP 2011249599 A5 JP2011249599 A5 JP 2011249599A5 JP 2010121789 A JP2010121789 A JP 2010121789A JP 2010121789 A JP2010121789 A JP 2010121789A JP 2011249599 A5 JP2011249599 A5 JP 2011249599A5
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JP
Japan
Prior art keywords
electrode
semiconductor
central portion
alloy
mounting substrate
Prior art date
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Application number
JP2010121789A
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Japanese (ja)
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JP2011249599A (en
JP5414622B2 (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2010121789A priority Critical patent/JP5414622B2/en
Priority claimed from JP2010121789A external-priority patent/JP5414622B2/en
Publication of JP2011249599A publication Critical patent/JP2011249599A/en
Publication of JP2011249599A5 publication Critical patent/JP2011249599A5/ja
Application granted granted Critical
Publication of JP5414622B2 publication Critical patent/JP5414622B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Description

より具体的には、本発明の半導体実装基板は、
基材と、
前記基材上の電極と、を含む半導体実装基板であって、
半導体素子が実装される前記電極の中央部と、
前記電極の中央部の周囲を囲む、前記電極の周縁部とがあり、
前記電極の周縁部の表面粗さが、前記電極の中央部の表面粗さより大きい半導体実装基板を提供する。
More specifically, the semiconductor mounting substrate of the present invention is
A substrate;
An electrode on the substrate; and a semiconductor mounting substrate comprising:
A central portion of the electrode on which a semiconductor element is mounted;
Surrounding the periphery of the central portion of the electrode, and the peripheral edge of the electrode ,
Provided is a semiconductor mounting substrate in which the surface roughness of the peripheral portion of the electrode is larger than the surface roughness of the central portion of the electrode .

Claims (13)

基材と、
前記基材上の電極と、を含む半導体実装基板であって、
半導体素子が実装される前記電極の中央部と、
前記電極の中央部の周囲を囲む、前記電極の周縁部とがあり、
前記電極の周縁部の表面粗さが、前記電極の中央部の表面粗さより大きい半導体実装基板。
A substrate;
An electrode on the substrate; and a semiconductor mounting substrate comprising:
A central portion of the electrode on which a semiconductor element is mounted;
Surrounding the periphery of the central portion of the electrode, and the peripheral edge of the electrode ,
The semiconductor mounting board whose surface roughness of the peripheral part of the said electrode is larger than the surface roughness of the center part of the said electrode .
前記電極の中央部の表面は、平坦でなく、粗されている請求項1に記載の半導体実装基板。The semiconductor mounting substrate according to claim 1, wherein a surface of a central portion of the electrode is not flat but rough. 前記電極の周縁部は、前記電極の中央部より、前記基材からの高さが高く形成されている請求項1または2に記載の半導体実装基板。The semiconductor mounting substrate according to claim 1, wherein the peripheral edge portion of the electrode is formed to have a height higher from the base material than a central portion of the electrode. 前記電極の周縁部の表面粗さが、前記電極の中央部の表面粗さより、50nm以上大きいことを特徴とする請求項1から3のいずれか1項に記載の半導体実装基板。 The surface roughness of the peripheral portion of the electrode, a semiconductor mounting substrate according to any one of claims 1 to 3, the surface roughness of the central portion, being greater than 50nm of said electrode. 前記電極の中央部と前記電極の周縁部とがAu、またはAu合金、
或いはAg、またはAg合金、
或いはCu、またはCu合金から構成されていることを特徴とする
請求項1から4のいずれか1項に記載の半導体実装基板。
The center part of the electrode and the peripheral part of the electrode are Au, or an Au alloy,
Or Ag or an Ag alloy,
Alternatively, the semiconductor mounting substrate according to any one of claims 1 to 4 , wherein the substrate is made of Cu or a Cu alloy.
記基材がアルミナまたは窒化アルミニウムから構成された
請求項1からのいずれか1項に記載の半導体実装基板。
The semiconductor mounting board according to any one of 5 from the previous Kimoto material according to claim 1 which is composed of alumina or aluminum nitride.
請求項1からのいずれか1項に示した半導体実装基板の前記電極の中央部上に
半導体素子を搭載してなることを特徴とする実装構造体。
A mounting structure comprising a semiconductor element mounted on a central portion of the electrode of the semiconductor mounting substrate according to any one of claims 1 to 6 .
前記半導体実装基板の電極と前記半導体素子とを電気的に接合するバンプがペーストで形成され、
前記半導体素子が封止材料により封止された
請求項に記載の実装構造体。
A bump for electrically bonding the electrode of the semiconductor mounting substrate and the semiconductor element is formed of a paste,
The mounting structure according to claim 7 , wherein the semiconductor element is sealed with a sealing material.
前記半導体実装基板の電極の中央部と前記半導体素子との間に
前記封止材料が存在しない領域を持つ
請求項またはに記載の実装構造体。
Mounting structure according to claim 7 or 8 having the area where the sealing material is not present between the central portion of the semiconductor mounting substrate electrode and the semiconductor element.
前記半導体実装基板の電極の周縁部の面が
前記封止材料に覆われている
請求項またはに記載の実装構造体。
Mounting structure according to claim 8 or 9 all surfaces are covered with the sealing material of the peripheral portion of the semiconductor mounting substrate of the electrode.
前記ペーストが
Au、またはAu合金、
或いはAg、またはAg合金、
或いはCu、またはCu合金の金属粒子を含むことを特徴とする
請求項から10のいずれか1項に記載の実装構造体。
The paste is Au, or an Au alloy,
Or Ag or an Ag alloy,
Or Cu or mounting structure according to claims 8 to any one of 10, which comprises metal particles of Cu alloy.
前記ペーストが
金属ナノ粒子のペーストであることを特徴とする
請求項から11のいずれか1項に記載の実装構造体。
The mounting structure according to any one of 11 claims 8, wherein the paste is a paste of a metal nanoparticle.
前記半導体素子はLED素子であることを特徴とする
請求項から12のいずれか1項に記載の実装構造体。
The mounting structure according to any one of the semiconductor device of claims 8, characterized in that is an LED element 12.
JP2010121789A 2010-05-27 2010-05-27 Semiconductor mounting substrate and mounting structure using the same Expired - Fee Related JP5414622B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010121789A JP5414622B2 (en) 2010-05-27 2010-05-27 Semiconductor mounting substrate and mounting structure using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010121789A JP5414622B2 (en) 2010-05-27 2010-05-27 Semiconductor mounting substrate and mounting structure using the same

Publications (3)

Publication Number Publication Date
JP2011249599A JP2011249599A (en) 2011-12-08
JP2011249599A5 true JP2011249599A5 (en) 2013-05-09
JP5414622B2 JP5414622B2 (en) 2014-02-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010121789A Expired - Fee Related JP5414622B2 (en) 2010-05-27 2010-05-27 Semiconductor mounting substrate and mounting structure using the same

Country Status (1)

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JP (1) JP5414622B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6214273B2 (en) * 2013-08-08 2017-10-18 三菱電機株式会社 Bonding structure using metal nanoparticles and bonding method using metal nanoparticles
TWI505380B (en) * 2013-12-31 2015-10-21 Tai Saw Technology Co Ltd Conducting packaging structure and manufacturing method thereof
JP2020155684A (en) * 2019-03-22 2020-09-24 株式会社カネカ Manufacturing method of solar cell string, solar cell module, and solar cell

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3893303B2 (en) * 2002-03-29 2007-03-14 住友ベークライト株式会社 Manufacturing method of semiconductor package
JP3904210B2 (en) * 2003-04-28 2007-04-11 株式会社リコー Joining method and joining structure of optoelectronic device
JP4656311B2 (en) * 2005-07-11 2011-03-23 セイコーエプソン株式会社 Electronic module
JP4835264B2 (en) * 2006-05-26 2011-12-14 株式会社村田製作所 Component built-in circuit module board
JP2009064995A (en) * 2007-09-07 2009-03-26 Sharp Corp Semiconductor package and electronic device
JP2008263248A (en) * 2008-08-07 2008-10-30 Sumitomo Electric Ind Ltd Mounting member of semiconductor light-emitting element, and method of manufacturing the same

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