JP2011243977A - Light emitting diode chip having wavelength converting layer and method of fabricating the same, and package having the light emitting diode chip and method of fabricating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light emitting diode (LED) chip capable of performing light conversion such as wavelength conversion at a chip level and a method of fabricating the same.SOLUTION: A light emitting diode (LED) chip having a wavelength conversion layer and a method of fabricating the same, and a package having the LED chip are disclosed. According to one embodiment, an LED chip comprises: a substrate; a GaN-based compound semiconductor stacked structure arranged on the top surface of the substrate, the semiconductor stacked structure comprising a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; an electrode electrically connected to the semiconductor stacked structure; an additional electrode formed on the electrode; and a wavelength converting layer covering an upper portion of the semiconductor stacked structure. Moreover, the additional electrode passes through the wavelength converting layer. This configuration makes it possible to provide an LED chip which can perform light conversion such as wavelength conversion and in which wire bonding can be easily performed.

Description

The present invention relates to a light emitting diode chip and a method for manufacturing the same, and a package including the same and a method for manufacturing the same. More particularly, the present invention relates to a light emitting diode chip having a wavelength conversion layer and a method for manufacturing the light emitting diode chip. .

Currently, light-emitting diodes can be made light and thin, and are used as back light sources for various display devices including mobile phones due to the advantages of energy saving and long life. Since the light emitting diode package can realize white light having high color rendering properties, the light emitting diode package is expected to be applied to general illumination in place of a white light source such as a fluorescent lamp.

On the other hand, there are various methods for realizing white light using a light emitting diode. Generally, an InGaN light emitting diode that emits blue light having a wavelength of 430 nm to 470 nm and a phosphor that can convert blue light into a long wavelength are combined. Thus, a method for realizing white light is used. For example, white light is realized through a combination of a blue light emitting diode and a yellow phosphor that is excited by the blue light emitting diode to emit yellow, or a combination of a blue light emitting diode and a green phosphor and a red phosphor. The

Conventionally, a white light emitting element has been formed by applying a resin containing a phosphor into a recess region of a package on which a light emitting diode is mounted. However, by applying a resin in the package, there is a problem that the phosphor is not uniformly distributed in the resin and it is difficult to form the resin in a uniform thickness.

Accordingly, a method of attaching a wavelength conversion sheet on a light emitting diode has been studied. The wavelength conversion sheet can be formed, for example, by mixing a phosphor with glass or the like. By attaching such a wavelength conversion sheet to the upper surface of the light emitting diode, white light can be realized at the chip level.

However, since the wavelength conversion sheet is attached to the upper surface of the light emitting diode, it limits the realization of white light in the light emitting diode having a structure in which light is mainly emitted from the upper surface of the light emitting diode. In a light emitting diode having a structure in which a considerable amount of light is emitted from the side surface of the light emitting diode, for example, the side surface of the growth substrate, wavelength conversion using a wavelength conversion sheet is not suitable.

On the other hand, when a resin containing phosphor is applied to the package, since the resin is applied after bonding the wire to the light emitting diode, there is a problem even if the electrode of the light emitting diode is covered with the resin containing the phosphor. Don't be. However, when the wavelength conversion layer is formed at the chip level, it is required to bond the wire to the light emitting diode after the wavelength conversion layer is formed. Accordingly, it is necessary to expose the electrode for bonding the wire from the wavelength conversion layer, and a technique for forming the wavelength conversion layer is required to facilitate the bonding of the wire.

The present invention has been made in view of the above problems, and an object thereof is to provide a light-emitting diode chip capable of performing light conversion such as wavelength conversion at a chip level and a manufacturing method thereof.

Another object of the present invention is to provide a light emitting diode chip capable of performing wavelength conversion on light emitted from the side surface of a substrate and a method for manufacturing the same.

Another object of the present invention is to provide a light emitting diode chip capable of performing optical conversion such as wavelength conversion and bonding a bonding wire easily, and a method for manufacturing the same.

Another object of the present invention is to provide a light emitting diode chip that can prevent the light converted by the wavelength conversion layer from entering the light emitting diode chip again and being lost.

Still another object is to provide a light emitting diode chip capable of mitigating damage to the wavelength conversion layer by light.

In order to achieve the above object, a light emitting diode chip according to an embodiment of the present invention includes a substrate, a gallium nitride-based compound semiconductor stacked structure positioned on the substrate, a first conductive semiconductor layer, an active semiconductor layer, A semiconductor stacked structure having a layer and a second conductivity type semiconductor layer, an electrode electrically connected to the semiconductor stacked structure, an additional electrode formed on the electrode, and a semiconductor stacked structure A wavelength conversion layer covering the top. Furthermore, the additional electrode penetrates the wavelength conversion layer. By employing the additional electrode, it is possible to provide a light-emitting diode chip capable of performing wavelength conversion and easily bonding wires.

The light emitting diode chip may further include a spacer layer interposed between the wavelength conversion layer and the semiconductor multilayer structure. The spacer layer is formed of an insulating layer. Further, the spacer layer may include a distributed Bragg reflector (DBR), and further includes a stress relaxation layer interposed between the distributed Bragg reflector and the semiconductor multilayer structure. You may have.

The spacer layer is interposed between the wavelength conversion layer and the semiconductor multilayer structure, and separates the wavelength conversion layer from the semiconductor multilayer structure. The spacer layer prevents yellowing of the phosphor in the wavelength conversion layer, which is generated by light emitted from the semiconductor multilayer structure.

The distributed Bragg reflector may be formed by alternately laminating insulating layers having different refractive indexes, for example, SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ . The distributed Bragg reflector may be formed so as to transmit light generated by the active layer and reflect light converted by the wavelength conversion layer by adjusting the optical thickness of these insulating layers. Good.

On the other hand, the stress relaxation layer relieves stress induced in the distributed Bragg reflector, and prevents the distributed Bragg reflector from peeling from its lower layer, for example, a semiconductor multilayer structure. The stress relaxation layer may be formed of spin-on glass (SOG) or a porous silicon oxide film.

On the other hand, a high-hardness transparent resin may cover the wavelength conversion layer. Here, the high hardness transparent resin means a resin having a durometer shore hardness of 60 Shore A or more.

In some embodiments, the light emitting diode chip may further include a lower distributed Bragg reflector located on a lower surface of the substrate. The lower distributed Bragg reflector may have a relatively high reflectance with respect to not only the light generated in the active layer but also substantially the entire visible light region. For example, the lower distributed Bragg reflector may have a reflectance of 90% or more for blue region light, green region light, and red region light. A metal layer may be located on the lower distributed Bragg reflector. The metal layer may be formed of a reflective metal.

On the other hand, the additional electrode may have a narrower width than that of the electrode, or the width may be narrower as the distance from the electrode increases. Accordingly, the additional electrode can be stably attached to the electrode, and thereafter, the reliability of the process of bonding the wire can be ensured.

In some embodiments, the top surface of the wavelength conversion layer is substantially flat. In another embodiment, the upper surface of the wavelength conversion layer may be formed uniformly along the topology of the semiconductor multilayer structure.

In some embodiments, an electrode electrically connected to the semiconductor stacked structure includes a first electrode electrically connected to the first conductivity type semiconductor layer, and an electrode connected to the second conductivity type semiconductor layer. You may have the 2nd electrode electrically connected. The additional electrode may include a first additional electrode formed on the first electrode and a second additional electrode formed on the second electrode. The first additional electrode and the second additional electrode penetrate through the wavelength conversion layer and are exposed to the outside of the light emitting diode chip. Further, the upper surfaces of the first additional electrode and the second additional electrode may coincide with the upper surface of the wavelength conversion layer.

Unlike this, the electrode electrically connected to the semiconductor multilayer structure may be electrically connected to the first conductive type semiconductor layer. The second conductive semiconductor layer is located between the substrate and the first conductive semiconductor layer. In this case, the additional electrode may not be formed on the electrode connected to the second conductive semiconductor layer.

Furthermore, the wavelength conversion layer may cover a side surface of the substrate. Therefore, wavelength conversion can also be performed on light emitted from the side surface of the substrate. The thickness of the wavelength conversion layer on the side surface of the substrate may be substantially the same as the thickness of the wavelength conversion layer above the semiconductor multilayer structure.

A light emitting diode chip according to still another embodiment of the present invention includes a substrate and a plurality of semiconductor stacks disposed on the substrate, each having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A structure, a first electrode electrically connected to one of the plurality of semiconductor multilayer structures, and another semiconductor multilayer structure of the plurality of semiconductor multilayer structures A second electrode connected to the first electrode, a first additional electrode formed on the first electrode, a second additional electrode formed on the second electrode, and the plurality of semiconductor stacked structures. A wavelength conversion layer covering the top. The first additional electrode and the second additional electrode pass through the wavelength conversion layer.

Furthermore, you may further have the wiring which electrically connects the said some semiconductor laminated structure mutually.

On the other hand, the light emitting diode chip may further include a spacer layer interposed between the wavelength conversion layer and the plurality of semiconductor multilayer structures. The spacer layer is formed of an insulating layer. Furthermore, the spacer layer may further include a distributed Bragg reflector interposed between the wavelength conversion layer and the plurality of semiconductor multilayer structures. A stress relaxation layer may be interposed between the distributed Bragg reflector and the plurality of semiconductor multilayer structures.

The first and second additional electrodes may have a narrower width than the first and second electrodes, respectively, and the first and second additional electrodes may be the first and second electrodes, respectively. The distance from the second electrode may decrease.

On the other hand, the first electrode is electrically connected to the first conductive semiconductor layer of the one semiconductor multilayer structure, and the second electrode is the semiconductor multilayer structure or another semiconductor multilayer structure. The second conductive type semiconductor layer may be electrically connected.

According to another embodiment of the present invention, a light emitting diode package having a light emitting diode chip mounted thereon is provided. The package includes a lead terminal, the above-described light emitting diode chip, and a bonding wire for connecting the lead terminal and the light emitting diode chip. The bonding wire connects the additional electrode of the light emitting diode chip and the lead terminal.

A method of manufacturing a light emitting diode chip according to another embodiment of the present invention includes arranging a plurality of bare chips on a support substrate, and each bare chip includes a substrate and a gallium nitride-based compound semiconductor stack positioned on the substrate. A structure comprising a semiconductor stacked structure having a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and an electrode electrically connected to the semiconductor stacked structure. Forming an additional electrode on the electrode of each bare chip, forming a transparent coating layer covering the plurality of bare chips and the additional electrode on the support substrate, and removing the upper portion of the transparent coating layer to form the additional electrode Exposing the substrate, removing the support substrate, and separating the transparent coating layer into individual light emitting diode chips.

Since the uniform transparent coating layer is formed on the bare chip on the support substrate, the uniform transparent coating layer can be formed also on the substrate side of the bare chip. Moreover, by using an additional electrode, a transparent coating layer can be formed with a uniform thickness on the bare chip, and the wire can be easily bonded. Furthermore, since the support substrate can be removed, the heat radiation path of the light generated in the active layer can be shortened.

The transparent coating layer may contain various materials depending on the purpose of use. For example, the transparent coating layer may include a phosphor or a diffusing material, but is not limited thereto. Therefore, the transparent coating layer is used as a wavelength conversion layer or a diffusion layer.

The electrode electrically connected to the semiconductor stacked structure has a first electrode electrically connected to the first conductive semiconductor layer and a second electrode electrically connected to the second conductive semiconductor layer. You may have an electrode. In addition, forming the additional electrode may include forming a first additional electrode on the first electrode and forming a second additional electrode on the second electrode.

The top surfaces of the first additional electrode and the second additional electrode may be positioned at the same height. Accordingly, after the upper portion of the transparent coating layer is removed, the upper surface of the transparent coating layer and the upper surfaces of the first and second additional electrodes can be positioned on the same surface.

In some embodiments, forming the additional electrode may be performed in advance before arranging the bare chip on a support substrate. In another embodiment, forming the additional electrode may be performed after the bare chip is arranged on a support substrate.

Furthermore, the manufacturing method may further include forming a spacer layer covering the bare chips arranged on the support substrate before forming the transparent coating layer.

The spacer layer may be formed of a single insulating layer or a plurality of insulating layers, and may be formed of a transparent resin, a silicon oxide film, or a silicon nitride film. The spacer layer may further include a stress relaxation layer, and the distributed Bragg reflector may be formed on the stress relaxation layer.

In some embodiments, the bare chip may further include a distributed Bragg reflector located on top of the semiconductor stacked structure. The bare chip may further include a stress relaxation layer interposed between the distributed Bragg reflector and the semiconductor multilayer structure.

Meanwhile, the removal of the support substrate may be performed before separating the transparent coating layer, but is not limited thereto, and is performed before removing the upper portion of the transparent coating layer. It may be performed after separating the transparent coating layer.

In some embodiments, the bare chip may include a plurality of semiconductor stacked structures positioned on the substrate. Furthermore, the bare chip may further include wiring for connecting the plurality of semiconductor stacked structures to each other.

Further, the bare chip may further include a spacer layer positioned on top of the plurality of semiconductor stacked structures. The spacer layer may be formed of an insulating layer and may have a distributed Bragg reflector. The spacer layer may further include a stress relaxation layer interposed between the distributed Bragg reflector and the plurality of semiconductor multilayer structures.

A light emitting diode package according to another embodiment of the present invention includes a submount substrate, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and the first conductive semiconductor layer. A first electrode electrically connected to the second conductive type semiconductor layer and a second electrode electrically connected to the second conductive type semiconductor layer, wherein at least one of the first electrode and the second electrode is disposed on an upper surface thereof. The bare chip mounted on the submount substrate and at least one of the first electrode and the second electrode formed on the top surface of the bare chip are exposed, and the top surface and side surfaces of the bare chip are integrally covered. A wavelength conversion layer covering at least a part of the upper surface of the submount substrate.

Here, the submount substrate may have a plurality of slits formed along a side surface of the bare chip.

Each of the plurality of slits may have an opening shape.

The wavelength conversion layer may cover an inner side surface of the submount substrate through at least a part of the plurality of slits.

Meanwhile, the submount substrate and the bare chip may be metal bonded.

The light emitting diode package encapsulates the substrate on which a power supply lead is formed, a bonding wire that electrically connects the power supply lead to the first electrode and the second electrode, and the bare chip. And a lens to be used.

A method of manufacturing a light emitting diode package according to another embodiment of the present invention includes a step of preparing a submount substrate, each of which includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. Mounting a plurality of bare chips on the submount substrate; forming a first electrode electrically connected to the first conductive semiconductor layer; and electrically connecting the second conductive semiconductor layer to the second conductive semiconductor layer Forming a second electrode to be connected; exposing at least one of the first electrode and the second electrode formed on the top surface of the bare chip; integrally covering a top surface and a side surface of the bare chip; Forming a wavelength conversion layer covering a part of the upper surface of the submount substrate.

Here, the step of forming the first electrode and the second electrode may include a step of forming at least one of the first electrode and the second electrode on an upper surface of the bare chip.

On the other hand, in the method of manufacturing the light emitting diode package, the first electrode and the second electrode are pressurized using a mold, and a gap is formed between the mold and the first electrode and the second electrode. It may further include a step of preventing it from occurring.

Here, the step of forming the wavelength conversion layer may include a step of injecting and curing a resin containing a phosphor in the internal space of the mold.

Meanwhile, the step of preparing the submount substrate may include a step of forming a plurality of slits along a region where the bare chip is mounted.

Here, each of the plurality of slits may have an opening shape.

In addition, the step of forming the wavelength conversion layer may include the step of forming the wavelength conversion layer so as to cover an inner side surface of the submount substrate through at least a part of the plurality of slits.

The method for manufacturing the light emitting diode package may further include a step of forming a transparent resin layer between the wavelength conversion layer and the bare chip.

Meanwhile, the method of manufacturing the light emitting diode package may further include a step of dicing the submount substrate in units of individual light emitting diode chips.

Here, in the method for manufacturing the light emitting diode package, the step of mounting the diced individual bare chip on a substrate having leads, and electrically connecting the first electrode and the second electrode to bonding wires, respectively. And a step of forming a lens for sealing the individual light emitting diode chip.

According to the present invention, it is possible to provide a light-emitting diode chip capable of performing wavelength conversion on light emitted from the side surface of a substrate.

Further, by employing the additional electrode, it is possible to provide a light emitting diode chip that can easily perform wire bonding while performing wavelength conversion.

Further, by employing the spacer layer, it is possible to prevent the phosphor in the wavelength conversion layer from being damaged by the light emitted from the semiconductor multilayer structure.

In addition, since the spacer layer includes a distributed Bragg reflector, light converted by the wavelength conversion layer can be prevented from entering the semiconductor multilayer structure again, and light efficiency can be improved. .

1 is a cross-sectional view illustrating a light emitting diode chip according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention. 1 is a cross-sectional view illustrating a light emitting diode package having a light emitting diode chip according to an embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode chip by one Embodiment of this invention. FIG. 6 is a top plan view illustrating a light emitting diode according to another embodiment of the present invention. It is sectional drawing by the C-C 'line | wire of the light emitting diode shown in FIG. It is a figure which shows the submount board | substrate with which the some light emitting diode was formed by one Embodiment of this invention. It is the figure which expanded the area | region shown with the circle | round | yen in FIG. 3 is a flowchart for explaining a method of manufacturing a light emitting diode package according to an embodiment of the present invention; FIG. 5 is a view illustrating a method of manufacturing a light emitting diode package according to an embodiment of the present invention, step by step. 1 is a cross-sectional view illustrating a light emitting diode package including a light emitting diode according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples in order to fully convey the idea of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments described later, and can be embodied in other forms. In the drawings, the width, length, thickness, and the like of components may be exaggerated for convenience of explanation. Throughout the specification, identical reference numbers indicate identical components.

FIG. 1 is a cross-sectional view illustrating a light emitting diode chip 101 according to an embodiment of the present invention.

The light-emitting diode chip 101 includes a substrate 21, a first conductive semiconductor layer 25, an active layer 27, and a gallium nitride-based semiconductor stacked structure 30 having a second conductive semiconductor layer 29, a first electrode 41, and a second electrode. Electrode 42, first additional electrode 43, second additional electrode 44, and transparent coating layer, for example, wavelength conversion layer 50. Further, the buffer layer 23 may be interposed between the first conductive type semiconductor layer 25 and the substrate 21.

The substrate 21 has an upper surface where the semiconductor multilayer structure is located, a lower surface facing the upper surface, and a side surface connecting the upper surface and the lower surface. The substrate 21 is not particularly limited as long as it is a transparent substrate, and may be a substrate on which a nitride semiconductor layer can be grown, for example, sapphire, silicon carbide, spinel, or a silicon substrate. The substrate 21 may be relatively thicker than the semiconductor multilayer structure, and a part of the light generated by the semiconductor multilayer structure may be emitted from the side surface of the substrate 21.

The active layer 27 and the first and second conductive semiconductor layers 25 and 29 may be formed of a group III nitride compound semiconductor, for example, an (Al, Ga, In) N semiconductor. Each of the first conductive semiconductor layer 25 and the second conductive semiconductor layer 29 may be a single layer or multiple layers. For example, the first conductive semiconductor layer 25 and / or the second conductive semiconductor layer 29 may have a contact layer and a cladding layer, and may have a superlattice layer. The active layer 27 may have a single quantum well structure or a multiple quantum well structure. For example, the first conductive semiconductor layer may be n-type and the second conductive semiconductor layer may be p-type, but is not limited to this, and may be vice versa. The buffer layer 23 relaxes lattice mismatch between the substrate 21 and the first conductivity type semiconductor layer 25, and reduces the density of defects generated in the semiconductor layers 25, 27, and 29.

On the other hand, the first electrode 41 contacts the exposed surface of the first conductive semiconductor layer 25 and is electrically connected to the first conductive semiconductor layer 25. The second electrode 42 is located on the second conductive semiconductor layer 29 and is electrically connected to the second conductive semiconductor layer 29. The first electrode 41 and the second electrode 42 may include, for example, Ti, Cu, Ni, Al, Au, or Cr, and may be formed of two or more of these materials. Further, a transparent electrode layer such as Ni / Au, ITO, IZO, ZnO for current distribution may be formed on the second conductive type semiconductor layer 29, and the second electrode 42 is formed of a transparent conductive layer. You may connect to the layers.

The first additional electrode 43 and the second additional electrode 44 are located on the first electrode 41 and the second electrode 42, respectively. The first additional electrode 43 and the second additional electrode 44 have a narrower width than the widths of the first electrode 41 and the second electrode 42, respectively. That is, the first additional electrode 43 and the second additional electrode 44 are limited to the upper portions of the first electrode 41 and the second electrode 42, respectively. In addition, the first additional electrode 43 and the second additional electrode 44 may have a shape in which the width decreases as the distance from the first electrode 41 and the second electrode 42 increases. With such a shape, the first additional electrode 43 and the second additional electrode 44 can be stably adhered to and maintained on the first electrode 41 and the second electrode 42, respectively, and subsequent processes such as wire bonding can be performed. It is advantageous to the process. The ratio of the height to the bottom surface is limited within a predetermined range so that the first additional electrode 43 and the second additional electrode 44 are stably maintained on the first electrode 41 and the second electrode 42. Can do.

The wavelength conversion layer 50 may be formed by containing a phosphor in epoxy or silicon, or may be formed only by the phosphor. For example, the wavelength conversion layer 50 may be formed by coating phosphor after containing phosphor in epoxy or silicon. In this case, a mold may be used so that the wavelength conversion layer 50 having a uniform thickness is formed on the side surface of the substrate 21. At this time, the wavelength conversion layer 50 may be formed by arranging the mold so that the whole or part of the upper surfaces of the first additional electrode 43 and the second additional electrode 44 may be exposed, or the first additional electrode. 43 and the second additional electrode 44 are coated so as to cover the phosphor, and then the resin is mechanically polished so that the upper surfaces of the first additional electrode 43 and the second additional electrode 44 are covered. Can be exposed. Accordingly, the wavelength conversion layer 50 having a flat upper surface may be formed, and the first additional electrode 43 and the second additional electrode 44 penetrate the wavelength conversion layer 50 and are exposed to the outside of the light emitting diode chip.

Furthermore, the wavelength conversion layer 50 may have, for example, a refractive index in the range of 1.4 to 2.0. In order to adjust the refractive index, TiO ₂ , SiO ₂ , Y ₂ O _3, etc. May be mixed in the wavelength conversion layer 50.

On the other hand, as illustrated, the upper surface of the first additional electrode 43 may be positioned at the same height as the upper surface of the second additional electrode 44. Therefore, when the second conductive semiconductor layer 29 and a part of the active layer 27 are removed and the first conductive semiconductor layer 25 is exposed, the first additional electrode 43 is formed as shown in FIG. It may be longer than the additional electrode 44.

The wavelength conversion layer 50 may cover the side surface of the substrate 21 and the upper portion of the semiconductor multilayer structure 30. Therefore, the light emitting diode chip 101 capable of performing wavelength conversion not only on the light emitted from the upper surface of the semiconductor multilayer structure 30 but also on the light emitted from the side surface of the substrate 21 is provided.

FIG. 2 is a cross-sectional view illustrating a light emitting diode chip 102 according to another embodiment of the present invention.

Referring to FIG. 2, the LED chip 102 according to the present embodiment is substantially similar to the LED chip 101 of FIG. 1, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. Is different. In addition, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31. Detailed descriptions of the same components as those of the light-emitting diode chip 101 of the above-described embodiment will be omitted to avoid duplication.

The spacer layer 33 may cover the top of the semiconductor multilayer structure 30 and the transparent conductive layer 31. The wavelength conversion layer 50 is separated from the semiconductor multilayer structure 30 by the spacer layer 33. The spacer layer 33 may be formed of, for example, silicon nitride or silicon oxide. The spacer layer 33 may be formed of a distributed Bragg reflector in which insulating layers having different refractive indexes, for example, SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ are alternately stacked. In this case, by adjusting the optical thickness of the insulating layer having a different refractive index, the spacer layer 33 transmits the light generated by the active layer 27 and transmits the light incident from the outside or converted by the wavelength conversion layer 50. Can be reflected. Such a distributed Bragg reflector has a reflection band that reflects light in the long wavelength region of the visible light region and transmits short wavelength visible light or ultraviolet light generated by the active layer 27. In particular, since the light absorption rate of Nb ₂ O ₅ is relatively smaller than that of TiO ₂ , it is more preferable to form a distributed Bragg reflector using SiO ₂ / Nb ₂ O ₅ in order to prevent light loss. .

On the other hand, a lower distributed Bragg reflector 45 is located below the substrate 21. The lower distributed Bragg reflector 45 is formed by alternately laminating insulating layers having different refractive indexes, and not only light in the blue wavelength region, for example, light generated in the active layer 27, but also light in the yellow wavelength region or green color. And / or relatively high reflectance for light in the red wavelength region, preferably 90% or higher. Furthermore, the lower distributed Bragg reflector 45 may have a reflectance of 90% or more as a whole over a wavelength range of 400 to 700 nm, for example.

The lower distributed Bragg reflector 45 having a relatively high reflectance over a wide wavelength region is formed by controlling the optical thicknesses of the material layers that are repeatedly stacked. The lower distributed Bragg reflector 45 is formed, for example, by alternately stacking a first layer of SiO _{2 and} a second layer of TiO ₂ , or alternately forming a first layer of SiO _{2 and} a second layer of Nb ₂ O ₅ . It may be formed by laminating. Since the light absorption rate of Nb ₂ O ₅ is relatively smaller than that of TiO ₂ , it is more preferable to alternately stack the first layer of SiO _{2 and} the second layer of Nb ₂ O ₅ . As the number of stacked layers of the first layer and the second layer increases, the reflectance of the distributed Bragg reflector 45 becomes more stable. For example, the number of stacked layers of the lower distributed Bragg reflector 45 is 50 layers or more, that is, 25 It may be a pair or more.

In the lower distributed Bragg reflector 45, it is not necessary that the first layer or the second layer alternately stacked have the same thickness, and not only the wavelength of the light generated in the active layer 27 but also other visible regions. The thicknesses of the first layer and the second layer are selected so as to have a relatively high reflectance with respect to the wavelength. Alternatively, the lower distributed Bragg reflector 45 can be formed by stacking a plurality of distributed Bragg reflectors having a high reflectance with respect to a specific wavelength band.

By adopting the lower distributed Bragg reflector 45, when the light converted by the wavelength conversion layer 50 is incident on the substrate 21 side again, the incident light can be reflected again and emitted to the outside. Thereby, the light efficiency can be improved.

On the other hand, the uppermost layer and the lowermost layer of the distributed Bragg reflector 45 may be SiO ₂ . By disposing SiO ₂ on the uppermost layer and the lowermost layer of the distributed Bragg reflector 45, the distributed Bragg reflector 45 can be stably attached to the substrate 21, and the lower distributed Bragg using the lowermost SiO ₂ layer. The reflector 45 can be protected.

The metal layer 47 is located below the lower distributed Bragg reflector 45. The metal layer 47 may be formed of a reflective metal such as aluminum in order to reflect the light transmitted through the lower distributed Bragg reflector 45, but may be formed of a metal other than the reflective metal. Furthermore, the metal layer 47 easily releases the heat generated in the stacked structure 30 to the outside, and improves the heat release performance of the light emitting diode chip 102.

According to the present embodiment, the spacer layer 33 is formed by a distributed Bragg reflector having a high reflectivity with respect to visible light having a long wavelength, so that the light converted by the wavelength conversion layer 50 is re-entered into the semiconductor multilayer structure 30. Incident light can be prevented. Further, by adopting the lower distributed Bragg reflector 45, when light incident on the substrate 21 side from the outside or light converted by the wavelength conversion layer 50 enters the substrate 21 side, it can be reflected again. , Can improve the light efficiency.

FIG. 3 is a cross-sectional view illustrating a light emitting diode chip 103 according to another embodiment of the present invention.

Referring to FIG. 3, the light emitting diode chip 103 is similar to the light emitting diode chip 102 described with reference to FIG. 2, but in addition to the spacer layer 33 or in place of the spacer layer 33, the stress relaxation layer 35. The upper distributed Bragg reflector 37 is interposed between the wavelength conversion layer 50 and the semiconductor multilayer structure 30. In other words, the stress relaxation layer 35 may be positioned on the semiconductor stacked structure 30, for example, on the spacer layer 33, and the upper distributed Bragg reflector 37 is positioned thereon. The stress relaxation layer 35 and the upper distributed Bragg reflector 37 also function as a spacer layer.

The upper distributed Bragg reflector 37 may be formed by alternately stacking insulating layers having different refractive indexes, for example, SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ . In this case, by adjusting the optical thickness of the insulating layers having different refractive indexes, the upper distributed Bragg reflector 37 transmits the light generated in the active layer 27 and is incident from the outside or converted by the wavelength conversion layer 50. Can reflect the light. The upper distributed Bragg reflector 37 has a reflection band that reflects light in the long wavelength region in the visible light region and transmits short wavelength visible light or ultraviolet light generated by the active layer 27. In particular, since the light absorption rate of Nb ₂ O ₅ is relatively smaller than that of TiO ₂ , it is more preferable to form a distributed Bragg reflector using SiO ₂ / Nb ₂ O ₅ in order to prevent light loss. .

On the other hand, the stress relaxation layer 35 may be formed of spin-on glass (SOG) or a porous silicon oxide film. The stress relaxation layer 35 relieves the stress of the upper distributed Bragg reflector 37 and prevents the upper distributed Bragg reflector 37 from peeling off.

When insulating layers having different refractive indexes, for example, SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ are alternately stacked to form the upper distributed Bragg reflector 37, relatively high-density layers are stacked. Therefore, the stress generated in the distributed Bragg reflector is increased. Thereby, the distributed Bragg reflector is easily peeled from the lower layer, for example, the spacer layer 33. Therefore, by disposing the stress relaxation layer 35 below the upper distributed Bragg reflector 37, the upper distributed Bragg reflector 37 can be prevented from peeling off.

On the other hand, in the present embodiment, the spacer layer 33 may be formed of a single layer, for example, silicon nitride or silicon oxide, or may be omitted.

FIG. 4 is a cross-sectional view illustrating a light emitting diode chip 104 according to another embodiment of the present invention.

Referring to FIG. 4, the horizontal light emitting diode chips 101, 102, and 103 are described as examples in FIGS. 1 to 3, but the light emitting diode chip 104 is a vertical light emitting diode chip. The light-emitting diode chip 104 includes a semiconductor stacked structure 30 having a substrate 51, a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29, an upper electrode 41, an additional electrode 43, and wavelength conversion. It has a layer 60. The wavelength conversion layer 60 is separated from the semiconductor multilayer structure 30 by the spacer layer. For example, the spacer layer may include the spacer layer 33 as described with reference to FIG. 2, and the spacer layer 33, the stress relaxation layer 35, and / or the upper portion as described with reference to FIG. A distributed Bragg reflector 37 may be included. Further, the light emitting diode chip 104 may include a reflective metal layer 55, a barrier metal layer 57, and a bonding metal 53.

Unlike the growth substrate for growing the semiconductor layers 25, 27, and 29, the substrate 51 is a secondary substrate attached to the already grown compound semiconductor layers 25, 27, and 29. The substrate 51 may be a conductive substrate, for example, a metal substrate or a semiconductor substrate, but is not limited thereto, and may be an insulating substrate such as sapphire.

The semiconductor stacked structure 30 is located on the substrate 51 and includes a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29. Here, in the semiconductor stacked structure 30, the p-type compound semiconductor layer 29 is located closer to the substrate 51 side than the n-type compound semiconductor layer 25, as in a general vertical light emitting diode. The semiconductor stacked structure 30 may be located on a partial region of the substrate 51. That is, the substrate 51 may have a relatively large area as compared with the semiconductor stacked structure 30, and the semiconductor stacked structure 30 may be located in a region surrounded by the periphery of the substrate 51.

Since the first conductive semiconductor layer 25, the active layer 27, and the second conductive semiconductor layer 29 are similar to the semiconductor layer described with reference to FIG. 1, detailed description thereof is omitted. On the other hand, a rough surface is formed on the upper surface of the n-type compound semiconductor layer 25 by positioning the n-type compound semiconductor layer 25 having a relatively low resistance on the opposite side of the substrate 51.

A reflective metal layer 55 may be interposed between the substrate 51 and the semiconductor multilayer structure 30, and a barrier metal layer 57 may be interposed between the substrate 51 and the reflective metal layer 55 so as to surround the reflective metal layer 55. . Further, the substrate 51 is bonded to the semiconductor multilayer structure 30 via the bonding metal 53. The reflective metal layer 55 and the barrier metal layer 57 can function as a lower electrode electrically connected to the second conductive type semiconductor layer 29.

On the other hand, the wavelength conversion layer 60 is located above the semiconductor multilayer structure 30. The wavelength conversion layer 60 may be limited to the upper portion of the semiconductor multilayer structure 30, but is not limited thereto, and may cover the side surface of the semiconductor multilayer structure 30 and further the side surface of the substrate 51.

The spacer layer 33 may cover the upper surface of the semiconductor multilayer structure 30, and the stress relaxation layer 35 and the upper distributed Bragg reflector 37 may be sequentially disposed thereon. Since the spacer layer 33, the stress relaxation layer 35, and the upper distributed Bragg reflector 37 may be formed of the same material as described with reference to FIG. 3, detailed description is omitted to avoid duplication. To do. The spacer layer 33 may be omitted. The spacer layer 33 may be a distributed Bragg reflector as described in the embodiment of FIG. 2, and in this case, the stress relaxation layer 35 and the upper distributed Bragg reflector 37 may be omitted.

On the other hand, the upper electrode 41 is positioned on the semiconductor stacked structure 30, for example, the first conductive semiconductor layer 25, and is electrically connected to the first conductive semiconductor layer 25, and the additional electrode 43 is on the upper electrode 41. Located in. The additional electrode 43 may have the same shape and structure as the first additional electrode 43 or the second additional electrode 44 described with reference to FIG. The additional electrode 43 is exposed from the wavelength conversion layer 60 to the outside.

FIG. 5 is a cross-sectional view illustrating a light emitting diode chip 105 according to another embodiment of the present invention.

Referring to FIG. 5, the light-emitting diode chip 105 is substantially similar to the light-emitting diode chip 101 described with reference to FIG. 1, except that the wavelength conversion layer 50 is separated from the semiconductor multilayer structure 30. That is, the spacer layer 61 is interposed between the wavelength conversion layer 50 and the semiconductor multilayer structure 30.

Since the wavelength conversion layer 50 is separated from the semiconductor multilayer structure 30, it is possible to prevent the resin or phosphor of the wavelength conversion layer 50 from being deteriorated by the light generated in the active layer 27. The spacer layer 61 may be interposed between the side surface of the substrate 21 and the wavelength conversion layer 50.

The spacer layer 61 may be formed of a transparent resin, a silicon oxide film, or a silicon nitride film. In order to reduce the heat transferred to the phosphor, the spacer layer 61 is more advantageous as the thermal conductivity is lower. For example, the spacer layer 61 may have a thermal conductivity of less than 3 W / mK. When the spacer layer 61 is formed of a transparent resin, powders such as TiO ₂ , SiO ₂ , and Y ₂ O ₃ may be mixed in the transparent resin in order to adjust the refractive index of the transparent resin. Furthermore, the spacer layer 61 may be formed of a plurality of layers as well as a single layer. By adjusting the refractive index and thickness of the plurality of layers constituting the spacer layer 61, the light generated by the active layer 27 is reflected, and the light that is converted by the wavelength conversion layer 50 and enters the light emitting diode chip 105 The spacer layer 61 may be formed so as to reflect. For example, by repeatedly laminating layers having different refractive indexes, for example, TiO ₂ and SiO ₂ , the light generated by the active layer 27 is selectively transmitted or the light converted by the wavelength conversion layer 50 is reflected. A distributed Bragg reflector may be formed. Furthermore, when the spacer layer 61 includes a distributed Bragg reflector, the light emitting diode shown in FIG. 6 is provided between the semiconductor multilayer structure 30 and the distributed Bragg reflector in order to prevent the distributed Bragg reflector from peeling off. A stress relaxation layer 62 may be interposed as in the example of the chip 106.

FIG. 7 is a cross-sectional view illustrating a light emitting diode chip 107 according to another embodiment of the present invention.

Referring to FIG. 7, the light emitting diode chip 107 is substantially similar to the light emitting diode chip 105 described with reference to FIG. 5, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. That is different. In addition, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31. The spacer layer 61 covers the spacer layer 33 and further separates the wavelength conversion layer 50 from the semiconductor multilayer structure 30. Further, when the spacer layer 61 is a distributed Bragg reflector, a stress relaxation layer 62 as shown in FIG. 6 is interposed between the spacer layer 61 and the semiconductor multilayer structure 30 in order to prevent the spacer layer 61 from peeling. May be interposed.

Since the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 are the same as those described with reference to FIG. 2, detailed description thereof is omitted to avoid duplication. Furthermore, as described with reference to FIG. 3, the upper distributed Bragg reflector 37 and the stress relaxation layer 35 may be located on the upper portion of the semiconductor multilayer structure 30. The structure 30 can be further separated.

FIG. 8 is a cross-sectional view illustrating a light emitting diode chip 108 according to another embodiment of the present invention.

Referring to FIG. 8, the light emitting diode chip 108 is substantially similar to the light emitting diode chip 105 described with reference to FIG. 5, except that a transparent resin 63 is added on the wavelength conversion layer 50. That is, the transparent resin 63 covers the wavelength conversion layer 50. The transparent resin 63 protects the phosphor from external moisture. In order to prevent moisture absorption, the transparent resin 63 preferably has a high hardness, for example, a durometer shore hardness of 60 A or more. The high-hardness transparent resin 63 may have a higher hardness than the transparent resin of the spacer layer 61 when the spacer layer 61 is formed of a transparent resin.

Furthermore, in order to adjust the refractive index of the high-hardness transparent resin 63, powders such as TiO ₂ , SiO ₂ , Y ₂ O ₃ may be mixed in the transparent resin 63.

FIG. 9 is a cross-sectional view illustrating a light emitting diode chip 109 according to another embodiment of the present invention.

Referring to FIG. 9, the light emitting diode chip 109 is substantially similar to the light emitting diode chip 108 described with reference to FIG. 8, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. That is different. Further, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31. The spacer layer 61 covers the spacer layer 33 and further separates the wavelength conversion layer 50 from the semiconductor multilayer structure 30.

Since the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 are the same as those described with reference to FIG. 2, detailed description thereof is omitted to avoid duplication. Furthermore, as described with reference to FIG. 3, the upper distributed Bragg reflector 37 and the stress relaxation layer 35 may be located on the upper portion of the semiconductor multilayer structure 30. The structure 30 can be further separated.

FIG. 10 is a cross-sectional view illustrating a light emitting diode chip 110 according to another embodiment of the present invention.

Referring to FIG. 10, the light emitting diode chip 110 is substantially similar to the light emitting diode chip 101 described with reference to FIG. 1, but the upper surface of the first additional electrode 43 is higher than the upper surface of the second additional electrode 44. It is different that it is located lower.

Thereby, the upper surface of the wavelength conversion layer 70 is substantially flat, but has a stepped shape near the first additional electrode 43. The wavelength conversion layer 70 having such a shape may be manufactured using a mold specially manufactured along the surface shape of the semiconductor multilayer structure.

FIG. 11 is a cross-sectional view illustrating a light emitting diode chip 111 according to another embodiment of the present invention.

Referring to FIG. 11, the light emitting diode chip 111 is substantially similar to the light emitting diode chip 110 described with reference to FIG. 10, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. That is different. In addition, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31.

Since the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 are the same as those described with reference to FIG. 2, detailed description thereof is omitted to avoid duplication. Furthermore, as described with reference to FIG. 3, the stress relaxation layer 35 and the upper distributed Bragg reflector 37 may be interposed between the wavelength conversion layer 70 and the semiconductor multilayer structure 30.

FIG. 12 is a cross-sectional view illustrating a light emitting diode chip 112 according to another embodiment of the present invention.

Referring to FIG. 12, the light emitting diode chip 112 is substantially similar to the light emitting diode chip 110 described with reference to FIG. 10, except that the wavelength conversion layer 70 is separated from the semiconductor multilayer structure 30. That is, the spacer layer 71 is interposed between the wavelength conversion layer 70 and the semiconductor multilayer structure as described with reference to FIG. By separating the wavelength conversion layer 70 from the semiconductor multilayer structure, it is possible to prevent the resin or phosphor of the wavelength conversion layer 70 from being deteriorated by the light generated in the active layer 27. The spacer layer 71 may be interposed between the side surface of the substrate 21 and the wavelength conversion layer 70.

When the spacer layer 71 has a distributed Bragg reflector, the stress relaxation layer 62 described with reference to FIG. 6 may be interposed between the spacer layer 71 and the semiconductor multilayer structure 30.

FIG. 13 is a cross-sectional view illustrating a light emitting diode chip 113 according to another embodiment of the present invention.

Referring to FIG. 13, the light emitting diode chip 113 is substantially similar to the light emitting diode chip 112 described with reference to FIG. 12, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. That is different. In addition, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31. The spacer layer 71 covers the spacer layer 33 and further separates the wavelength conversion layer 70 from the semiconductor multilayer structure.

Since the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 are the same as those described with reference to FIG. 2, detailed description thereof is omitted to avoid duplication. Furthermore, as described with reference to FIG. 3, the upper distributed Bragg reflector 37 and the stress relaxation layer 35 may be positioned on the upper portion of the semiconductor multilayer structure 30. The structure 30 can be further separated.

FIG. 14 is a cross-sectional view illustrating a light emitting diode chip 114 according to another embodiment of the present invention.

Referring to FIG. 14, the light emitting diode chip 114 is substantially similar to the light emitting diode chip 112 described with reference to FIG. 12, except that a transparent resin 73 is added on the wavelength conversion layer 70. That is, the transparent resin 73 covers the wavelength conversion layer 70. The transparent resin 73 protects the phosphor from external moisture. In order to prevent moisture absorption, the transparent resin 73 preferably has a high hardness, for example, a durometer shore hardness of 60 A or more. When the spacer layer 71 is formed of a transparent resin, the high-hardness transparent resin 73 may have a higher hardness than the transparent resin of the spacer layer 71.

Furthermore, in order to adjust the refractive index of the high-hardness transparent resin 73, powders such as TiO ₂ , SiO ₂ , and Y ₂ O ₃ may be mixed in the transparent resin 73.

FIG. 15 is a cross-sectional view illustrating a light emitting diode chip 115 according to another embodiment of the present invention.

Referring to FIG. 15, the light emitting diode chip 115 is substantially similar to the light emitting diode chip 114 described with reference to FIG. 14, but further includes a spacer layer 33, a lower distributed Bragg reflector 45, and a metal layer 47. That is different. In addition, the transparent conductive layer 31 is interposed between the spacer layer 33 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure 30. The second electrode 42 may be connected to the transparent conductive layer 31. The spacer layer 71 covers the spacer layer 33 and further separates the wavelength conversion layer 50 from the semiconductor multilayer structure 30.

Since the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 are the same as those described with reference to FIG. 2, detailed description thereof is omitted to avoid duplication. Furthermore, as described with reference to FIG. 3, the upper distributed Bragg reflector 37 and the stress relaxation layer 35 may be positioned on the upper portion of the semiconductor multilayer structure 30. Further away from the structure 30.

FIG. 16 is a cross-sectional view illustrating a light emitting diode chip 116 according to another embodiment of the present invention.

Referring to FIG. 16, the light emitting diode chip 116 is substantially similar to the light emitting diode chip 101 described with reference to FIG. 1, except that a plurality of semiconductor multilayer structures 30 are located on the substrate 21. The plurality of semiconductor stacked structures may be electrically connected to each other by a wiring 83. The wiring 83 may form a series array by connecting the first conductive semiconductor layer 25 of one semiconductor stacked structure 30 and the second conductive semiconductor layer 29 of the semiconductor stacked structure 30 adjacent thereto. Such series arrays may be connected in parallel or anti-parallel.

On the other hand, in order to prevent the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 29 of the semiconductor multilayer structure from being short-circuited by the wiring 83, the insulating layer 81 is formed between the semiconductor multilayer structure and the wiring 83. It may be interposed between them. The insulating layer 81 also functions as a spacer layer that separates the semiconductor multilayer structure 30 and the wavelength conversion layer 50 from each other.

On the other hand, the first electrode 41 and the second electrode 42 may be located on different semiconductor stacked structures 30. Moreover, in this embodiment, the position in which the 1st electrode 41 and the 2nd electrode 42 are formed is not specifically limited. For example, the first electrode 41 and the second electrode 42 may all be formed on the substrate 21 or may be formed on the first conductive semiconductor layer 25 or the second conductive semiconductor layer 29. . In this case, the first electrode 41 and the second electrode 42 may be connected to different semiconductor multilayer structures 30 via the wiring 83. A first additional electrode 43 and a second additional electrode 44 are disposed on the first electrode 41 and the second electrode 42, respectively.

The wavelength conversion layer 50 covers the plurality of semiconductor multilayer structures 30. The wavelength conversion layer 50 may also cover the substrate 21. As described with reference to FIG. 5, the wavelength conversion layer 50 may be separated from the semiconductor multilayer structure by the spacer layer 61.

FIG. 17 is a cross-sectional view illustrating a light emitting diode chip 117 according to another embodiment of the present invention.

Referring to FIG. 17, the light emitting diode chip 117 is substantially similar to the light emitting diode chip 116 described with reference to FIG. 16, but the second insulating layer 85, the lower distributed Bragg reflector 45, and the metal layer 47. In order to facilitate the formation of the wiring 83, the side surface of the semiconductor multilayer structure 30 is formed to be inclined. Further, the transparent conductive layer 31 is located between the insulating layer 81 and each semiconductor multilayer structure 30, and the transparent conductive layer 31 is in ohmic contact with the second conductive type semiconductor layer 29. The wiring 83 connects the first conductive semiconductor layer 25 of one semiconductor stacked structure 30 to the second conductive semiconductor layer 29 (or the transparent conductive layer 31) of the semiconductor stacked structure 30 adjacent thereto. A series array can be formed, and such series arrays may be connected in parallel or anti-parallel.

On the other hand, the insulating layer 81 may cover the transparent conductive layer 31, and may further cover the side surface of the semiconductor multilayer structure 30. Further, in order to protect the semiconductor multilayer structure 30 and the wiring 83, the second insulating layer 85 may cover the semiconductor multilayer structure 30 and the wiring 83, and the second insulating layer 85 is composed of the insulating layer 81. Cover. The insulating layer 81 and the second insulating layer 85 may be formed of a material film of the same material, for example, a silicon oxide film or a silicon nitride film, or may be formed of a single layer. In this case, the second insulating layer 85 may be relatively thinner than the insulating layer 81 in order to prevent the second insulating layer 85 from peeling from the insulating layer 81.

Unlike this, the insulating layer 81 and / or the second insulating layer 85 is similar to the spacer layer 33 described with reference to FIG. 2, and is a distributed Bragg reflector in which insulating layers having different refractive indexes are alternately stacked. May be formed. Such a distributed Bragg reflector is formed so as to transmit the light generated by the active layer 27 and reflect the light converted by the wavelength conversion layer 50, as described with reference to FIG. Preferably, the second insulating layer 85 may be formed of a distributed Bragg reflector, and the insulating layer 81 may be formed of a stress relaxation layer such as SOG or a porous silicon oxide film.

The wavelength conversion layer 50 is located above the second insulating layer 85, and the insulating layer 81 and the second insulating layer 85 function as a spacer layer. In addition, a spacer layer 61 as described with reference to FIG. 5 may be interposed between the plurality of semiconductor stacked structures 30 and the wavelength conversion layer 50. Further, as described with reference to FIG. 8, the high-hardness transparent resin 63 may cover the wavelength conversion layer 50.

FIG. 18 is a cross-sectional view illustrating a light emitting diode chip 118 according to another embodiment of the present invention.

Referring to FIG. 18, the light emitting diode chip 118 is substantially similar to the light emitting diode chip 117 described with reference to FIG. 17 except that it further includes a stress relaxation layer 87 and an upper distributed Bragg reflector 89.

That is, the upper distributed Bragg reflector 89 may be positioned between the plurality of semiconductor multilayer structures 30 and the wavelength conversion layer 50. In addition, the upper distributed Bragg reflector 89 and the plurality of semiconductor multilayer structures The stress relaxation layer 87 may be positioned between Similar to the upper distributed Bragg reflector 37 described with reference to FIG. 3, the upper distributed Bragg reflector 89 may be formed by alternately stacking insulating layers having different refractive indexes. Further, the stress relaxation layer 87 may be formed of SOG or a porous silicon oxide film like the stress relaxation layer 35 of FIG. The upper distributed Bragg reflector 89 and the stress relaxation layer 87 also function as a spacer layer that separates the wavelength conversion layer 50 from the semiconductor multilayer structure 30.

In the present embodiment, the insulating layer 81 and the second insulating layer 85 may be formed as a single layer, and the second insulating layer 85 may be omitted.

In the above-described embodiments, the phosphor may be a YAG or TAG phosphor, a silicate phosphor, a nitride or an oxynitride phosphor. Furthermore, the wavelength conversion layer 50, 60, or 70 may include the same type of phosphor, but is not limited thereto, and may include two or more types of phosphor. In addition, although the wavelength conversion layer 50, 60, or 70 is illustrated and described as a single layer, a plurality of wavelength conversion layers may be used, and each of the plurality of wavelength conversion layers includes different phosphors. May be.

FIG. 19 is a cross-sectional view for explaining a light emitting diode package on which the light emitting diode chip 101 according to an embodiment of the present invention is mounted.

Referring to FIG. 19, the light emitting diode package includes a light emitting diode chip 101 and a mount 91 for mounting the light emitting diode chip 101. In addition, the light emitting diode package may include a bonding wire 95 and a lens 97.

The mount 91 may be, for example, a printed circuit board, a lead frame, a ceramic substrate, or the like, and includes lead terminals 93a and 93b. The first additional electrode (43 in FIG. 1) and the second additional electrode (44 in FIG. 1) of the light emitting diode chip 101 are electrically connected to the lead terminals 93a and 93b through bonding wires 95, respectively.

On the other hand, the lens 97 covers the light emitting diode chip 101. The lens 97 adjusts the directivity angle of the light emitted from the light emitting diode chip 101 so that the light is emitted in a desired direction. Since the wavelength conversion layer 50 is formed on the light emitting diode chip 101, the lens 97 does not need to contain a phosphor.

In the present embodiment, the light emitting diode package on which the light emitting diode chip 101 is mounted is described. The light emitting diode package is mounted with the light emitting diode chips 101 to 117 described with reference to FIGS. May be.

Hereinafter, a method for manufacturing a light-emitting diode chip according to an embodiment of the present invention will be described in detail.

FIG. 20 is a cross-sectional view for explaining a method of manufacturing the light-emitting diode chip 101 according to an embodiment of the present invention.

Referring to FIG. 20A, the bare chips 150 are arranged on the support substrate 121. The bare chips 150 may be arranged on the support substrate 121 at equal intervals. As shown in FIG. 1, the bare chip 150 includes a substrate 21, a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29, a gallium nitride based semiconductor stacked structure 30, a first An electrode 41 and a second electrode 42 are provided. Further, the buffer layer 23 may be interposed between the first conductive type semiconductor layer 25 and the substrate 21. That is, the bare chip 150 corresponds to a portion of the light emitting diode chip 101 of FIG. 1 excluding the first additional electrode 43, the second additional electrode 44, and the wavelength conversion layer 50, and in order to avoid duplication, Detailed description of each component will be omitted.

The support substrate 121 supports the bare chips 150 so as to maintain an equal interval. The support substrate 121 may be a substrate of glass, ceramic, sapphire, GaN, Si, or the like, for example.

Referring to FIG. 20B, the first additional electrode 43 and the second additional electrode 44 are formed on the bare chip 150, respectively. The first additional electrode 43 and the second additional electrode 44 may be formed using, for example, chemical vapor deposition, sputtering, plating, solder balls, or the like. The first additional electrode 43 and the second additional electrode 44 may be formed of a material having electrical conductivity such as Au, Ag, Cu, W, Ni, and Al. Thereby, the first additional electrode 43 and the second additional electrode 44 as shown in FIG. 1 may be formed on the bare chip 150.

Referring to FIG. 20C, the wavelength conversion layer 50 that covers the bare chip 150, the first additional electrode 43, and the second additional electrode 44 is formed on the support substrate 121. The wavelength conversion layer 50 may contain a phosphor, and may contain a powder of TiO ₂ , SiO ₂ , Y ₂ O ₃ or the like in order to control the refractive index. The wavelength conversion layer 50 is formed to be sufficiently thick so as to cover the first additional electrode 43 and the second additional electrode 44. The wavelength conversion layer 50 can be formed by various coating methods such as injection molding, transfer molding, compression molding, and printing.

Referring to FIG. 20D, after the wavelength conversion layer 50 is formed, the support substrate 121 is removed. In order to easily remove the support substrate 121, a release film (not shown) may be formed on the support substrate 121. Such a release film may be a film that can be peeled off by heat or light such as ultraviolet rays. Therefore, the support substrate 121 can be easily removed by applying heat to such a release film or irradiating light such as ultraviolet rays.

After removing the support substrate 121, the bare chips 150 are fixed to each other by the wavelength conversion layer 50, and may be attached on a separate support.

Referring to FIG. 20E, the upper portion of the wavelength conversion layer 50 is removed, and the first additional electrode 43 and the second additional electrode 44 are exposed. The upper portion of the wavelength conversion layer 50 may be removed by a physical method using grinding, cutting, or laser, or may be removed using a chemical method such as etching. Furthermore, the upper part of the wavelength conversion layer 50 may be removed so that the upper surfaces of the first additional electrode 43 and the second additional electrode 44 and the wavelength conversion layer 50 are flush with each other.

Referring to FIG. 20F, by separating the wavelength conversion layer 50 that fills the space between the bare chips 150, individual light emitting diode chips 101 as shown in FIG. 1 are completed. The wavelength conversion layer 50 can be separated using a blade or a laser. The individual light emitting diode chip 101 has a wavelength conversion layer 50 that exposes the first additional electrode 43 and the second additional electrode 44 and covers the side surface of the substrate 21 and the upper surface of the semiconductor multilayer structure.

In the present embodiment, it is described that the first additional electrode 43 and the second additional electrode 44 are formed on the support substrate 121. However, the present invention is not limited to this, and the first additional electrode 43 and the second additional electrode 44 are not limited thereto. The additional electrode 44 may be formed on the bare chip before the bare chip is arranged on the support substrate 121.

In addition, before forming the first additional electrode 43 and the second additional electrode 44, a spacer layer (61 in FIG. 5) may be first formed on the bare chip 150 arranged on the support substrate 121. A stress relaxation layer (62 in FIG. 6) may be formed before forming the spacer layer. Next, the spacer layer may be patterned to expose the first electrode 41 and the second electrode 42, and the first additional electrode 43 and the second additional electrode 44 may be formed thereon.

In the present embodiment, it is described that the support substrate 121 is removed before removing the upper portion of the wavelength conversion layer 50. However, the support substrate is removed after removing the upper portion of the wavelength conversion layer 50 or wavelength conversion. Layer 50 may be removed after separation using a blade or laser.

Meanwhile, the bare chip 150 may include the spacer layer 33, the lower distributed Bragg reflector 45, and the metal layer 47 as described with reference to FIG. 2, and the upper portion as described with reference to FIG. A distributed Bragg reflector 37 and a stress relaxation layer 35 may be provided. Further, the bare chip 150 may have a single semiconductor multilayer structure 30 as shown in FIG. 1, but the present invention is not limited to this, and the bare chip 150 is configured as described with reference to FIGS. 16 to 18. A plurality of stacked semiconductor structures 30 may be included, and the insulating layer 81, the second insulating layer 85, the stress relaxation layer 87, and the distributed Bragg reflector 89 may be included. Thus, the light emitting diode chips 116 to 118 shown in FIGS. 16 to 18 can be manufactured.

In the present embodiment, a method for manufacturing a light-emitting diode chip by forming the wavelength conversion layer 50 on the bare chip 150 is described. However, the present invention is for changing not only the wavelength conversion layer 50 but also the optical characteristics. Various transparent coating layers are formed on the bare chip 150 by a method similar to the method of forming the wavelength conversion layer 50. Such a transparent coating layer may contain various materials for improving optical properties, for example, a diffusing material.

Hereinafter, a light emitting diode according to another embodiment of the present invention will be described with reference to FIGS. 21 and 22.

FIG. 21 is a top plan view for explaining a light emitting diode according to an embodiment of the present invention, and FIG. 22 is a cross-sectional view of the light emitting diode shown in FIG.

Referring to FIGS. 21 and 22, the light emitting diode according to the present embodiment includes the submount substrate 1000, the bare chip 200, the bonding member 300, the first electrode 210 and the second electrode 220 formed on the bare chip 200, One additional electrode 410, second additional electrode 420, and wavelength conversion layer 500 may be provided.

Here, the submount substrate 1000 is for mounting and moving the bare chip 200. Unlike the growth substrate for growing the semiconductor stacked structure of the bare chip 200 described later, the submount substrate 1000 has electrodes ( For example, a printed circuit board, a lead frame, or a ceramic substrate may be used, and an upper surface and a lower surface, and these may be connected. It has a side. In the submount substrate 1000, a first slit 1110 and a second slit 1120 may be formed along the periphery of the region where the bare chip 200 is placed.

The first slit 1110 and the second slit 1120 are pre-mounted on the submount substrate before the bare chip 200 is mounted in consideration of the position where the bare chip 200 is mounted on the submount substrate 1000 and the size of the bare chip 200. The distance between the first slit 1110 and the second slit 1120 and the bare chip 200 is kept constant. By forming the slits 1110 and 1120, for example, the bare chip 200 is metal bonded as described later. When mounting on the submount substrate by the method, the movement of the metal melted by the slits 1110 and 1120 is limited, and as a result, the bare chip 200 is disposed in the correct position without being disposed in the wrong position. be able to.

In addition, the first slit 1110 and the second slit 1120 are not limited to this. For example, the first slit 1110 and the second slit 1120 are formed in an opening shape penetrating the submount substrate 1000 or, for example, an etching method according to the embodiment. You may take the shape of the concave pattern formed by.

When the first slit 1110 and the second slit 1120 are manufactured in an opening shape, the wavelength conversion layer 500 penetrates the opening of the first slit 1110 as shown in the region A of FIG. The submount substrate 1000 and the bare chip 200 are fixed by the wavelength conversion layer 500 by being formed not only on the upper surface but also on the inner side surface.

Further, the opening shapes of the first slit 1110 and the second slit 1120 may be the same or different, and may take a form similar to a rounded rectangle as shown in the figure, but is not limited thereto. The shape extended along the side surface of the bare chip 200 may be taken. However, FIG. 21 shows the submount substrate 1000 in a state where the second slit 1120 is formed at a position overlapping the dicing line 1140 (see FIG. 24) and is cut in units of individual chips. The second slit 1120 is different from the first slit 1110 and only its half shape is shown. Therefore, when the position of the dicing line 1140 is adjusted, the second slit 1120 is formed in a shape similar to the first slit 1110. The bonding member 300 serves to attach the bare chip 200 to the upper surface of the submount substrate 1000, and is not limited thereto. For example, when the bare chip 200 has a horizontal structure, the semiconductor layer of the bare chip 200 is The lower surface of the growth substrate (not shown) formed on the upper surface and the upper surface of the submount substrate 1000 are bonded via the bonding member 300. The joining member 300 is manufactured using, for example, silicon paste, metal paste, epoxy paste, or the like. However, the present invention is not limited to a specific type of bonding member, and the bare chip 200 may be mounted on the submount substrate 1000 by metal bonding using a metal such as AuSn.

The bare chip 200 is an LED chip on which a gallium nitride-based semiconductor multilayer structure having a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer is formed. There may be. Specifically, the semiconductor multilayer structure may include, for example, an n-type layer and a p-type layer formed of a GaN film, and an active layer formed of an InGaN film interposed therebetween. Such a semiconductor laminated structure is usually grown on a growth substrate (not shown), and the growth substrate is a sapphire (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a zinc oxide. An oxide (ZnO) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, or the like may be used. However, when the bare chip 200 has a vertical structure, the growth substrate is separated from the semiconductor multilayer structure through, for example, a laser lift-off process (LLO).

Although the present invention is not limited to a specific bare chip structure such as a horizontal structure or a vertical structure, the following description will be described centering on the horizontal bare chip, and the configuration of the bare chip 200 is a normal gallium nitride system. Since the structure is the same as that of the light emitting diode, detailed description thereof is omitted.

The first electrode 210 and the second electrode 220 are electrically connected to a first conductive type semiconductor layer and a second conductive type semiconductor layer (not shown) of the bare chip 200, respectively, for example, Ti, Cu, Ni, Al, Au, or Cr may be included, and may be formed of two or more of these substances. Further, the first electrode 210 and the second electrode 220 may be formed with a thickness of about 10 to 200 μm. However, in FIG. 21, two first electrodes 210 and two second electrodes 220 are illustrated, but the numbers and positions of the first electrodes 210 and the second electrodes 220 are illustrated. It is not limited to the specific embodiments described. That is, when the bare chip 200 has a horizontal structure according to the type of the bare chip 200, all of the first electrode 210 and the second electrode 220 are formed on the top surface of the bare chip 200, and when the vertical structure is taken. Any one of the first electrode 210 and the second electrode 220 may be omitted. Further, when all of the first electrode 210 and the second electrode 220 are formed on the top surface of the bare chip 200, the first electrode 210 and the second electrode 220 are formed on the top surface of the bare chip 200, unlike the illustration of FIG. You may form one by one facing each other. That is, by increasing the area of the bare chip 200 itself, two first electrodes 210 and two second electrodes 220 may be formed on the upper surface of the bare chip 200 as shown in FIG. In this case, the first electrode 210 and the second electrode 220 are formed one by one, and the positions of the first electrode 210 and the second electrode 220 differ depending on the horizontal type or vertical type structure. However, the following description will be described focusing on the structure of FIG.

The first additional electrode 410 and the second additional electrode 420 have a thickness of about 100 μm or more on the first electrode 210 and the second electrode 220, respectively, and are conductive such as Au, Cu, Ag, Al, etc. It can be formed using a metal material. Also, it may be formed by a chemical vapor deposition method, e-Beam, sputtering, plating, or a manufacturing method using a solder ball, etc. According to an embodiment, it is manufactured by applying a photosensitive material, and then exposing and developing. Therefore, the present invention is not limited to a specific electrode forming method.

Further, the first additional electrode 410 and the second additional electrode 420 may have a width narrower than the width of the first electrode 210 and the second electrode 220, respectively. In other words, the first additional electrode 410 and the second additional electrode 420 are disposed on the first electrode 210 and the second electrode 220, respectively. In addition, the first additional electrode 410 and the second additional electrode 420 may have a shape in which the width decreases as the distance from the contact surface with the first electrode 210 and the second electrode 220 increases. With such a shape, the first additional electrode 410 and the second additional electrode 420 are stably attached and maintained on the first electrode 210 and the second electrode 220, respectively, which is advantageous for subsequent processes such as wire bonding. It is. Further, the height ratio with respect to the bottom surface is set within a predetermined range so that the first additional electrode 410 and the second additional electrode 420 are stably maintained on the first electrode 210 and the second electrode 220. Also good.

The wavelength conversion layer 500 is formed of a phosphor in epoxy or silicon, or is formed only of the phosphor, and the wavelength is converted using light generated from an active layer (not shown) of the bare chip 200 as an excitation source. Later, it plays the role of emitting.

Here, the kind of the phosphor is not particularly limited, and all known wavelength converting substances can be used, and are not limited thereto. For example, (Ba, Sr, Ca) ₂ SiO ₄ : Eu ²⁺ , YAG ((Y, Gd) ₃ (Al, Ga) ₅ O ₁₂ : Ce ³⁺ ) -based phosphor, TAG ((Tb, Gd) ₃ (Al, Ga) ₅ O ₁₂ : Ce ³⁺ ) Phosphor, (Ba, Sr, Ca) ₃ SiO ₅ : Eu ²⁺ , (Ba, Sr, Ca) MgSi ₂ O ₆ : Eu ²⁺ , Mn ²⁺ , (Ba, Sr, Ca) ₃ MgSi ₂ O ₈ : Eu Examples thereof include one or more selected from the group consisting of ²⁺ , Mn ²⁺ and (Ba, Sr, Ca) MgSiO ₄ : Eu ²⁺ , Mn ²⁺ .

In addition, according to an embodiment of the present invention, the wavelength conversion layer 500 can be formed with a uniform thickness not only on the top of the bare chip 200 (the region indicated by the dotted line in FIG. 21) but also on the side surface. At this time, as described later, the wavelength conversion layer 500 having a flat upper surface is formed in a region excluding the upper surface (whole or a part) region of the first additional electrode 410 and the second additional electrode 420 using a mold. By forming and exposing the first additional electrode 410 and the second additional electrode 420 to the outside of the light emitting diode chip through the wavelength conversion layer 500, wire bonding can be easily performed at the time of packaging work, The wavelength conversion layer 500 can be formed at the chip level, and an additional step of exposing the electrode for wire bonding is not required.

Furthermore, the wavelength conversion layer 500 may have a refractive index in the range of 1.4 to 2.0, for example, and TiO ₂ , SiO ₂ , Y ₂ O _3, etc. in order to adjust the refractive index. May be mixed in the wavelength conversion layer 50.

On the other hand, as shown in FIG. 22, the upper surface of the first additional electrode 410 may be positioned at the same height as the upper surface of the second additional electrode 420. Therefore, when the bare chip 200 is a horizontal light emitting diode, a part of the second conductive type semiconductor layer and the active layer are removed, and the first conductive type semiconductor layer is exposed, The first additional electrode 410 that is electrically connected may be formed longer than the second additional electrode 420 that is electrically connected to the second conductive semiconductor layer.

According to the present embodiment, since the wavelength conversion layer 500 covers not only the upper surface of the bare chip 200 but also the side surface, not only the light emitted from the upper surface of the semiconductor multilayer structure but also the light emitted from the side surface, A light emitting diode capable of wavelength conversion is provided.

FIG. 23 is a diagram showing a submount substrate on which a plurality of light emitting diodes are formed according to an embodiment of the present invention, and FIG. 24 is an enlarged view of a region indicated by a circle in FIG.

According to an embodiment of the present invention, after mounting a plurality of bare chips 200 in a matrix on one submount substrate 1000, the wavelength conversion layer 500 is formed on the top surfaces of the plurality of bare chips 200 at once using a mold. And can be diced in units of individual chips. At this time, if the second slit 1120 is formed at a position overlapping the dicing line 1140, such a dicing process can be performed more easily.

Meanwhile, the submount substrate 1000 according to an embodiment of the present invention may further include a chip separation slit 1130 in addition to the first slit 1110 and the second slit 1120 described above. That is, when the submount substrate 1000 is cut in the horizontal direction (X direction) along the dicing line 1140, the chip separation slits 1130 formed in the vertical direction (Y direction) at regular intervals in the submount substrate 1000 Light emitting diodes are separated into individual chips.

Therefore, according to the present invention, after mounting a plurality of bare chips on one substrate, a wavelength conversion layer is formed on all the bare chips through the same process, and this is cut into individual chips. Since a plurality of light emitting devices can be manufactured at the same time, the manufacturing time can be shortened and the manufacturing cost can be reduced by mass production.

Hereinafter, a method for manufacturing a light emitting diode and a package including the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 25 and 26.

FIG. 25 is a flowchart for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, and FIG. 26 is a diagram illustrating a manufacturing process of the light emitting diode according to the embodiment of the present invention step by step. However, each step of FIG. 25 may be performed simultaneously or separately, and in some cases, the order may be changed, and specific steps may be omitted. Therefore, the present invention is not limited to the illustrated order.

First, as shown in FIG. 26A, a submount substrate 1000 is prepared (step S1). As described above, a plurality of first slits 1110 and second slits 1120 may be formed on the submount substrate 1000 (see FIG. 24) along the periphery of the region where the bare chip 200 is placed. Even if the chip separation slit 1130 is formed in advance and the submount substrate 1000 is cut only in the X direction in a dicing process, the light emitting diodes can be separated in units of individual chips.

Thereafter, as shown in FIG. 26B, a plurality of bare chips 200 can be mounted in a matrix on the prepared submount substrate 1000 (step S2). Here, the bare chip 200 may be attached to the upper surface of the submount substrate 1000 using the bonding member 300, for example, using a metal bonding method using AuSn or the like. Further, when the bare chip 200 is mounted, the bare chip 200 is not arranged at an incorrect position by the first slit 1110 and the second slit 1120, and can be arranged at a desired position. At this time, on the upper surface of the bare chip 200, a first electrode 210 and a second electrode electrically connected to a first conductive semiconductor layer (not shown) and a second conductive semiconductor layer (not shown), respectively. The electrode 220 may be formed.

Thereafter, as shown in FIG. 26C, a first additional electrode 410 and a second additional electrode 420 are formed on the first electrode 210 and the second electrode 220, respectively (step S3). The first additional electrode 410 and the second additional electrode 420 can be formed using, for example, a conductive metal material such as Au, Cu, Ag, and Al. Chemical vapor deposition, e-Beam, sputtering , Plating, or a manufacturing method using solder balls or the like. Depending on the embodiment, the photosensitive material may be applied, and then exposed and developed.

Thereafter, the wavelength conversion layer 500 is formed on the upper surface and side surfaces of the bare chip 200 (step S4). According to one embodiment of the present invention, as shown in FIG. 26D, the submount substrate 1000 on which the bare chip 200 is mounted is clamped by the mold 650, and the first additional electrode 410 and the second additional electrode are clamped. While pressing the upper surface of 420, the surface of the mold 650 and the upper surfaces of the additional electrodes 410 and 420 are in close contact with each other so that no space is formed, and the phosphor and the resin mixture are injected into the inner space 600 of the mold. After that, the wavelength conversion layer 500 can be formed by curing the resin ((e) of FIG. 26). At this time, even when the shapes of the additional electrodes 410 and 420 are deformed by the force with which the mold 650 pressurizes the additional electrodes 410 and 420, and the heights thereof are slightly different, the height of the additional electrodes 410 and 420 is increased depending on the mold. Therefore, it is possible to prevent a gap from being formed between the mold and the additional electrodes 410 and 420.

Also, depending on the embodiment, the mold 650 is lower than the total height of the bare chip 200 having the additional electrodes 410 and 430 so that the mold 650 presses the additional electrode more effectively. May be adjusted. In FIG. 26E, only a single bare chip 200 is shown as a reference, but in the actual formation of the wavelength conversion layer 500, a plurality of bare chips arranged in a matrix in FIGS. It is possible to form the wavelength conversion layer 500 on the upper surfaces of the plurality of bare chips 200 at a time using a single mold for the whole 200.

Thereafter, the submount substrate 1000 on which the wavelength conversion layer 500 is formed is cut along the dicing line 1140, and the light emitting diodes are separated in units of individual chips (step S5). In this case, as described above, since the opening of the chip separating slit 1130 extends in the Y-axis direction in the region between the chips, the cutting operation may be performed only in one direction of the X-axis. The dicing process can be simplified and the process time is shortened.

Then, as shown in FIG. 27, after mounting the individual light emitting diodes on the package substrate 1500, the bonding wires 800 are electrically connected to the first additional electrode 410 and the second additional electrode 420, respectively. The lens 700 that seals the light emitting diode can be formed by applying a power source to the light emitting diode to protect the light emitting diode from the outside (step S6).

That is, FIG. 27 is a cross-sectional view for explaining a light emitting diode package on which a light emitting diode according to an embodiment of the present invention is mounted. Referring to FIG. 27, the light emitting diode package includes a package substrate 1500 to which a submount substrate 1000 on which the bare chip 200 is mounted is attached, a first additional electrode 410 and a second additional electrode 420 formed on the bare chip 200. A bonding wire 800 that is electrically connected and a lens 700 that seals the bare chip 200 may be provided.

Unlike the submount substrate 1000, the package substrate 1500 is a substrate provided for supplying power to the bare chip 200, and is not limited thereto, but includes, for example, a printed circuit board, a lead frame, and a ceramic. It may be a substrate or the like, and may have a power supply lead terminal (not shown). Therefore, the first additional electrode 410 and the second additional electrode 420 of the bare chip 200 are electrically connected to the lead terminals via the bonding wires 800, respectively.

On the other hand, the lens 700 is formed so as to integrally seal the submount substrate 1000 on which the wavelength conversion layer 500 is formed, that is, is formed so as to cover the entire bare chip 200, and the directivity angle of light emitted from the bare chip 200 is set. Can be adjusted to emit light in the desired direction. According to the present embodiment, since the wavelength conversion layer 500 is formed on the bare chip 200, the lens 700 does not need to include a phosphor, but in some cases, the fluorescence different from the phosphor included in the wavelength conversion layer 500 may be used. May include body.

Therefore, according to an embodiment of the present invention, by packaging the light emitting diode using the bare chip 200 mounted on the submount substrate 1000, the package design can be made more free and the packaging work is simplified. , Work efficiency is improved.

Hereinafter, a light emitting diode according to another embodiment of the present invention will be described with reference to FIG.

Unlike the embodiment described above, for example, the light emitting diode of FIG. 22 is a structure in which the wavelength conversion layer 500 is in contact with the semiconductor multilayer structure of the bare chip 200, but the light emitting diode shown in FIG. The layer 500 is formed so as to be separated from the semiconductor multilayer structure, that is, the transparent resin 550 is interposed between the wavelength conversion layer 500 and the semiconductor multilayer structure.

Thereby, when the wavelength conversion layer 500 is separated from the semiconductor multilayer structure, it is possible to prevent the resin or phosphor of the wavelength conversion layer 500 from being deteriorated by the light generated in the active layer (not shown). In this case, the transparent resin 550 may be interposed between the inner surface of the first slit 1110 formed in the submount substrate 1000 and the wavelength conversion layer 500 (region B in FIG. 28).

Here, the transparent resin 550 is more advantageous as the thermal conductivity is lower in order to reduce the heat transmitted to the phosphor, and may be, for example, less than 3 W / mK. The transparent in order to adjust the refractive index of the resin _{550, TiO 2, SiO 2,} Y a 2 _{O 3} or the like of the powder may be mixed into the transparent resin.

Alternatively, although not shown, a high-hardness transparent resin (not shown) having a hardness higher than that of the transparent resin 550 may be further formed on the wavelength conversion layer 500 so as to cover the wavelength conversion layer 500. Good. In this case, the high-hardness transparent resin can protect the phosphor from external moisture, and in order to prevent moisture absorption, the high-hardness transparent resin preferably has a durometer shore hardness of 60 A or more, for example. Further, in order to adjust the refractive index of the high-hardness transparent resin, powders such as TiO ₂ , SiO ₂ , Y ₂ O ₃ may be mixed into the resin.

As described above, the light emitting diode chip according to the present invention and the manufacturing method thereof, and the package including the light emitting diode chip and the manufacturing method thereof are not limited to the above-described embodiments. Application is possible.

The present invention can be modified and changed without departing from the scope of the invention, and the scope of the present invention is defined by the following claims rather than the above detailed description. All changes or modified forms derived from the meaning and range of the range and the equivalent concept thereof should be construed as being included in the scope of the present invention.

21 Substrate 23 Buffer layer 25 First conductivity type semiconductor layer 27 Active layer 29 Second conductivity type semiconductor layer 30 Semiconductor stacked structure 41 First electrode 42 Second electrode 43 First additional electrode 44 Second addition Electrode 50 Wavelength conversion layer 101 Light emitting diode chip

Claims (20)

A substrate,
A gallium nitride-based compound semiconductor multilayer structure positioned on the substrate, the semiconductor multilayer structure having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer;
An electrode electrically connected to the semiconductor multilayer structure;
An additional electrode formed on the electrode;
A wavelength conversion layer covering a part of the semiconductor multilayer structure,
The light emitting diode chip, wherein the electrode penetrates the wavelength conversion layer. 2. The light emitting device according to claim 1, wherein the electrode includes a first electrode disposed on the semiconductor multilayer structure and a first additional electrode disposed on the first electrode. Diode chip. The light-emitting diode chip according to claim 1, further comprising a spacer layer interposed between the wavelength conversion layer and the semiconductor multilayer structure. The light emitting diode chip according to claim 3, wherein the spacer layer includes an insulating layer. The light emitting diode chip according to claim 3, wherein the spacer layer includes a distributed Bragg reflector. 6. The light emitting diode chip according to claim 5, wherein the spacer layer further includes a stress relaxation layer interposed between the distributed Bragg reflector and the semiconductor multilayer structure. The light emitting diode chip according to claim 6, wherein the stress relaxation layer is formed of spin-on glass or a porous silicon oxide film. The light emitting diode chip according to claim 2, wherein the first additional electrode has a narrower width than the first electrode. The light emitting diode chip according to claim 8, wherein the first additional electrode has a width that decreases as the distance from the first electrode increases. A second electrode disposed on the semiconductor multilayer structure and electrically connected to the semiconductor multilayer structure; and a second additional electrode disposed on the second electrode. The light-emitting diode chip according to claim 2. The light emitting diode chip according to claim 2, wherein an upper surface of the first additional electrode coincides with an upper surface of the wavelength conversion layer. The light emitting diode chip according to claim 11, wherein an upper surface of the additional electrode and an upper surface of the wavelength conversion layer are substantially flat. The light emitting diode according to claim 11, wherein an upper surface of the first additional electrode is opposite to the first electrode, and an upper surface of the first additional electrode is not covered by the wavelength conversion layer. Chip. The light emitting diode chip according to claim 1, wherein the electrode is electrically connected to the first conductive semiconductor layer. Lead terminal,
In a light emitting diode package comprising a light emitting diode chip, and a bonding wire connecting the lead terminal and the light emitting diode chip,
The light emitting diode chip is:
A substrate,
A gallium nitride-based compound semiconductor multilayer structure located on an upper surface of the substrate, the semiconductor multilayer structure having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer;
An electrode electrically connected to the semiconductor multilayer structure;
An additional electrode formed on the electrode;
A wavelength conversion layer covering a part of the semiconductor multilayer structure,
The electrode penetrates the wavelength conversion layer,
The light emitting diode package, wherein the bonding wire connects the additional electrode and the lead terminal. The light emitting device according to claim 15, wherein the electrode includes a first electrode disposed on the semiconductor multilayer structure and a first additional electrode disposed on the first electrode. Diode package. The light emitting diode package according to claim 15, further comprising a spacer layer interposed between the wavelength conversion layer and the semiconductor multilayer structure. The light emitting diode package according to claim 16, wherein the first additional electrode has a narrower width than the first electrode. 19. The light emitting diode package according to claim 18, wherein the first additional electrode has a width that decreases as the distance from the first electrode increases. The light emitting diode package according to claim 15, wherein the electrode is electrically connected to the first conductive semiconductor layer.