JP2011138845A - Wiring board - Google Patents

Wiring board Download PDF

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JP2011138845A
JP2011138845A JP2009296544A JP2009296544A JP2011138845A JP 2011138845 A JP2011138845 A JP 2011138845A JP 2009296544 A JP2009296544 A JP 2009296544A JP 2009296544 A JP2009296544 A JP 2009296544A JP 2011138845 A JP2011138845 A JP 2011138845A
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pair
conductor
external connection
connection pads
conductors
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JP5311669B2 (en
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Kenichiro Haruta
健一郎 春田
Hisayoshi Wada
久義 和田
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board where a pair of belt-like wiring conductors can be shielded successfully from outside by forming through conductors for shielding at predetermined intervals along both sides of the pair of belt-like wiring conductors. <P>SOLUTION: This invention relates to the wiring board, wherein first to third grounding or power supply conductor layers 94, 95 and 96 have projection portions 94b, 95b and 96b protruding to inner sides of center portions in long-hole shapes of first to third opening portions 94a, 95b and 96a or an island portion 95c, and the through conductors 54c and 55c connecting the first to third grounding or power-supply conductor layers 94, 95 and 96 are connected to both sides of the pair 72 of belt-like wiring conductors at the protrusion portions 94b, 95b and 96b and/or island portion 95c. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体集積回路素子等の半導体素子を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a semiconductor element such as a semiconductor integrated circuit element.

半導体素子を搭載するための小型の配線基板は、複数の絶縁層が積層されて成る絶縁基板の内部および表面に配線導体用の複数の導体層が配置されているとともに絶縁層を貫通する貫通導体により上下の配線導体同士が接続された多層配線構造をしている。絶縁基板の上面中央部には半導体素子の電極が半田バンプ等を介して電気的に接続される複数の半導体素子接続パッドが形成されており、絶縁基板の下面には外部電気回路基板の配線導体に半田ボール等を介して電気的に接続される外部接続パッドが形成されている。これらの半導体素子接続パッドと外部接続パッドとは、所定のもの同士が絶縁基板の表面および内部に配置された配線導体および貫通導体により互いに電気的に接続されている。   A small-sized wiring board for mounting a semiconductor element has a plurality of conductor layers for wiring conductors disposed inside and on the surface of an insulating substrate formed by laminating a plurality of insulating layers, and a through conductor that penetrates the insulating layer Thus, a multilayer wiring structure in which the upper and lower wiring conductors are connected to each other is formed. A plurality of semiconductor element connection pads are formed in the central portion of the upper surface of the insulating substrate, to which the electrodes of the semiconductor element are electrically connected via solder bumps, etc. The wiring conductor of the external electric circuit substrate is formed on the lower surface of the insulating substrate. External connection pads are formed which are electrically connected to each other via solder balls or the like. These semiconductor element connection pads and external connection pads are electrically connected to each other by wiring conductors and through conductors disposed on the surface and inside of the insulating substrate.

ところで近時、半導体素子を搭載するための配線基板においては、高周波伝送における電気的ロスの少ない形態が要求されている。そこで、信号用の伝送線路として互いに差動線路として機能するペア伝送路を備えた配線基板が使用されている。ペア伝送路は、絶縁基板の表面または内部に互いに所定間隔で平行に延びる2本の帯状配線導体をペアとして設けるとともに、このペアをなす2本の帯状配線導体の上下や左右に接地または電源用導体を所定の間隔で設けてインピーダンス整合させることにより形成されている。また、ペアをなす帯状配線導体と上下の導体層との接続に使用される貫通導体も所定の間隔でペアをなして隣接するようして設けられている。   Recently, a wiring board for mounting a semiconductor element is required to have a form with less electrical loss in high-frequency transmission. Therefore, a wiring board having a pair transmission line that functions as a differential line is used as a transmission line for signals. The pair transmission line is provided with two strip-shaped wiring conductors extending in parallel with each other at a predetermined interval on the surface or inside of the insulating substrate as a pair, and for grounding or power supply above, below, left and right of the two strip-shaped wiring conductors forming the pair The conductors are formed by providing impedance matching at predetermined intervals. Further, the through conductors used for connecting the pair of strip-shaped wiring conductors and the upper and lower conductor layers are also provided so as to be adjacent to each other in pairs at a predetermined interval.

上述のようなペア伝送路を有する配線基板における従来の例を図4に示す。従来の配線基板200は、図4に示すように、コア用の絶縁層113の上面にビルドアップ用の絶縁層112および111を積層するとともに絶縁層113の下面にビルドアップ用の絶縁層114および115を積層して成る絶縁基板110の上下面および絶縁層111,112,113,114,115の間に配線導体用の導体層121,122,123,124,125,126が配置されて成る。絶縁基板110の上面中央部には半導体素子Sの電極端子に半田バンプB1を介して電気的に接続される半導体素子接続パッド130が形成されており、絶縁基板110の下面には外部電気回路基板の配線導体に半田ボールを介して電気的に接続される外部接続パッド140が形成されている。これらの半導体素子接続パッド130と外部接続パッド140とは導体層121〜126内に形成された配線導体および各絶縁層111,112,113,114,115をそれぞれ貫通する貫通導体151,152,153,154,155を介して互いに電気的に接続されている。さらに、最上層の絶縁層111および導体層121の表面には半導体素子接続パッド130の中央部を露出させる開口部を有するソルダーレジスト層161が被着されており、最下層の絶縁層115および導体層126の表面には外部接続パッド140の中央部を露出させる開口部を有するソルダーレジスト層162が被着されている。   FIG. 4 shows a conventional example of a wiring board having a pair transmission line as described above. As shown in FIG. 4, the conventional wiring board 200 includes build-up insulating layers 112 and 111 laminated on the upper surface of the core insulating layer 113 and build-up insulating layers 114 and 111 on the lower surface of the insulating layer 113. Conductive layers 121, 122, 123, 124, 125, 126 for wiring conductors are arranged between the upper and lower surfaces of the insulating substrate 110 formed by laminating 115 and the insulating layers 111, 112, 113, 114, 115. A semiconductor element connection pad 130 that is electrically connected to an electrode terminal of the semiconductor element S via a solder bump B1 is formed at the center of the upper surface of the insulating substrate 110. An external electric circuit board is formed on the lower surface of the insulating substrate 110. External connection pads 140 that are electrically connected to the wiring conductors via solder balls are formed. These semiconductor element connection pads 130 and external connection pads 140 are wiring conductors formed in the conductor layers 121 to 126 and through conductors 151, 152, 153 penetrating through the insulating layers 111, 112, 113, 114, 115, respectively. , 154, 155 are electrically connected to each other. Furthermore, a solder resist layer 161 having an opening exposing the central portion of the semiconductor element connection pad 130 is deposited on the surfaces of the uppermost insulating layer 111 and the conductor layer 121, and the lowermost insulating layer 115 and the conductor layer are exposed. A solder resist layer 162 having an opening exposing the central portion of the external connection pad 140 is deposited on the surface of the layer 126.

図5は、上述した配線基板200における導体層121,122,123,124,125,126の一部および貫通導体151,152,153,154,155の一部のみを抜き出して示した斜視図である。半導体素子接続パッド130のうち、一部のものは互いに隣接する2個がペア131,132を形成している。一方の半導体素子接続パッドのペア131には導体層121により形成された帯状配線導体のペア171が接続されている。帯状配線導体のペア171は、その端部を除いて互いに所定間隔で平行に延びており、その他端部が貫通導体151a,152a,153a,154a,155aおよびランドを介して外部接続パッドのペア141に電気的に接続されている。他方、半導体素子接続パッドのペア132には導体層123により形成された帯状配線導体のペア172が貫通導体151b,152b,153b,154bおよびランドを介して接続されている。帯状配線導体のペア172は、帯状配線導体のペア171と同様にその端部を除いて互いに所定間隔で平行に延びており、その他端部が貫通導体155bおよびランドを介して外部接続パッドのペア142に電気的に接続されている。   FIG. 5 is a perspective view in which only a part of the conductor layers 121, 122, 123, 124, 125, 126 and a part of the through conductors 151, 152, 153, 154, 155 are extracted from the wiring board 200 described above. is there. Some of the semiconductor element connection pads 130 are adjacent to each other to form a pair 131 and 132. One pair of semiconductor element connection pads 131 is connected to a pair of strip-like wiring conductors 171 formed by the conductor layer 121. The strip-like wiring conductor pair 171 extends in parallel with each other at a predetermined interval except for its end portion, and the other end portion is a pair 141 of external connection pads via the through conductors 151a, 152a, 153a, 154a, 155a and the land. Is electrically connected. On the other hand, a pair of semiconductor element connection pads 132 is connected to a pair of strip-like wiring conductors 172 formed of a conductor layer 123 through through conductors 151b, 152b, 153b, 154b and lands. The pair of strip-shaped wiring conductors 172 extend in parallel with each other at a predetermined interval except for the ends thereof, like the pair of strip-shaped wiring conductors 171, and the other end is a pair of external connection pads via the through conductor 155 b and the land. 142 is electrically connected.

ここで、図5に示した半導体素子接続パッドのペア131,132、帯状配線導体のペア171,172、外部接続パッドのペア141,142、ランドの一部を各導体層121,122,123,124,125,126別に図6(a)〜(f)にそれぞれ平面図で示す。図6(a)に示すように、導体層121においては、半導体素子接続パッドのペア131,132と帯状配線導体のペア171とランド181aと接地または電源用導体層191が形成されている。半導体素子接続パッドのペア131,132および帯状配線導体のペア171ならびにランド181aと接地または導体層191との間には所定間隔が形成されている。   Here, the semiconductor element connection pad pair 131, 132, the strip-like wiring conductor pair 171, 172, the external connection pad pair 141, 142, and a part of the land shown in FIG. FIG. 6A to FIG. 6F are shown in plan views for 124, 125, and 126, respectively. As shown in FIG. 6A, in the conductor layer 121, a pair of semiconductor element connection pads 131, 132, a pair of strip-like wiring conductors 171, a land 181a, and a ground or power source conductor layer 191 are formed. A predetermined distance is formed between the pair of semiconductor element connection pads 131 and 132, the pair of strip-like wiring conductors 171 and the land 181a and the ground or conductor layer 191.

図6(b)に示すように、導体層122においては、ランド182aおよび182bと接地または電源用導体層192とが形成されている。ランド182aは、図示しない貫通導体151aを介して上層のランド181aに接続されている。ランド182bは、図示しない貫通導体151bを介して上層の半導体素子接続パッドのペア132に接続されている。   As shown in FIG. 6B, in the conductor layer 122, lands 182a and 182b and a ground or power source conductor layer 192 are formed. The land 182a is connected to the upper land 181a via a through conductor 151a (not shown). The land 182b is connected to a pair 132 of upper-layer semiconductor element connection pads via a through conductor 151b (not shown).

図6(c)に示すように、導体層123においては、ランド183aおよびランド183bと接地または電源用導体層193とが形成されている。ランド183aは図示しない貫通導体152aを介して上層のランド182aに接続されている。ランド183bは、図示しない貫通導体152bを介して上層のランド182bに接続されている。   As shown in FIG. 6C, in the conductor layer 123, lands 183a and 183b and a ground or power source conductor layer 193 are formed. The land 183a is connected to the upper land 182a through a through conductor 152a (not shown). The land 183b is connected to the upper land 182b via a through conductor 152b (not shown).

図6(d)に示すように、導体層124においては、ランド184aおよびランド184bと接地または電源用導体層194とが形成されている。ランド184aは図示しない貫通導体153aを介して上層のランド183aに接続されている。ランド184bは、図示しない貫通導体153bを介して上層のランド183bに接続されている。   As shown in FIG. 6D, in the conductor layer 124, lands 184a and 184b and a ground or power source conductor layer 194 are formed. The land 184a is connected to the upper land 183a via a through conductor 153a (not shown). The land 184b is connected to the upper land 183b via a through conductor 153b (not shown).

図6(e)に示すように、導体層125においては、帯状配線導体のペア172と、ランド185a,185b,185cと接地または電源用導体層195とが形成されている。ランド185aは図示しない貫通導体154aを介して上層のランド184aに接続されている。ランド185bは、図示しない貫通導体154bを介して上層のランド184bに接続されている。   As shown in FIG. 6E, in the conductor layer 125, a pair of strip-shaped wiring conductors 172, lands 185a, 185b, and 185c and a ground or power source conductor layer 195 are formed. The land 185a is connected to the upper land 184a via a through conductor 154a (not shown). The land 185b is connected to the upper land 184b through a through conductor 154b (not shown).

図6(f)に示すように、導体層126においては、外部接続パッドのペア141,142とランド186a,186bと接地または電源用導体層196とが形成されている。ランド186aは図示しない貫通導体155aを介して上層のランド185aに接続されている。ランド186bは、図示しない貫通導体155bを介して上層のランド185cに接続されている。   As shown in FIG. 6 (f), in the conductor layer 126, a pair of external connection pads 141, 142, lands 186 a, 186 b, and a ground or power source conductor layer 196 are formed. The land 186a is connected to the upper land 185a via a through conductor 155a (not shown). The land 186b is connected to an upper land 185c through a through conductor 155b (not shown).

ところで、このような高速信号が伝送されるペア伝送路を有する配線基板200においては、ペア伝送路の帯状配線導体のペア171,172に接続される外部接続パッドのペア141,142に対向する位置の接地または電源用導体層191,192,193,194,195,196に、長円形の開口部191a,192a,193a,194a,195a,196aを設けている。このような開口部191a,192a,193a,194a,195a,196aを設けることにより、接地または電源用導体層191,192,193,194,195,196とペア伝送路帯状配線導体のペア171,172に接続される外部接続パッドのペア141,142との間の静電容量が低減され、それにより外部接続用パッドのペア141,142における信号の反射が抑制されて高周波信号を効率よく外部に伝送することが可能となる。   By the way, in the wiring board 200 having a pair transmission path through which such a high-speed signal is transmitted, the positions facing the external connection pad pairs 141 and 142 connected to the strip-like wiring conductor pairs 171 and 172 of the pair transmission path. Are provided with oval openings 191 a, 192 a, 193 a, 194 a, 195 a, 196 a in the grounding or power conductor layers 191, 192, 193, 194, 195, 196. By providing such openings 191a, 192a, 193a, 194a, 195a, 196a, a pair 171, 172 of the ground or power conductor layers 191, 192, 193, 194, 195, 196 and the pair transmission line strip-shaped wiring conductors The capacitance between the external connection pad pair 141 and 142 connected to the external connection pad is reduced, thereby suppressing the reflection of the signal in the external connection pad pair 141 and 142 and efficiently transmitting a high-frequency signal to the outside. It becomes possible to do.

しかしながら、このような配線基板200においては、図6(e)に示すように、帯状配線導体のペア172が互いに隣接して設けられた開口部195aの間を抜けるようにして延在する場合がある。このように、帯状配線導体のペア172が互いに隣接して設けられた開口部195aの間を抜けるようにして延在する場合、それらの開口部195aと帯状配線導体のペア172との間に十分な幅の接地または電源用導体層195を設けることが困難となり、場合によっては開口部195aと帯状配線導体のペア172との間に接地または電源用導体層195を設けることができなくなる。したがって、帯状配線導体のペア172の両側に沿ってシールド用の接地または電源用の複数の貫通導体154c,155cを所定間隔で並べて設けることにより帯状配線導体のペア172を外部からシールドしようとすると、開口部195aの間を抜ける部分では、帯状配線導体のペア172の両側に接地または電源用の貫通導体154c,155cを設けることができずに、シールド用の貫通導体154c,155cの間隔が広いものとなってしまい、その結果、帯状配線導体のペア172を良好にシールドすることが困難となってしまう。   However, in such a wiring board 200, as shown in FIG. 6 (e), a pair of strip-shaped wiring conductors 172 may extend so as to pass through between openings 195a provided adjacent to each other. is there. Thus, when the strip-shaped wiring conductor pair 172 extends so as to pass through the openings 195 a provided adjacent to each other, the gap between the openings 195 a and the strip-shaped wiring conductor pair 172 is sufficient. It is difficult to provide a ground or power source conductor layer 195 having a wide width, and in some cases, it becomes impossible to provide the ground or power source conductor layer 195 between the opening 195a and the strip-like wiring conductor pair 172. Therefore, when a plurality of through conductors 154c and 155c for grounding or power supply are arranged at predetermined intervals along both sides of the pair 172 of the strip-shaped wiring conductors, an attempt is made to shield the pair 172 of the strip-shaped wiring conductors from the outside. In the part passing through between the openings 195a, the grounding or power supply through conductors 154c and 155c cannot be provided on both sides of the pair of strip-like wiring conductors 172, and the shield through conductors 154c and 155c have a wide interval. As a result, it becomes difficult to shield the strip-shaped wiring conductor pair 172 well.

特開2003−249760号公報JP 2003-249760 A 特開2003−273525号公報JP 2003-273525 A

本発明の課題は、互いに隣接して対向するように並んだ2個ずつの外部接続パッドのペアに対応して、上面視で前記外部接続パッドのペアをそれぞれ囲繞する長孔形状の開口部が互いに隣接して形成された接地または電源用導体層を有する配線基板において、前記隣接する開口部の間を帯状配線導体のペアが抜けるようにして延在する場合に、帯状配線導体のペアが開口部の間を抜ける部分においても、帯状配線導体のペアの両側にシールド用の接地または電源用の貫通導体を設けることができ、それにより帯状配線導体のペアの両側に沿ってシールド用の貫通導体を所定の間隔で形成して帯状配線導体のペアを外部から良好にシールドすることが可能な配線基板を提供することにある。   An object of the present invention is to correspond to two pairs of external connection pads arranged adjacent to each other so as to face each other, and has an elongated hole-shaped opening part surrounding each pair of external connection pads in a top view. In a wiring board having grounding or power supply conductor layers formed adjacent to each other, when the band-shaped wiring conductor pair extends between the adjacent openings, the pair of band-shaped wiring conductors is opened. Even in the portion that passes between the two portions, shield grounding or power supply penetrating conductors can be provided on both sides of the pair of strip wiring conductors, whereby the shield penetrating conductors are formed along both sides of the strip wiring conductor pairs. It is an object of the present invention to provide a wiring board capable of forming a pair of strip-shaped wiring conductors at a predetermined interval and satisfactorily shielding a pair of strip-shaped wiring conductors from outside.

本発明の配線基板は、少なくとも第1の絶縁層と該第1の絶縁層上に積層された第2の絶縁層とを含む複数の絶縁層が積層されて成る絶縁基板と、前記絶縁基板の下面に被着されており、互いに隣接して対向するように並んだ2個ずつがそれぞれペアをなすように配置された複数の外部接続パッドと、前記第1の絶縁層の下面に被着されており、前記外部接続パッドのペアに対応する位置に上面視で前記外部接続パッドのペアをそれぞれ囲繞する長孔形状の第1の開口部が形成された第1の接地または電源用導体層と、前記第1の絶縁層と第2の絶縁層との間に被着されており、前記外部接続パッドの前記ペアに対応する位置に上面視で前記外部接続パッドのペアをそれぞれ囲繞する長孔形状の第2の開口部が形成された第2の接地または電源用導体層と、前記第2の絶縁層の上面に被着されており、前記外部接続パッドのペアに対応する位置に上面視で該外部接続パッドのペアをそれぞれ囲繞する長孔形状の第3の開口部が形成された第3の接地または電源用導体層と、前記第1の絶縁層と第2の絶縁層との間に被着されており、前記第2の開口部同士の間を抜けるようにして互いに所定間隔で平行に延在する帯状配線導体のペアと、を具備して成る配線基板であって、前記第1乃至第3の接地または電源用導体層は、前記第1乃至第3の開口部における長孔形状の中央部の内側に張り出した突起部または島部を有し、該突起部および/または島部における前記帯状配線導体のペアの両側に前記第1乃至第3の接地または電源用導体層を接続する貫通導体が接続されていることを特徴とするものである。   The wiring board of the present invention includes an insulating substrate formed by laminating a plurality of insulating layers including at least a first insulating layer and a second insulating layer stacked on the first insulating layer, A plurality of external connection pads arranged in pairs so as to be adjacent to each other and in pairs are attached to the lower surface and the lower surface of the first insulating layer. A first grounding or power supply conductor layer formed with a first opening having a long hole shape surrounding each pair of the external connection pads in a top view at a position corresponding to the pair of external connection pads; A long hole that is deposited between the first insulating layer and the second insulating layer and surrounds the pair of external connection pads in a top view at a position corresponding to the pair of external connection pads. A second ground or electricity formed with a shaped second opening. A third conductor having a long hole shape that is attached to the upper surface of the conductive layer and the second insulating layer and surrounds the pair of external connection pads in a top view at a position corresponding to the pair of external connection pads. A third ground or power supply conductor layer having an opening formed between the first insulating layer and the second insulating layer, and a gap between the second openings. A wiring board comprising a pair of strip-like wiring conductors extending in parallel with each other at a predetermined interval so as to come out, wherein the first to third ground or power supply conductor layers are the first to third layers. The third opening has a projecting portion or an island portion projecting inside a long hole-shaped central portion, and the first to third sides on both sides of the pair of strip-shaped wiring conductors in the projecting portion and / or the island portion. Make sure that the through conductor that connects the grounding or power supply conductor layer is connected. It is an butterfly.

本発明の配線基板によれば、第1乃至第3の接地または電源用導体層は、第1乃至第3の開口部における長孔形状の中央部の内側に張り出した突起部または島部を有し、これらの突起部または島部における帯状配線導体のペアの両側に第1乃至第3の接地または電源用導体層を接続する貫通導体が接続されていることから、帯状配線導体のペアが第2の開口部の間を抜ける部分においても、帯状配線導体のペアの両側にシールド用の接地または電源用の貫通導体を設けることができ、それにより帯状配線導体のペアの両側に沿ってシールド用の貫通導体を所定の間隔で形成して帯状配線導体のペアを外部から良好にシールドすることが可能となる。   According to the wiring board of the present invention, the first to third grounding or power supply conductor layers have protrusions or islands projecting inside the central portion of the long hole shape in the first to third openings. In addition, since the through conductors connecting the first to third grounding or power supply conductor layers are connected to both sides of the pair of strip-like wiring conductors in these protrusions or islands, the pair of strip-like wiring conductors is the first. Even in the portion that passes between the two openings, shield grounding or power supply through conductors can be provided on both sides of the pair of strip-shaped wiring conductors, thereby shielding along the both sides of the pair of strip-shaped wiring conductors. Thus, it becomes possible to shield the pair of strip-shaped wiring conductors from the outside satisfactorily.

図1は、本発明の配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図2は、図1に示す配線基板の導体層の一部および貫通導体の一部のみを抜き出して示した斜視図である。FIG. 2 is a perspective view showing only a part of the conductor layer and part of the through conductor of the wiring board shown in FIG. 図3は、図1および図2に示した配線基板の各導体層の一部を導体層別に示した平面図である。FIG. 3 is a plan view showing a part of each conductor layer of the wiring board shown in FIGS. 1 and 2 for each conductor layer. 図4は、従来の配線基板を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. 図5は、図4に示す配線基板の導体層の一部および貫通導体の一部のみを抜き出して示した斜視図である。FIG. 5 is a perspective view showing only a part of the conductor layer and a part of the through conductor of the wiring board shown in FIG. 図6は、図4および図5に示した配線基板の各導体層の一部を導体層別に示した平面図である。FIG. 6 is a plan view showing a part of each conductor layer of the wiring board shown in FIGS. 4 and 5 for each conductor layer.

次に、本発明の配線基板における実施形態の一例を説明する。図1は、本例の配線基板100を示す概略断面図であり、図中、10は絶縁層11,12,13,14,15が積層されて成る絶縁基板、21,22,23,24,25,26は導体層、30は半導体素子接続パッド、40は外部接続パッド、51,52,53,54,55は貫通導体、61,62はソルダーレジスト層である。本例の配線基板100は、コア用の絶縁層13の上面にビルドアップ用の絶縁層12および11を積層するとともに絶縁層13の下面にビルドアップ用の絶縁層14および15を積層して成る絶縁基板10の上下面および絶縁層11,12,13,14,15の間に配線導体用の導体層21,22,23,24,25,26が配置されて成る。絶縁基板10の上面中央部には半導体素子Sの電極端子に半田バンプB1を介して電気的に接続される半導体素子接続パッド30が形成されており、絶縁基板10の下面には外部電気回路基板の配線導体に半田ボールを介して電気的に接続される外部接続パッド40が形成されている。これらの半導体素子接続パッド30と外部接続パッド40とは導体層21,22,23,24,25,26に形成された配線導体および各絶縁層11,12,13,14,15をそれぞれ貫通する貫通導体51,52,53,54,55を介して互いに電気的に接続されている。さらに、最上層の絶縁層11および導体層21の表面には半導体素子接続パッド30の中央部を露出させる開口部を有するソルダーレジスト層61が被着されており、最下層の絶縁層15および導体層26の表面には外部接続パッド40の中央部を露出させる開口部を有するソルダーレジスト層62が被着されている。   Next, an example of an embodiment of the wiring board of the present invention will be described. FIG. 1 is a schematic sectional view showing a wiring board 100 of this example, in which 10 is an insulating board in which insulating layers 11, 12, 13, 14, and 15 are laminated, 21, 22, 23, 24, 25 and 26 are conductor layers, 30 is a semiconductor element connection pad, 40 is an external connection pad, 51, 52, 53, 54 and 55 are through conductors, and 61 and 62 are solder resist layers. The wiring board 100 of this example is formed by laminating build-up insulating layers 12 and 11 on the upper surface of a core insulating layer 13 and laminating build-up insulating layers 14 and 15 on the lower surface of the insulating layer 13. Conductor layers 21, 22, 23, 24, 25, 26 for wiring conductors are arranged between the upper and lower surfaces of the insulating substrate 10 and the insulating layers 11, 12, 13, 14, 15. A semiconductor element connection pad 30 that is electrically connected to the electrode terminal of the semiconductor element S via the solder bump B1 is formed at the center of the upper surface of the insulating substrate 10, and an external electric circuit board is formed on the lower surface of the insulating substrate 10. External connection pads 40 that are electrically connected to the wiring conductors via solder balls are formed. The semiconductor element connection pad 30 and the external connection pad 40 penetrate through the wiring conductors formed in the conductor layers 21, 22, 23, 24, 25, and 26 and the insulating layers 11, 12, 13, 14, and 15, respectively. The through conductors 51, 52, 53, 54 and 55 are electrically connected to each other. Furthermore, a solder resist layer 61 having an opening exposing the central portion of the semiconductor element connection pad 30 is deposited on the surfaces of the uppermost insulating layer 11 and the conductor layer 21, and the lowermost insulating layer 15 and the conductor are exposed. A solder resist layer 62 having an opening that exposes the central portion of the external connection pad 40 is deposited on the surface of the layer 26.

絶縁層13は、配線基板100のコア基板となる部材であり、例えばガラス繊維束を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成り、厚みが0.3〜1.5mm程度であり、その上面から下面にかけて直径が0.1〜0.3mm程度の複数のスルーホール13aを有している。そして、その上下面には導体層23,24が被着されており、スルーホール13aの内面には貫通導体53が被着されている。なお、貫通導体53が被着されたスルーホール13a内は樹脂により充填されている。   The insulating layer 13 is a member that becomes a core substrate of the wiring substrate 100, and is formed by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. It has a plurality of through holes 13a having a diameter of about 0.1 to 0.3 mm from the upper surface to the lower surface. The conductor layers 23 and 24 are attached to the upper and lower surfaces, and the through conductor 53 is attached to the inner surface of the through hole 13a. In addition, the inside of the through hole 13a to which the through conductor 53 is attached is filled with resin.

このような絶縁層13は、ガラス織物に未硬化の熱硬化性樹脂を含浸させた絶縁シートを熱硬化させた後、これに上面から下面にかけてスルーホール13aをドリル加工することにより製作される。なお、絶縁層13上下面の導体層23,24は、絶縁層13用の絶縁シートの上下全面に厚みが3〜50μm程度の銅箔を貼着しておくとともに、この銅箔をシートの硬化後にエッチング加工することにより所定のパターンに形成される。また、スルーホール13a内面の貫通導体53は、スルーホール13a内面に無電解めっき法および電解めっき法により厚みが3〜50μm程度の銅めっき膜を析出させることにより形成される。なお、スルーホール13a内を樹脂により充填するには、貫通導体53が形成されたスルーホール13a内に未硬化のペースト状の熱硬化性樹脂をスクリーン印刷法により充填し、その後、充填された樹脂を熱硬化させる方法が採用される。   Such an insulating layer 13 is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling through holes 13a from the upper surface to the lower surface. The conductor layers 23 and 24 on the upper and lower surfaces of the insulating layer 13 have a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the insulating sheet for the insulating layer 13, and the copper foil is cured on the sheet. A predetermined pattern is formed by etching later. The through conductor 53 on the inner surface of the through hole 13a is formed by depositing a copper plating film having a thickness of about 3 to 50 μm on the inner surface of the through hole 13a by an electroless plating method and an electrolytic plating method. In order to fill the through hole 13a with a resin, an uncured paste-like thermosetting resin is filled into the through hole 13a in which the through conductors 53 are formed by a screen printing method, and then the filled resin is filled. A method of thermally curing is adopted.

絶縁層13の上下面に積層された各絶縁層11,12,14,15は、ビルドアップ絶縁層であり、エポキシ樹脂等の熱硬化性樹脂に酸化珪素粉末等の無機絶縁物フィラーを30〜70質量%程度分散させた絶縁材料から成る。絶縁層11,12,14,15は、それぞれの厚みが20〜60μm程度であり、各層の上面から下面にかけて直径が30〜100μm程度の複数のビアホール11a,12a,14a,15aを有している。ビアホール11a,12a,14a,15a内には、貫通導体51,52,54,55がそれぞれ充填されており、これらの貫通導体51,52,54,55を介して導体層21,22,23,24,25,26の所定の配線パターン同士を電気的に接続することにより高密度配線が立体的に形成可能となっている。このような各絶縁層11,12,14,15は、厚みが20〜60μm程度の未硬化の熱硬化性樹脂から成る絶縁フィルムを絶縁層13の上下面に貼着し、これを熱硬化させるとともにレーザ加工によりビアホール12a,14aを穿孔し、さらにその上に同様にして次の絶縁層11,15を順次積み重ねることによって形成される。なお、各絶縁層11,12,14,15の表面に被着された導体層21,22,25,26およびビアホール11a,12a,14a,15a内に充填された貫通導体51,52,54,55は、各絶縁層11,12,14,15を形成する毎に各絶縁層11,12,14,15の表面およびビアホール11a,12a,14a,15a内に5〜50μm程度の厚みの銅めっき膜を公知のセミアディティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。   Each of the insulating layers 11, 12, 14, and 15 laminated on the upper and lower surfaces of the insulating layer 13 is a build-up insulating layer, and an inorganic insulating filler such as silicon oxide powder is added to a thermosetting resin such as an epoxy resin 30 to 30. It is made of an insulating material dispersed by about 70% by mass. The insulating layers 11, 12, 14, and 15 each have a thickness of about 20 to 60 μm, and have a plurality of via holes 11a, 12a, 14a, and 15a having a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. . The via holes 11a, 12a, 14a, and 15a are filled with penetrating conductors 51, 52, 54, and 55, respectively, and the conductor layers 21, 22, 23, and 23 are inserted through the penetrating conductors 51, 52, 54, and 55, respectively. By electrically connecting predetermined wiring patterns 24, 25, and 26, high-density wiring can be formed in three dimensions. Each of the insulating layers 11, 12, 14, and 15 has an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 μm attached to the upper and lower surfaces of the insulating layer 13 and thermally cured. At the same time, the via holes 12a and 14a are formed by laser processing, and the next insulating layers 11 and 15 are sequentially stacked thereon in the same manner. The conductor layers 21, 22, 25, 26 deposited on the surfaces of the insulating layers 11, 12, 14, 15 and the through conductors 51, 52, 54, filled in the via holes 11a, 12a, 14a, 15a, 55 is a copper plating having a thickness of about 5 to 50 μm in the surface of each insulating layer 11, 12, 14, 15 and in the via holes 11 a, 12 a, 14 a, 15 a every time each insulating layer 11, 12, 14, 15 is formed. The film is formed by depositing a film in a predetermined pattern by a pattern forming method such as a known semi-additive method.

また、ソルダーレジスト層61,62は、例えばアクリル変性エポキシ樹脂等の熱硬化性樹脂にシリカやタルク等のフィラーを含有させて成り、上面側のソルダーレジスト層61であれば、半導体素子接続パッド30の中央部を露出させる開口部を有しているとともに、下面側のソルダーレジスト層62であれば、外部接続パッド40の中央部を露出させる開口部を有している。このようなソルダーレジスト層61,62は、その厚みが10〜50μm程度であり、感光性を有するソルダーレジスト層61,62用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して絶縁層11,15の上に塗布し、これを乾燥させた後、露光および現像処理を行なって半導体素子接続パッド30や外部接続パッド40の中央部を露出させる開口部を形成した後、これを熱硬化させることによって形成される。     In addition, the solder resist layers 61 and 62 are formed by adding a filler such as silica or talc to a thermosetting resin such as an acrylic-modified epoxy resin. If the solder resist layer 61 is on the upper surface side, the semiconductor element connection pad 30 is used. In addition, the solder resist layer 62 on the lower surface side has an opening for exposing the central portion of the external connection pad 40. The solder resist layers 61 and 62 have a thickness of about 10 to 50 μm, and the uncured resin paste for the solder resist layers 61 and 62 having photosensitivity is insulated by adopting a roll coater method or a screen printing method. After coating on the layers 11 and 15 and drying them, exposure and development are performed to form openings that expose the central portions of the semiconductor element connection pads 30 and the external connection pads 40, and then this is heated. It is formed by curing.

図2に、上述した配線基板100における導体層21,22,23,24,25,26の一部および貫通導体51,52,53,54,55の一部のみを抜き出した斜視図を示す。半導体素子接続パッド30のうち、一部のものは互いに隣接する2個がペア31,32を形成している。一方の半導体素子接続パッドのペア31には導体層21により形成されたペア伝送路の帯状配線導体のペア71が接続されている。帯状配線導体のペア71は、その端部を除いて互いに所定間隔で平行に延びており、その他端部が貫通導体51a,52a,53a,54a,55aおよびランドを介して外部接続パッドのペア41に電気的に接続されている。他方、半導体素子接続パッドのペア32には導体層25により形成されたペア伝送路の帯状配線導体を形成する帯状配線導体のペア72が貫通導体51b,52b,53b,54bおよびランドを介して接続されている。帯状配線導体のペア72は、帯状配線導体のペア71と同様にその端部を除いて互いに所定間隔で平行に延びており、その他端部が貫通導体55bおよびランドを介して外部接続パッドのペア42に電気的に接続されている。   FIG. 2 is a perspective view in which only a part of the conductor layers 21, 22, 23, 24, 25, and 26 and a part of the through conductors 51, 52, 53, 54, and 55 are extracted from the wiring board 100 described above. Some of the semiconductor element connection pads 30 are adjacent to each other to form pairs 31 and 32. One pair of semiconductor element connection pads 31 is connected to a pair 71 of band-shaped wiring conductors of a pair transmission path formed by the conductor layer 21. The strip-like wiring conductor pair 71 extends in parallel with each other at a predetermined interval except for its end portion, and the other end portion is connected to the pair 41 of external connection pads via the through conductors 51a, 52a, 53a, 54a, 55a and lands. Is electrically connected. On the other hand, the pair of semiconductor element connection pads 32 is connected to a pair 72 of band-shaped wiring conductors that form a band-shaped wiring conductor of a pair transmission path formed by the conductor layer 25 through through conductors 51b, 52b, 53b, 54b and lands. Has been. The pair of strip-shaped wiring conductors 72 extend in parallel with each other at a predetermined interval except for the end portions thereof, like the pair of strip-shaped wiring conductors 71, and the other end portion is a pair of external connection pads via the through conductor 55b and the land. 42 is electrically connected.

ここで、図2に示した半導体素子接続パッドのペア31,32、帯状配線導体のペア71,72、外部接続パッドのペア41,42およびランドの一部を各導体層21,22,23,24,25,26別に図3(a)〜(f)に平面図で示す。図3(a)に示すように、導体層21においては、半導体素子接続パッドのペア31,32と帯状配線導体のペア71とランド81aと接地または電源用導体層91が形成されている。半導体素子接続パッドのペア31,32および帯状配線導体のペア71ならびにランド81aと接地または導体層91との間には所定間隔が形成されている。   Here, the semiconductor element connection pad pair 31, 32, the strip-like wiring conductor pair 71, 72, the external connection pad pair 41, 42 and a part of the land shown in FIG. 24, 25, and 26 are shown in plan views in FIGS. As shown in FIG. 3A, in the conductor layer 21, a pair 31 and 32 of semiconductor element connection pads, a pair 71 of strip-like wiring conductors, a land 81a, and a ground or power source conductor layer 91 are formed. A predetermined gap is formed between the pair 31 and 32 of semiconductor element connection pads, the pair 71 of strip-like wiring conductors, and the land 81 a and the ground or conductor layer 91.

図3(b)に示すように、導体層22においては、ランド82aおよび82bと接地または電源用導体層92とが形成されている。ランド82aは、図示しない貫通導体51aを介して上層のランド81aに接続されている。ランド82bは、図示しない貫通導体51bを介して上層の半導体素子接続パッドのペア32に接続されている。   As shown in FIG. 3B, in the conductor layer 22, lands 82a and 82b and a ground or power source conductor layer 92 are formed. The land 82a is connected to the upper land 81a via a through conductor 51a (not shown). The land 82b is connected to the pair 32 of upper-layer semiconductor element connection pads via a through conductor 51b (not shown).

図3(c)に示すように、導体層23においては、ランド83aおよびランド83bと接地または電源用導体層93とが形成されている。ランド83aは図示しない貫通導体52aを介して上層のランド82aに接続されている。ランド83bは、図示しない貫通導体52bを介して上層のランド82bに接続されている。   As shown in FIG. 3C, in the conductor layer 23, lands 83a and lands 83b and a ground or power source conductor layer 93 are formed. The land 83a is connected to the upper land 82a through a through conductor 52a (not shown). The land 83b is connected to the upper land 82b via a through conductor 52b (not shown).

図3(d)に示すように、導体層24においては、ランド84aおよびランド84bと接地または電源用導体層94とが形成されている。ランド84aは図示しない貫通導体53aを介して上層のランド83aに接続されている。ランド84bは、図示しない貫通導体53bを介して上層のランド83bに接続されている。   As shown in FIG. 3D, in the conductor layer 24, lands 84a and lands 84b and a ground or power source conductor layer 94 are formed. The land 84a is connected to an upper land 83a via a through conductor 53a (not shown). The land 84b is connected to the upper land 83b via a through conductor 53b (not shown).

図3(e)に示すように、導体層25においては、帯状配線導体のペア72と、ランド85a,85b,85cと接地または電源用導体層95とが形成されている。ランド85aは図示しない貫通導体54aを介して上層のランド84aに接続されている。ランド85bは、図示しない貫通導体54bを介して上層のランド84bに接続されている。   As shown in FIG. 3 (e), in the conductor layer 25, a strip-like wiring conductor pair 72, lands 85a, 85b, 85c, and a ground or power source conductor layer 95 are formed. The land 85a is connected to the upper land 84a through a through conductor 54a (not shown). The land 85b is connected to the upper land 84b through a through conductor 54b (not shown).

図3(f)に示すように、導体層26においては、外部接続パッドのペア41,42とランド86a,86bと接地または電源用導体層96とが形成されている。ランド86aは図示しない貫通導体55aを介して上層のランド85aに接続されている。ランド86bは、図示しない貫通導体55bを介して上層のランド85cに接続されている。   As shown in FIG. 3F, in the conductor layer 26, external connection pad pairs 41, 42, lands 86a, 86b, and a ground or power source conductor layer 96 are formed. The land 86a is connected to an upper land 85a through a through conductor 55a (not shown). The land 86b is connected to an upper land 85c through a through conductor 55b (not shown).

そして、この配線基板100においては、ペア伝送路の帯状配線導体のペア71,72に接続される外部接続パッドのペア41,42に対向する位置の接地または電源用導体層91,92,93,94,95,96に、長孔形状の開口部91a,92a,93a,94a,95a,96aを設けている。このような開口部91a,92a,93a,94a,95a,96aを設けることにより、接地または電源用の導体層91,92,93,94,95,96とペア伝送路の帯状配線導体のペア71,72に接続される外部接続パッドのペア41,42との間の静電容量が低減され、それにより外部接続用パッドのペア41,42における信号の反射が抑制されて高周波信号を効率よく外部に伝送することが可能となる。   In this wiring board 100, grounding or power supply conductor layers 91, 92, 93, which are opposed to the external connection pad pairs 41, 42 connected to the strip wiring conductor pairs 71, 72 of the pair transmission line, 94, 95, 96 are provided with elongated hole-shaped openings 91a, 92a, 93a, 94a, 95a, 96a. By providing such openings 91 a, 92 a, 93 a, 94 a, 95 a, 96 a, grounding or power supply conductor layers 91, 92, 93, 94, 95, 96 and a pair 71 of band-shaped wiring conductors in a pair transmission path are provided. , 72 is reduced in electrostatic capacitance between the pair of external connection pads 41 and 42, thereby suppressing the reflection of signals in the pair 41 and 42 of external connection pads, thereby efficiently externalizing high frequency signals. Can be transmitted.

なお、開口部91a,92a,93aは概ね長円状の長孔形状であり、上面視で外部接続パッドのペア41,42をそれぞれ囲繞する大きさである。また、開口部94a,95a,96aは、概ね鉄アレイ形の長孔形状であり、上面視で外部接続パッドのペア41,42を囲繞する大きさである。そして、接地または電源用導体層94は、開口部94aの中央部の内側に張り出した突起部94bを各開口部94aの両側に有し、接地または電源用導体層95は、開口部95aの中央部の内側に張り出した突起部95bまたは島部95cを各開口部95aの両側に有し、接地または電源用導体層96は、開口部96aの中央部の内側に張り出した突起部96bを各開口部96aの両側に有している。   The openings 91a, 92a, and 93a have a generally elliptical long hole shape, and are large enough to surround the external connection pad pairs 41 and 42, respectively, when viewed from above. The openings 94a, 95a, and 96a have a generally iron array long hole shape, and are sized to surround the external connection pad pairs 41 and 42 in a top view. The ground or power conductor layer 94 has protrusions 94b projecting inside the center of the opening 94a on both sides of each opening 94a, and the ground or power conductor layer 95 is located at the center of the opening 95a. Each of the openings 95a has protrusions 95b or islands 95c projecting on the inner side of the opening, and the ground or power conductor layer 96 has the protrusions 96b projecting on the inner side of the central part of the opening 96a. It has on both sides of the part 96a.

さらに、絶縁層14,15には、帯状配線導体のペア72の両側に沿って上下の接地または電源用導体層94,95,96の間を接続するシールド用の貫通導体54c,55cが所定間隔で並べて設けられている。このようなシールド用の貫通導体54c,55cを設けることによって、帯状配線導体のペア72を伝送する信号に外部からノイズが入ったり、帯状配線導体のペア72から外部にノイズが漏れたりするのを有効に防止している。そして、本例の配線基板100においては、シールド用の貫通導体54c,55cが突起部94b,95b,96bおよび島部95cにおける帯状配線導体のペア72の両側に設けられている。そのため、帯状配線導体のペア72が開口部95aの間を抜ける部分においても、帯状配線導体のペア72の両側にシールド用の貫通導体54c,55cを設けることができ、それにより帯状配線導体のペア72の両側に沿ってシールド用の貫通導体54c,55cを所定の間隔で形成して帯状配線導体のペア72を外部から良好にシールドすることが可能となる。なお、突起部94b,95b,96bおよび島部95cが、開口部94a,95a,96aの中央部の内側に張り出す長さおよび幅は、突起部94b,95b,96bおよび島部95cにシールド用の貫通導体54c,55cが所定の間隔で接続できる幅であればよい。   Further, shield insulating through conductors 54c and 55c connecting the upper and lower grounding or power supply conductor layers 94, 95 and 96 along the both sides of the strip-like wiring conductor pair 72 are formed on the insulating layers 14 and 15 at a predetermined interval. Are arranged side by side. By providing such shielding through conductors 54c and 55c, it is possible to prevent noise from entering the signal transmitted through the strip-shaped wiring conductor pair 72 or from leaking from the strip-shaped wiring conductor pair 72 to the outside. Effectively preventing. In the wiring substrate 100 of this example, shield through conductors 54c and 55c are provided on both sides of the pair of strip-like wiring conductors 72 in the protrusions 94b, 95b, and 96b and the island portion 95c. Therefore, even in a portion where the pair of strip-shaped wiring conductors 72 passes between the openings 95a, the shielding through conductors 54c and 55c can be provided on both sides of the pair of strip-shaped wiring conductors 72, thereby forming the pair of strip-shaped wiring conductors. The shield through conductors 54c and 55c are formed at predetermined intervals along both sides of the 72, so that the pair 72 of the strip-shaped wiring conductors can be well shielded from the outside. Note that the length and width of the protrusions 94b, 95b, 96b and the island part 95c projecting inside the central part of the openings 94a, 95a, 96a are shielded by the protrusions 94b, 95b, 96b and the island part 95c. As long as the through conductors 54c and 55c can be connected at a predetermined interval.

10・・・絶縁基板
11,12,13,14,15・・・絶縁層
41,42・・・外部接続パッドのペア
71,72・・・帯状配線導体のペア
91,92,93,94,95・・・接地または電源用導体層
91a,92a,93a,94a,95a,96a・・・開口部
94b,95b,96b・・・突起部
95c・・・島部
54c,55c・・・シールド用の貫通導体
100・・・配線基板
DESCRIPTION OF SYMBOLS 10 ... Insulating substrate 11, 12, 13, 14, 15 ... Insulating layer 41, 42 ... Pair of external connection pads 71, 72 ... Pair of strip-shaped wiring conductors 91, 92, 93, 94, 95: Conductive layer for grounding or power supply 91a, 92a, 93a, 94a, 95a, 96a ... Opening 94b, 95b, 96b ... Projection 95c ... Island 54c, 55c ... For shielding Through conductor 100 ... wiring board

Claims (1)

少なくとも第1の絶縁層と該第1の絶縁層上に積層された第2の絶縁層とを含む複数の絶縁層が積層されて成る絶縁基板と、前記絶縁基板の下面に被着されており、互いに隣接して対向するように並んだ2個ずつがそれぞれペアをなすように配置された複数の外部接続パッドと、前記第1の絶縁層の下面に被着されており、前記外部接続パッドのペアに対応する位置に上面視で前記外部接続パッドのペアをそれぞれ囲繞する長孔形状の第1の開口部が形成された第1の接地または電源用導体層と、前記第1の絶縁層と第2の絶縁層との間に被着されており、前記外部接続パッドの前記ペアに対応する位置に上面視で前記外部接続パッドのペアをそれぞれ囲繞する長孔形状の第2の開口部が形成された第2の接地または電源用導体層と、前記第2の絶縁層の上面に被着されており、前記外部接続パッドのペアに対応する位置に上面視で該外部接続パッドのペアをそれぞれ囲繞する長孔形状の第3の開口部が形成された第3の接地または電源用導体層と、前記第1の絶縁層と第2の絶縁層との間に被着されており、前記第2の開口部同士の間を抜けるようにして互いに所定間隔で平行に延在する帯状配線導体のペアと、を具備して成る配線基板であって、前記第1乃至第3の接地または電源用導体層は、前記第1乃至第3の開口部における長孔形状の中央部の内側に張り出した突起部または島部を有し、該突起部および/または島部における前記帯状配線導体のペアの両側に前記第1乃至第3の接地または電源用導体層を接続する貫通導体が接続されていることを特徴とする配線基板。   An insulating substrate formed by laminating a plurality of insulating layers including at least a first insulating layer and a second insulating layer stacked on the first insulating layer; and is attached to a lower surface of the insulating substrate. A plurality of external connection pads arranged adjacent to each other so as to form a pair, and attached to the lower surface of the first insulating layer, and the external connection pads A first grounding or power supply conductor layer in which a first opening having a long hole shape surrounding each pair of the external connection pads in a top view is formed at a position corresponding to the pair of the first and second insulating layers; A second opening having a long hole shape that is attached between the first and second insulating layers and surrounds the pair of external connection pads in a top view at a position corresponding to the pair of external connection pads. A second ground or power source conductor layer formed with A third opening having a long hole shape is formed at a position corresponding to the pair of external connection pads, and surrounds the pair of external connection pads in a top view, at a position corresponding to the pair of external connection pads. 3 and a conductor layer for grounding or power, and the first insulating layer and the second insulating layer, and are spaced from each other at predetermined intervals so as to pass through the second openings. A pair of strip-shaped wiring conductors extending in parallel, wherein the first to third grounding or power supply conductor layers are elongated holes in the first to third openings. A projecting portion or an island portion projecting inside the central portion of the shape, and the first to third grounding or power supply conductor layers are provided on both sides of the strip-like wiring conductor pair in the projecting portion and / or the island portion. A wiring board characterized in that a connecting through conductor is connected.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015106599A (en) * 2013-11-29 2015-06-08 京セラサーキットソリューションズ株式会社 Wiring board
JP2017085132A (en) * 2016-12-15 2017-05-18 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2017120932A (en) * 2017-04-03 2017-07-06 株式会社フジクラ Printed Wiring Board
US10129978B2 (en) 2014-09-22 2018-11-13 Fujikura Ltd. Printed wiring board
WO2021038951A1 (en) 2019-08-23 2021-03-04 日本特殊陶業株式会社 Wiring substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006093325A (en) * 2004-09-22 2006-04-06 Kyocera Corp Wiring board
JP2009100003A (en) * 2004-02-13 2009-05-07 Molex Inc Preferential grounding, and via extension structure for printed circuit board
JP2009212400A (en) * 2008-03-05 2009-09-17 Ngk Spark Plug Co Ltd High-frequency package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009100003A (en) * 2004-02-13 2009-05-07 Molex Inc Preferential grounding, and via extension structure for printed circuit board
JP2006093325A (en) * 2004-09-22 2006-04-06 Kyocera Corp Wiring board
JP2009212400A (en) * 2008-03-05 2009-09-17 Ngk Spark Plug Co Ltd High-frequency package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015106599A (en) * 2013-11-29 2015-06-08 京セラサーキットソリューションズ株式会社 Wiring board
US10129978B2 (en) 2014-09-22 2018-11-13 Fujikura Ltd. Printed wiring board
JP2017085132A (en) * 2016-12-15 2017-05-18 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2017120932A (en) * 2017-04-03 2017-07-06 株式会社フジクラ Printed Wiring Board
WO2021038951A1 (en) 2019-08-23 2021-03-04 日本特殊陶業株式会社 Wiring substrate

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