JP2006093325A - Wiring board - Google Patents

Wiring board Download PDF

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JP2006093325A
JP2006093325A JP2004275521A JP2004275521A JP2006093325A JP 2006093325 A JP2006093325 A JP 2006093325A JP 2004275521 A JP2004275521 A JP 2004275521A JP 2004275521 A JP2004275521 A JP 2004275521A JP 2006093325 A JP2006093325 A JP 2006093325A
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conductor
differential
line
signal
wiring board
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JP4601369B2 (en
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Koki Kawabata
幸喜 川畑
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

<P>PROBLEM TO BE SOLVED: To largely suppress reflection loss of a high frequency signal in a connection part of a differential line and a differential through conductor, and to make operability of a semiconductor element to be sufficient. <P>SOLUTION: A wiring board 1 is provided with the differential line 8 formed of a pair of signal lines 8a and 8b which are formed on the main face or the inner part of an insulating substrate 2 and are mutually parallel, an identical face ground conductor 4b formed to surround the differential line 8 at a prescribed interval, land conductors 13 arranged at one end of each signal line 8a and 8b, and through conductors 9a and 9b where one end is electrically connected to the land conductors 13. In the differential line 8, one end of a land conductor 13-side is set to be a developing part 14 where an interval between a pair of signal lines 8a and 8b gradually spreads, and line width of the developing part 14 of the signal lines 8a and 8b is smaller than that of a part except for the developing part 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、高速で作動する半導体素子や光半導体素子等の電子部品を搭載するのに好適な、差動線路を有する配線基板に関する。   The present invention relates to a wiring board having a differential line suitable for mounting electronic components such as a semiconductor element and an optical semiconductor element that operate at high speed.

従来、高速で作動するIC,LSI等の半導体素子や光半導体素子等の電子部品を搭載するための配線基板においては、従来の配線基板の例の断面図である図4に示すように、高速の高周波信号を正確かつ効率よく伝播させるために、差動線路48を用いている。また、差動線路48は、外部と高周波信号の入出力を行なうために差動貫通導体49を介して外部接続用電極411に電気的に接続されており、また、差動貫通導体49、電極パッド47および導体バンプ46を介して半導体素子45の電極に電気的に接続されている。   Conventionally, in a wiring board for mounting electronic components such as semiconductor elements such as IC and LSI that operate at high speed and optical semiconductor elements, as shown in FIG. 4 which is a cross-sectional view of an example of a conventional wiring board, high speed The differential line 48 is used to accurately and efficiently propagate the high frequency signal. The differential line 48 is electrically connected to the external connection electrode 411 through the differential through conductor 49 in order to input / output a high frequency signal to / from the outside. The pads 47 and the conductor bumps 46 are electrically connected to the electrodes of the semiconductor element 45.

差動線路48は、配線基板41の部分拡大断面図5に示すように、一対の信号線路48a,48bによって決定される特性インピーダンスが所望の値となるように、絶縁基板42の絶縁層42a〜42fの材料、絶縁層42a〜42fの断面構造、即ち信号線路48a, 48bの幅、厚み及び間隔、信号線路48a, 48bと内層接地導体42a〜42cとの距離等を制御して決定されている。   As shown in the partial enlarged cross-sectional view of the wiring substrate 41, the differential line 48 has insulating layers 42a to 42b on the insulating substrate 42 so that the characteristic impedance determined by the pair of signal lines 48a and 48b becomes a desired value. 42f, the cross-sectional structure of the insulating layers 42a to 42f, that is, the widths, thicknesses and intervals of the signal lines 48a and 48b, the distances between the signal lines 48a and 48b and the inner-layer ground conductors 42a to 42c, and the like. .

差動貫通導体49は、配線基板41の部分拡大平面図6に示すように、一対の貫通導体49a,49bによって決定される特性インピーダンスが所望の値となるように、配線基板42の絶縁層42a〜42fの材料、差動貫通導体49及び接地貫通導体410の直径を変更したり、更にこれらの相対位置を互いに変更することによって決定されている。また、差動貫通導体49の周囲には、それを平面視で円形状に取り囲むように開口部412が形成された内層接地導体44aが形成されている。   As shown in the partial enlarged plan view 6 of the wiring board 41, the differential through conductor 49 has an insulating layer 42a of the wiring board 42 so that the characteristic impedance determined by the pair of through conductors 49a and 49b becomes a desired value. It is determined by changing the diameter of the material of ~ 42f, the differential through conductor 49 and the ground through conductor 410, and further changing their relative positions. Further, an inner layer ground conductor 44a having an opening 412 is formed around the differential through conductor 49 so as to surround it in a circular shape in plan view.

また、配線基板41に形成された差動線路48と差動貫通導体49との接続部周辺の要部拡大平面図である図7に示すように、差動貫通導体49と差動線路48との接続は、差動線路48の信号線路48a,48bの間隔が漸次広がる展開部414が、その一端に接続されたランド導体部413を介して接続されることによってなされる。また、差動線路48と差動貫通導体49との接続部の周囲には、接続部を平面視で円形状に取り囲むように開口部412が形成された内層接地導体44bが形成されている。
特開2001−54497号公報
Further, as shown in FIG. 7 which is an enlarged plan view of the main part around the connection portion between the differential line 48 and the differential through conductor 49 formed on the wiring board 41, the differential through conductor 49 and the differential line 48 are Is connected by connecting a development portion 414 in which the distance between the signal lines 48a and 48b of the differential line 48 gradually increases via a land conductor portion 413 connected to one end thereof. In addition, an inner layer ground conductor 44b having an opening 412 formed so as to surround the connection portion in a circular shape in plan view is formed around the connection portion between the differential line 48 and the differential through conductor 49.
JP 2001-54497 A

しかしながら、従来の配線基板41に搭載される半導体素子45の動作速度が数十GHzと高速化するに従い、差動線路48と差動貫通導体49との接続部において、ランド導体部413を介して差動線路48と差動貫通導体49が接続されるため、内層接地導体44bとランド導体部413との間に発生する容量成分によって特性インピーダンスが低下するために、高周波信号の反射が発生していた。その結果、差動線路48と差動貫通導体49との接続部において、高周波信号の反射損失が大きくなって高周波信号の伝送性が劣化し、半導体素子45の作動性が損なわれるという問題点があった。   However, as the operation speed of the semiconductor element 45 mounted on the conventional wiring board 41 is increased to several tens GHz, the connection portion between the differential line 48 and the differential through conductor 49 is connected via the land conductor portion 413. Since the differential line 48 and the differential through conductor 49 are connected, the characteristic impedance is reduced due to the capacitance component generated between the inner layer ground conductor 44b and the land conductor portion 413, so that the reflection of the high frequency signal occurs. It was. As a result, the connection loss between the differential line 48 and the differential through conductor 49 increases the reflection loss of the high frequency signal, degrades the transmission performance of the high frequency signal, and impairs the operability of the semiconductor element 45. there were.

本発明は、上記問題点に鑑みて完成されたものであり、その目的は、差動線路と差動貫通導体との接続部における高周波信号の反射損失を大幅に抑制することができ、その結果、半導体素子の作動性を良好なものとできる配線基板を提供することにある。   The present invention has been completed in view of the above-mentioned problems, and the object thereof is to greatly suppress the reflection loss of the high-frequency signal at the connecting portion between the differential line and the differential through conductor. An object of the present invention is to provide a wiring board capable of improving the operability of a semiconductor element.

本発明の配線基板は、絶縁基体の主面または内部に形成された互いに平行な一対の信号線路から成る差動線路と、該差動線路を所定間隔をもって取り囲むように形成された同一面接地導体と、前記各信号線路の一端に設けられたランド導体部と、該ランド導体部に一端が電気的に接続された貫通導体とを具備しており、前記差動線路は、前記ランド導体部側の一端部が前記一対の信号線路同士の間の間隔が漸次広がっている展開部とされているとともに、前記各信号線路の前記展開部の線路幅が前記展開部以外の部位の線路幅よりも小さいことを特徴とする。   The wiring board of the present invention includes a differential line composed of a pair of parallel signal lines formed on the main surface or inside of an insulating base, and a coplanar ground conductor formed so as to surround the differential line at a predetermined interval. And a land conductor portion provided at one end of each signal line, and a through conductor whose one end is electrically connected to the land conductor portion, and the differential line is connected to the land conductor portion side. One end of the signal line is a development part in which the distance between the pair of signal lines gradually increases, and the line width of the development part of each signal line is larger than the line width of the part other than the development part It is small.

本発明の配線基板は好ましくは、前記各信号線路の前記展開部の線路幅が前記ランド導体部に向かって漸次小さくなっていることを特徴とする。   The wiring board according to the present invention is preferably characterized in that the line width of the developed portion of each signal line gradually decreases toward the land conductor portion.

また、本発明の配線基板は好ましくは、前記絶縁基体は、主面または内部に前記差動線路の前記展開部以外の部位および前記展開部の一部と対向する接地導体が形成されていることを特徴とする。   In the wiring board of the present invention, it is preferable that the insulating base has a main surface or an inside thereof formed with a ground conductor facing a portion other than the developed portion of the differential line and a part of the developed portion. It is characterized by.

本発明の配線基板は、差動線路は、ランド導体部側の一端部が一対の信号線路同士の間の間隔が漸次広がっている展開部とされているとともに、各信号線路の展開部の線路幅が展開部以外の部位の線路幅よりも小さいことから、差動線路の展開部における信号線路の誘導成分が増加し、ランド導体部と同一面接地導体との間に発生する容量成分を相殺することができるため、差動線路の信号線路と差動貫通導体との接続部における特性インピーダンス低下による信号伝送の不連続性を抑制し、差動線路と差動貫通導体との接続部における高周波信号の反射損失を抑えることが可能となる。   In the wiring board according to the present invention, the differential line has a development portion in which one end portion on the land conductor portion side is gradually widened between the pair of signal lines, and the development portion of each signal line Since the width is smaller than the line width of the part other than the development part, the inductive component of the signal line in the development part of the differential line increases, and the capacitance component generated between the land conductor part and the ground conductor on the same plane is offset. Therefore, it is possible to suppress the discontinuity of signal transmission due to the characteristic impedance drop at the connection portion between the signal line of the differential line and the differential through conductor, and to reduce the high frequency at the connection portion between the differential line and the differential through conductor. Signal reflection loss can be suppressed.

本発明の配線基板は好ましくは、各信号線路の展開部の線路幅がランド導体部に向かって漸次小さくなっていることから、差動線路の展開部の線路幅と展開部以外の線路幅が段階的に異なることに伴う急激な特性インピーダンス変化を緩和し、高周波信号の反射損失をより抑えることが可能となる。   In the wiring board of the present invention, preferably, the line width of the development part of each signal line gradually decreases toward the land conductor part, so that the line width of the development part of the differential line and the line width other than the development part are It is possible to alleviate a sudden change in characteristic impedance due to the difference in stages, and to further suppress reflection loss of high-frequency signals.

また、本発明の配線基板は好ましくは、絶縁基体は、主面または内部に差動線路の展開部以外の部位および展開部の一部と対向する内層接地導体が形成されていることから、差動線路からの高周波信号(電磁波)の漏洩を有効に遮蔽し、高周波信号の透過損失を抑制することが可能となる。その結果、差動線路と差動貫通導体との接続部における高周波信号の反射損失を極めて小さくすることができるので、本発明の配線基板に搭載される半導体素子の高周波領域における作動性を非常に良好なものとすることができる。   Further, in the wiring board of the present invention, preferably, the insulating base is formed with an inner layer ground conductor facing a part other than the development part of the differential line and a part of the development part on the main surface or inside. It becomes possible to effectively shield the leakage of the high frequency signal (electromagnetic wave) from the moving line and suppress the transmission loss of the high frequency signal. As a result, the reflection loss of the high-frequency signal at the connection portion between the differential line and the differential through conductor can be extremely reduced, so that the operability in the high-frequency region of the semiconductor element mounted on the wiring board of the present invention is very high. It can be good.

本発明の配線基板について以下に詳細に説明する。図1は本発明の配線基板の実施の形態の一例を示す断面図であり、図2は図1の配線基板における差動配線8と差動貫通導体9の接続部の周辺部の要部拡大平面図である。また、図3は図1の配線基板における差動配線8の要部拡大断面図である。   The wiring board of the present invention will be described in detail below. FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention, and FIG. 2 is an enlarged view of a main part in the periphery of a connecting portion between a differential wiring 8 and a differential through conductor 9 in the wiring board of FIG. It is a top view. 3 is an enlarged cross-sectional view of a main part of the differential wiring 8 in the wiring board of FIG.

本発明の配線基板1においては、絶縁基板2を構成する絶縁層2a〜2fは基本的には同じ誘電率を有する絶縁材料で形成されている。絶縁層2c上には信号配線群3が形成され、絶縁層2b,2d上には信号配線群3に対向させて広面積の内層接地導体層4a,4cが形成されており、信号配線群3の各信号配線はストリップ線路構造を有している。内層接地導体層4a,4cは、配線基板1の仕様に応じて入れ換えて配置されることもある。   In the wiring substrate 1 of the present invention, the insulating layers 2a to 2f constituting the insulating substrate 2 are basically formed of an insulating material having the same dielectric constant. The signal wiring group 3 is formed on the insulating layer 2c, and the inner ground conductor layers 4a and 4c having large areas are formed on the insulating layers 2b and 2d so as to face the signal wiring group 3, and the signal wiring group 3 Each of the signal wirings has a stripline structure. The inner ground conductor layers 4a and 4c may be interchanged depending on the specifications of the wiring board 1.

また、信号配線群3の各信号配線の配線幅、および信号配線群3と内層接地導体層4a,4cとの間に介在する絶縁層2b,2cの厚みを設定することにより、信号配線群3の特性インピーダンスを制御することができるため、高周波信号の良好な伝送特性を有する信号配線群3を形成することができる。信号配線群3の特性インピーダンスは一般的には50Ωに設定される。なお、信号配線群3に含まれる複数の信号配線は、それぞれ異なる電気信号を伝送するものとしてもよい。   Further, by setting the wiring width of each signal wiring of the signal wiring group 3 and the thickness of the insulating layers 2b and 2c interposed between the signal wiring group 3 and the inner ground conductor layers 4a and 4c, the signal wiring group 3 Therefore, it is possible to form the signal wiring group 3 having good transmission characteristics for high-frequency signals. The characteristic impedance of the signal wiring group 3 is generally set to 50Ω. The plurality of signal wirings included in the signal wiring group 3 may transmit different electrical signals.

図1の例では、配線基板1上面には高速で動作するIC,LSI等の半導体集積回路素子や半導体レーザ(LD),フォトダイオード(PD)等の光半導体素子等の半導体素子5や電子部品が搭載され、錫−鉛(Sn−Pb)合金半田等の半田や金(Au)等から成る導体バンプ6および半導体素子5を接続するための電極パッド7を介して、差動線路8に電気的に接続されている。また、配線基板1下面には、半導体素子5に信号の入出力および電源供給を行なうための外部接続用電極11が形成されている。   In the example of FIG. 1, a semiconductor integrated circuit element such as an IC or LSI that operates at high speed, a semiconductor element 5 such as an optical semiconductor element such as a semiconductor laser (LD), a photodiode (PD), or an electronic component is formed on the upper surface of the wiring substrate 1. Is mounted on the differential line 8 via the electrode pads 7 for connecting the semiconductor bumps 6 and the conductor bumps 6 made of solder such as tin-lead (Sn—Pb) alloy solder or gold (Au). Connected. On the lower surface of the wiring substrate 1, external connection electrodes 11 for inputting / outputting signals to the semiconductor element 5 and supplying power are formed.

また、差動線路8は、絶縁層2cの上面に内層接地導体層4a,4cとの間に形成されたストリップ構造の一対の信号線路から成り、外部と信号の入出力を行なうために差動貫通導体9を介して外部接続用電極11に電気的に接続されており、また、差動貫通導体9、電極パッド7および錫−鉛合金半田等の半田や金等から成る導体バンプ6を介して半導体素子5の電極に電気的に接続されている。   The differential line 8 is composed of a pair of striped signal lines formed between the inner ground conductor layers 4a and 4c on the upper surface of the insulating layer 2c. It is electrically connected to the external connection electrode 11 through the through conductor 9, and through the differential through conductor 9, the electrode pad 7, and a conductor bump 6 made of solder such as tin-lead alloy solder or gold. Are electrically connected to the electrodes of the semiconductor element 5.

また、信号配線群3および差動線路8の構造は、信号配線群3に対向して電源配線層もしくは内層接地導体層を形成して成るマイクロストリップ線路構造の他に、信号配線群3の上下に電源配線層もしくは内層接地導体層を形成して成るストリップ線路構造、また信号配線群3の各信号配線に隣接して所定間隔をもって同一面電源配線層もしくは同一面接地導体層を形成して成るコプレーナ線路構造であってもよい。   Further, the signal wiring group 3 and the differential line 8 have a structure in addition to the microstrip line structure in which a power wiring layer or an inner ground conductor layer is formed opposite to the signal wiring group 3, A strip line structure formed by forming a power wiring layer or an inner ground conductor layer, and a single power wiring layer or a single ground conductor layer with a predetermined interval adjacent to each signal wiring of the signal wiring group 3 A coplanar line structure may be used.

また、配線基板1にチップ抵抗,薄膜抵抗,コイルインダクタ,クロスインダクタ,チップコンデンサまたは電解コンデンサ等を搭載して、電子回路モジュール等を構成してもよい。   Moreover, a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, an electrolytic capacitor, or the like may be mounted on the wiring board 1 to constitute an electronic circuit module or the like.

また、各絶縁層2a〜2fの平面視における形状は、正方形状や長方形状の他に、菱形状,六角形状または八角形状等の形状であってもよい。   Further, the shape of each of the insulating layers 2a to 2f in a plan view may be a rhombus shape, a hexagonal shape, an octagonal shape, or the like in addition to a square shape or a rectangular shape.

そして、このような本発明の配線基板1は、半導体素子収納用パッケージ等の電子部品収納用パッケージや電子部品搭載用基板、多数の半導体素子が搭載される所謂マルチチップモジュールやマルチチップパッケージ、あるいはマザーボード等として使用される。   Such a wiring board 1 of the present invention includes an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip package on which a large number of semiconductor elements are mounted, or Used as a motherboard.

本発明の配線基板1は、図2に示すように、差動貫通導体9の貫通導体9a,9bと差動線路8の信号線路8a,8bとは、差動線路8の信号線路8a,8b同士の間の間隔が漸次広がっている展開部14が一端に接続されたランド導体部13(13a,13b)を介して電気的に接続されている。そして、差動線路8が形成された絶縁層2bに差動線路8を取り囲むとともに差動貫通導体9との接続部を円形状に取り囲むように開口部12が形成された同一面接地導体4bとを具備し、差動線路8の展開部14の信号線路幅が展開部14以外の信号線路幅よりも小さいことから、展開部14の信号線路8a,8bの誘導成分が増加する。その結果、差動線路8と差動貫通導体9との接続部において、ランド導体部13と同一面接地導体4bとの間に発生する容量成分を増加した誘導成分によって相殺し、特性インピーダンス低下を抑制することによって、差動線路8と差動貫通導体9との接続部における高周波信号の反射損失を抑えることが可能となる。   As shown in FIG. 2, the wiring board 1 of the present invention includes the through conductors 9 a and 9 b of the differential through conductor 9 and the signal lines 8 a and 8 b of the differential line 8. The development part 14 where the space | interval between them spreads gradually is electrically connected via the land conductor part 13 (13a, 13b) connected to the end. The same-surface ground conductor 4b in which an opening 12 is formed so as to surround the differential line 8 in the insulating layer 2b in which the differential line 8 is formed and to surround the connection portion with the differential through conductor 9 in a circular shape. And the inductive component of the signal lines 8a and 8b of the development part 14 increases because the signal line width of the development part 14 of the differential line 8 is smaller than the signal line width other than the development part 14. As a result, in the connection portion between the differential line 8 and the differential through conductor 9, the capacitance component generated between the land conductor portion 13 and the same plane ground conductor 4b is canceled by the increased inductive component, and the characteristic impedance is reduced. By suppressing the reflection loss of the high frequency signal at the connection portion between the differential line 8 and the differential through conductor 9 can be suppressed.

また本発明において好ましくは、展開部14の各線路8a,8bの線路幅がランド導体部13に向かって漸次小さくなっていることから、展開部14の信号線路8a,8bの線路幅と展開部14以外の線路幅が段階的に異なることに伴う急激な特性インピーダンス変化を緩和し、高周波信号の反射損失をより抑えることが可能となる。   In the present invention, preferably, the line widths of the lines 8a and 8b of the development part 14 are gradually reduced toward the land conductor part 13, so that the line widths and development parts of the signal lines 8a and 8b of the development part 14 are reduced. It is possible to alleviate a sudden change in characteristic impedance caused by stepwise differences in line widths other than 14, and to further suppress reflection loss of high-frequency signals.

また本発明において好ましくは、絶縁基体2bは、図3に示されるように主面または内部に差動線路8の展開部14以外の部位および展開部14の一部と対向する(展開部14以外の部位から延出して展開部14の一部と対向する)内層接地導体4a,4cが形成されていることから、高周波信号(電磁波)の差動線路8からの漏洩を有効に遮蔽し、高周波信号の透過損失を抑制することが可能となる。   Preferably, in the present invention, the insulating base 2b is opposed to a part other than the development part 14 of the differential line 8 and a part of the development part 14 on the main surface or inside as shown in FIG. Since the inner-layer ground conductors 4a and 4c are formed so as to extend from the portion of the developing portion 14 and face a part of the developing portion 14, leakage of the high-frequency signal (electromagnetic wave) from the differential line 8 is effectively shielded. Signal transmission loss can be suppressed.

次に、図3に基き本発明における差動線路8について説明する。本発明の配線基板1において、絶縁層2a〜2fは例えばセラミックグリーンシート積層法によって形成される。この場合、絶縁層2a〜2fは、酸化アルミニウム質焼結体,窒化アルミニウム質焼結体,炭化珪素質焼結体,窒化珪素質焼結体,ムライト質焼結体またはガラスセラミックス等の無機絶縁材料から成る。また、絶縁層2a〜2fは、ポリイミド,エポキシ樹脂,フッ素樹脂,ポリノルボルネンまたはベンゾシクロブテン等の樹脂絶縁材料、あるいはセラミック粉末等の無機絶縁物粉末をエポキシ樹脂等の熱硬化性樹脂で結合して成る複合絶縁材料等の電気的な絶縁材料から成っていてもよい。   Next, the differential line 8 according to the present invention will be described with reference to FIG. In the wiring board 1 of the present invention, the insulating layers 2a to 2f are formed by, for example, a ceramic green sheet lamination method. In this case, the insulating layers 2a to 2f are made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Made of material. The insulating layers 2a to 2f are formed by bonding a resin insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder with a thermosetting resin such as epoxy resin. It may be made of an electrically insulating material such as a composite insulating material.

これらの絶縁層2a〜2fは以下のようにして作製される。絶縁層2a〜2fが例えば酸化アルミニウム質焼結体から成る場合、まず、酸化アルミニウム,酸化珪素,酸化カルシウムまたは酸化マグネシウム等の原料粉末に適当な有機バインダや溶剤等を添加混合して泥漿状となし、これをドクターブレード法等を採用してシート状となすことによってセラミックグリーンシートを得る。そして、セラミックグリーンシートに信号配線群3および各導体層4と成る金属ペーストを所定パターンに印刷塗布し、これらのセラミックグリーンシートを上下に積層し、最後にこの積層体を還元雰囲気中で約1600℃の温度で焼成することによって製作される。   These insulating layers 2a to 2f are manufactured as follows. When the insulating layers 2a to 2f are made of, for example, an aluminum oxide sintered body, first, an appropriate organic binder or solvent is added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide, or magnesium oxide to form a slurry. None, using a doctor blade method or the like to form a sheet, a ceramic green sheet is obtained. Then, a metal paste for forming the signal wiring group 3 and each conductor layer 4 is printed and applied to the ceramic green sheet in a predetermined pattern, and these ceramic green sheets are laminated on top and bottom, and finally, this laminate is about 1600 in a reducing atmosphere. It is manufactured by firing at a temperature of ° C.

また、絶縁層2a〜2fがエポキシ樹脂から成る場合、まず酸化アルミニウム質焼結体から成るセラミックスを混合した熱硬化性のエポキシ樹脂、あるいはガラス繊維を織り込んだ布にエポキシ樹脂を含浸させて成るガラスエポキシ樹脂等から成る絶縁層の上面に、樹脂前駆体をスピンコート法もしくはカーテンコート法等により被着させ、これを熱硬化処理することによって絶縁層を形成する。この絶縁層と、銅層を無電解めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィ技術を採用することによって形成して成る薄膜配線導体層とを交互に積層し、約170℃程度の温度で加熱硬化することによって製作される。   When the insulating layers 2a to 2f are made of an epoxy resin, first, a glass made by impregnating an epoxy resin into a thermosetting epoxy resin mixed with ceramics made of an aluminum oxide sintered body or a cloth woven with glass fibers. A resin precursor is deposited on the upper surface of an insulating layer made of an epoxy resin or the like by a spin coating method or a curtain coating method, and the insulating layer is formed by heat-curing the resin precursor. This insulating layer and a thin film wiring conductor layer formed by adopting a copper layer by employing a thin film forming technique such as an electroless plating method or a vapor deposition method and a photolithography technique are alternately laminated, and a temperature of about 170 ° C. It is manufactured by heating and curing.

これらの絶縁層2a〜2fの厚みは、使用する材料の特性に応じて、要求される仕様に対応する機械的強度や電気的特性等の条件を満たすように設定される。   The thicknesses of these insulating layers 2a to 2f are set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications according to the characteristics of the materials used.

また、信号配線群3、差動線路8および各導体層4は、例えばタングステン(W),モリブデン(Mo),モリブデン−マンガン(Mo−Mn),銅(Cu),銀(Ag)または銀−パラジウム(Ag−Pd)等の金属粉末メタライズ、あるいは銅(Cu),銀(Ag),ニッケル(Ni),クロム(Cr),チタン(Ti),金(Au)またはニオブ(Nb)やそれらの合金等の金属材料の薄膜等により形成すればよい。   The signal wiring group 3, the differential line 8, and each conductor layer 4 are made of, for example, tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag), or silver- Metal powder metallization such as palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au) or niobium (Nb) and their What is necessary is just to form by the thin film etc. of metal materials, such as an alloy.

具体的には、信号配線群3や内層接地導体層4をWの金属粉末のメタライズ層で形成する場合、W粉末に適当な有機バインダや溶剤等を添加混合して得た金属ペーストを、絶縁層2a〜2fと成るセラミックグリーンシートに所定のパターンで印刷塗布し、これをセラミックグリーンシートの積層体とともに焼成することによって形成することができる。   Specifically, when the signal wiring group 3 and the inner ground conductor layer 4 are formed of a metallized layer of W metal powder, the metal paste obtained by adding and mixing an appropriate organic binder or solvent to the W powder is insulated. It can be formed by printing and applying in a predetermined pattern on the ceramic green sheets to be the layers 2a to 2f, and firing this together with a laminate of ceramic green sheets.

また、信号配線群3や各導体層4を金属薄膜で形成する場合、例えばスパッタリング法,真空蒸着法またはメッキ法により金属薄膜を形成した後、フォトリソグラフィ法により所定の配線パターンに形成することによって形成できる。   Further, when the signal wiring group 3 and each conductor layer 4 are formed of a metal thin film, for example, after forming the metal thin film by a sputtering method, a vacuum evaporation method or a plating method, it is formed into a predetermined wiring pattern by a photolithography method. Can be formed.

このような配線基板1は、信号配線群3が配設されている絶縁層2a〜2fの誘電率に応じて、信号配線群3および差動線路8の信号線路8a,8bの配線幅,配線厚み,配線間隔を所望の値に設定することで、信号配線群3の各信号配線の特性インピーダンス値および差動線路8の特性インピーダンス値を所望の値とすることができる。   Such a wiring board 1 has wiring widths and wirings of the signal wiring group 3 and the signal lines 8a and 8b of the differential line 8 according to the dielectric constant of the insulating layers 2a to 2f on which the signal wiring group 3 is disposed. By setting the thickness and the wiring interval to desired values, the characteristic impedance value of each signal wiring of the signal wiring group 3 and the characteristic impedance value of the differential line 8 can be set to desired values.

なお、本発明は上記の実施の形態の例に限定されず、本発明の要旨を逸脱しない範囲内で種々の変更を行なうことは何ら差し支えない。例えば、差動線路8は配線基板1の主面に形成されていてもよい。さらに、差動貫通導体9が電気的に接続される二次実装部は、コネクタやワイヤボンディングパッド等で接続されていてもよい。また、差動貫通導体9は、配線基板1の異なる絶縁層に形成された差動線路8同士の接続に用いてもよい。   It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the differential line 8 may be formed on the main surface of the wiring board 1. Further, the secondary mounting portion to which the differential through conductor 9 is electrically connected may be connected by a connector, a wire bonding pad, or the like. Further, the differential through conductor 9 may be used to connect the differential lines 8 formed in different insulating layers of the wiring board 1.

本発明の図1の構成の配線基板1を以下のようにして作製した。酸化アルミニウム質焼結体から成る各厚みが0.14mmの絶縁層2a〜2fを、上述のセラミックグリーンシート積層法によって積層し形成することにより、絶縁基板2を作製した。このとき、信号配線群3、差動線路8、各導体層4、差動貫通導体9および接地貫通導体10を、上述のCuの金属粉末のメタライズ層で形成した。   The wiring board 1 having the configuration shown in FIG. 1 according to the present invention was manufactured as follows. The insulating substrate 2 was manufactured by laminating and forming the insulating layers 2a to 2f each made of an aluminum oxide sintered body having a thickness of 0.14 mm by the ceramic green sheet laminating method. At this time, the signal wiring group 3, the differential line 8, each conductor layer 4, the differential through conductor 9, and the ground through conductor 10 were formed of the metallized layer of the above-described Cu metal powder.

そして、この場合、図2に示すように、比誘電率が5.2の絶縁基板2bに、信号線路8a,8bのそれぞれの線路幅が65μm、信号線路8a,8b間の間隔が145μmであり、信号線路8a,8b間の間隔がランド導体部13の間隔に合わせて漸次広がっている展開部14を含む差動線路8を形成した。差動線路8の展開部14の信号線路8a,8bは、展開部14以外の部位の信号線路8a,8bとの成す角度が30度で展開され、ランド導体部13に接続されている。また、展開部14においては、信号線路8a,8bの線路幅は漸次細くなっており、ランド導体部13の一端に接続される部位の線路幅は35μmで形成した。   In this case, as shown in FIG. 2, on the insulating substrate 2b having a relative dielectric constant of 5.2, each of the signal lines 8a and 8b has a line width of 65 μm and a distance between the signal lines 8a and 8b is 145 μm. Thus, the differential line 8 including the expanded portion 14 in which the interval between the signal lines 8a and 8b gradually increases in accordance with the interval of the land conductor portion 13 is formed. The signal lines 8 a and 8 b of the development portion 14 of the differential line 8 are developed at an angle of 30 degrees with the signal lines 8 a and 8 b in portions other than the development portion 14 and are connected to the land conductor portion 13. Further, in the developed part 14, the line widths of the signal lines 8a and 8b are gradually narrowed, and the line width of the part connected to one end of the land conductor part 13 is 35 μm.

また、各直径が50μmで互いの間隔が0.3mmの一対の貫通導体9a,9bから成る差動貫通導体9を平面視で同心円状に取り囲むように、各直径が50μmで互いの間隔が0.15mmの6本の接地貫通導体10、および内層接地導体層4aと差動貫通導体9を絶縁する開口部12を形成した。開口部12の形状は、それぞれ貫通導体9a,9bを中心とする各直径150μmの2つの円を、それらの円の接線で結んだ楕円形状(長円形状)である。差動線路8と差動貫通導体9は直径100μmのランド導体部13を介して接続されている。   Further, each diameter is 50 μm and the distance between each other is 0 so as to surround the differential through conductor 9 composed of a pair of the through conductors 9 a and 9 b each having a diameter of 50 μm and a distance of 0.3 mm in a plan view. The six grounding through conductors 10 of 15 mm and the opening 12 that insulates the inner grounding conductor layer 4a from the differential through conductor 9 were formed. The shape of the opening 12 is an elliptical shape (oval shape) in which two circles each having a diameter of 150 μm centering on the through conductors 9a and 9b are connected by tangent lines of the circles. The differential line 8 and the differential through conductor 9 are connected via a land conductor portion 13 having a diameter of 100 μm.

さらに、高周波信号をシールドするために、同一面接地導体4bは差動線路8の周囲を取り囲むとともに、差動線路8と差動貫通導体9との接続部を円形状に取り囲むように形成されている。その接続部を円形状に取り囲む部分は、それぞれランド導体部13a,13bを中心とする各直径150μmの2つの円を、それらの円の接線で結んだ楕円形状(長円形状)で形成されている。   Further, in order to shield the high frequency signal, the same-surface ground conductor 4b surrounds the periphery of the differential line 8 and is formed so as to surround the connection portion between the differential line 8 and the differential through conductor 9 in a circular shape. Yes. The portion surrounding the connecting portion in a circular shape is formed in an elliptical shape (oval shape) in which two circles each having a diameter of 150 μm centering on the land conductor portions 13a and 13b are connected by tangent lines of the circles. Yes.

上記構成の差動線路8について、40GHzの高周波信号を貫通導体8a,8bに位相差180度で入力したところ、差動線路8と差動貫通導体9との接続部における信号線路の不連続性を小さくできるため、高周波信号の反射損失を抑えることが可能となった。即ち、差動線路8と差動貫通導体9との接続部における高周波信号の反射レベルは−42dB程度となり、きわめて小さい値であった。   When the high-frequency signal of 40 GHz is input to the through conductors 8a and 8b with a phase difference of 180 degrees with respect to the differential line 8 having the above configuration, the signal line discontinuity at the connection portion between the differential line 8 and the differential through conductor 9 is obtained. Therefore, the reflection loss of high frequency signals can be suppressed. That is, the reflection level of the high-frequency signal at the connection portion between the differential line 8 and the differential through conductor 9 is about −42 dB, which is a very small value.

また、比較例として、差動線路8の展開部14において信号線路8a,8bの線路幅を65μmと一定として形成した配線基板1においては、差動貫通導体9と差動線路8との接続部における高周波信号の反射レベルは−26dB程度と大きくなった。   As a comparative example, in the wiring substrate 1 in which the line widths of the signal lines 8 a and 8 b are fixed to 65 μm in the development part 14 of the differential line 8, the connection part between the differential through conductor 9 and the differential line 8. The reflection level of the high-frequency signal was as high as about -26 dB.

本発明の配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the wiring board of this invention. 図1の配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the wiring board of FIG. 図1の配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the wiring board of FIG. 従来の配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the conventional wiring board. 従来の配線基板の一例の部分拡大断面図である。It is a partial expanded sectional view of an example of the conventional wiring board. 従来の配線基板の一例の部分拡大平面図である。It is a partial enlarged plan view of an example of a conventional wiring board. 従来の配線基板の一例の要部拡大平面図である。It is a principal part enlarged plan view of an example of the conventional wiring board.

符号の説明Explanation of symbols

1・・・配線基板
2・・・絶縁基板
2a〜2f・・・絶縁層
5・・・半導体素子
8・・・差動線路
8a,8b・・・一対の信号線路
9・・・差動貫通導体
9a,9b・・・貫通導体
12・・・開口部
13・・・ランド導体部
14・・・展開部
DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Insulating board 2a-2f ... Insulating layer 5 ... Semiconductor element 8 ... Differential line 8a, 8b ... A pair of signal line 9 ... Differential penetration Conductors 9a, 9b ... through conductor 12 ... opening 13 ... land conductor 14 ... deployed part

Claims (3)

絶縁基体の主面または内部に形成された互いに平行な一対の信号線路から成る差動線路と、該差動線路を所定間隔をもって取り囲むように形成された同一面接地導体と、前記各信号線路の一端に設けられたランド導体部と、該ランド導体部に一端が電気的に接続された貫通導体とを具備しており、前記差動線路は、前記ランド導体部側の一端部が前記一対の信号線路同士の間の間隔が漸次広がっている展開部とされているとともに、前記各信号線路の前記展開部の線路幅が前記展開部以外の部位の線路幅よりも小さいことを特徴とする配線基板。 A differential line composed of a pair of parallel signal lines formed on the main surface or inside of the insulating base, a coplanar ground conductor formed so as to surround the differential line at a predetermined interval, and each of the signal lines A land conductor portion provided at one end; and a through conductor having one end electrically connected to the land conductor portion, and the differential line has one end portion on the land conductor portion side of the pair of land conductor portions. The wiring is characterized in that the interval between the signal lines is gradually expanded, and the line width of the expansion portion of each signal line is smaller than the line width of the portion other than the expansion portion. substrate. 前記各信号線路の前記展開部の線路幅が前記ランド導体部に向かって漸次小さくなっていることを特徴とする請求項1記載の配線基板。 The wiring board according to claim 1, wherein a line width of the development portion of each signal line gradually decreases toward the land conductor portion. 前記絶縁基体は、主面または内部に前記差動線路の前記展開部以外の部位および前記展開部の一部と対向する内層接地導体が形成されていることを特徴とする請求項1または請求項2記載の配線基板。 The inner surface ground conductor which opposes the site | part other than the said expansion | deployment part of the said differential line and a part of said expansion | deployment part is formed in the said insulation base | substrate or the inside, The Claim 1 or Claim characterized by the above-mentioned. 2. The wiring board according to 2.
JP2004275521A 2004-09-22 2004-09-22 Wiring board Expired - Fee Related JP4601369B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021511A (en) * 2007-07-13 2009-01-29 Ricoh Co Ltd Printed wiring board, and electronic device
JP2009212400A (en) * 2008-03-05 2009-09-17 Ngk Spark Plug Co Ltd High-frequency package
JP2011138845A (en) * 2009-12-27 2011-07-14 Kyocer Slc Technologies Corp Wiring board
CN112349668A (en) * 2020-09-28 2021-02-09 中国电子科技集团公司第二十九研究所 Broadband radio frequency module structure adopting radio frequency motherboard and design method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349192A (en) * 1999-06-07 2000-12-15 Canon Inc Semiconductor integrated circuit and printed wiring board
JP2002190541A (en) * 2000-12-22 2002-07-05 Kyocera Corp Package for high-frequency circuit
JP2004006789A (en) * 2002-04-04 2004-01-08 Seiko Epson Corp Printed wiring board
JP2004253746A (en) * 2002-12-26 2004-09-09 Kyocera Corp Wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349192A (en) * 1999-06-07 2000-12-15 Canon Inc Semiconductor integrated circuit and printed wiring board
JP2002190541A (en) * 2000-12-22 2002-07-05 Kyocera Corp Package for high-frequency circuit
JP2004006789A (en) * 2002-04-04 2004-01-08 Seiko Epson Corp Printed wiring board
JP2004253746A (en) * 2002-12-26 2004-09-09 Kyocera Corp Wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021511A (en) * 2007-07-13 2009-01-29 Ricoh Co Ltd Printed wiring board, and electronic device
JP2009212400A (en) * 2008-03-05 2009-09-17 Ngk Spark Plug Co Ltd High-frequency package
JP2011138845A (en) * 2009-12-27 2011-07-14 Kyocer Slc Technologies Corp Wiring board
CN112349668A (en) * 2020-09-28 2021-02-09 中国电子科技集团公司第二十九研究所 Broadband radio frequency module structure adopting radio frequency motherboard and design method thereof

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