KR101522786B1 - Multilayered substrate and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a multilayer board and a method for manufacturing a multilayer board, wherein a multilayer board including a plurality of wiring layers is provided with a reinforcing layer for reducing warpage on the outermost sides of both sides of the multilayer board, By optimizing the wiring pattern in accordance with the formed method, it is possible to improve the manufacturing efficiency and to reduce the warpage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multi-

The present invention relates to a multilayer substrate and a method of manufacturing a multilayer substrate.

Called multi-layer substrate technologies for forming a plurality of wiring layers on a printed circuit board (PCB) have been developed in order to meet the trend of weight reduction, miniaturization, high speed, versatility, and high performance of electronic devices. Further, Technology for embedding electronic components such as devices in a multilayer substrate has also been developed.

For example, Patent Document 1 discloses a printed circuit board made of a plurality of layers by inserting an electronic component into a cavity and a manufacturing method thereof.

On the other hand, one of the important tasks in the multi-layer substrate field is to allow the built-in electronic component to efficiently transmit and receive signals including voltage or current to an external circuit or other devices.

In addition, in recent years, as the performance of electronic parts has become higher and the size and thickness of electronic parts and electronic parts built-in boards have been increased, a small electronic component is built in a thinner and narrower substrate, It is essential that the improvement of the integration degree is also accompanied.

On the other hand, as the electronic component built-in substrate becomes thinner, the warpage of the board becomes a serious problem. Such warpage phenomenon is also called warpage. However, warpage is getting worse as the electronic component built-up substrate is composed of various materials having different thermal expansion coefficients.

In order to reduce such warpage, conventionally, a method of forming an insulating layer using a material having high rigidity has been applied. However, when the insulating layer is provided only by a material having high rigidity, the surface of the insulating layer is rough, There is a limit in improving the degree of integration of the device.

Patent Document 2 discloses a technique in which an electronic component is embedded in one side of a core substrate and a circuit pattern layer and an insulation layer are built up only in a single direction in order to secure mechanical rigidity. Patent Document 3 A capacitor is disposed at the center of the core substrate and a circuit pattern layer and an insulating layer are built up in both directions.

However, conventional technologies including Patent Documents 1 to 4 uniformly apply structures and methods that can be implemented to all electronic components at the level of technology at the time of development, It is difficult to improve the integration degree of the wiring pattern while reducing the warpage phenomenon.

United States Patent Application Publication No. 2012-0006469 U.S. Patent No. 5,353,498 Japanese Patent Application Laid-Open No. 2000-261124 Japanese Patent Application Laid-Open No. 1992-283987

It is an object of the present invention, which is created to solve the above problems, to provide a technique capable of reducing warpage.

It is another object of the present invention to provide a technique capable of reducing warpage while improving the degree of integration of wiring patterns in consideration of the characteristics of electronic parts.

According to an aspect of the present invention, there is provided a multi-layer substrate including a plurality of wiring layers, wherein the multi-layer substrate includes a plurality of reinforcing layers for reducing warpage, Respectively.

At this time, it is preferable that the reinforcing layer is made of a material having a thermal expansion coefficient of 11 ppm / ° C or less.

The reinforcing layer is preferably made of a material having an elastic modulus of 25 GPa or more.

The reinforcing layer may be made of a glass material.

The reinforcing layer provided on the outermost periphery of the multilayer board is a first reinforcing layer and the reinforcing layer provided on the outermost periphery of the other surface of the multilayer board is a second reinforcing layer, A first insulating layer having a cavity into which the first insulating layer is inserted may be further included between the first and second reinforcing layers.

Further, the solder resist may cover at least a part of at least one of the one surface of the first reinforcing layer and the other surface of the second reinforcing layer.

The first reinforcing layer is provided on the lower surface of the first reinforcing layer and the second insulating layer contacting the third circuit pattern layer is provided between the first reinforcing layer and the first insulating layer, As shown in FIG.

The semiconductor device may further include a third insulating layer disposed between the first insulating layer and the second reinforcing layer, the fourth insulating layer having a fourth circuit pattern layer contacting the second reinforcing layer.

The third insulating layer may include a third upper insulating layer contacting the surfaces of the first insulating layer and the electronic component and having a fifth circuit pattern layer on the lower surface thereof; And a third lower insulating layer having one side in contact with the fourth circuit pattern layer and the second reinforcing layer.

The method of claim 1, further comprising: passing through at least one circuit pattern of the third circuit pattern layer and at least one circuit pattern on the fifth circuit pattern layer through the second insulating layer, the first insulating layer, and the third upper insulating layer The fifth vias may be formed.

At this time, it may further include a third via which passes through the third upper insulating layer and directly connects at least one circuit pattern of the fifth circuit pattern layer and the external electrode.

A method of manufacturing a multilayered board according to an embodiment of the present invention is a method of manufacturing a multilayered board including at least one of the following conditions: a condition that a thermal expansion coefficient is 11 ppm / 占 폚 or less and a condition that an elastic modulus is 25 GPa or more And forming a reinforcing layer made of a satisfactory material.

At this time, the reinforcing layer may be formed of a glass material.

According to another aspect of the present invention, there is provided a method of manufacturing a multilayer board, including: mounting an electronic component having an external electrode on a first reinforcing layer having a third circuit pattern layer on a first surface thereof; Forming a second insulating layer covering the third circuit pattern layer and the first reinforcing layer and contacting the side surface of the electronic component on the first reinforcing layer; Layering a first insulating layer having a cavity into which at least a part of the electronic component is inserted, on the second insulating layer; Forming a third upper insulating layer on the first insulating layer to cover the electronic component and the first insulating layer and fill the gap between the cavity and the electronic component; Forming a fifth circuit pattern layer on the third upper insulating layer in which at least one circuit pattern is directly connected to the external electrode by a third via; Forming a third lower insulating layer covering the fifth circuit pattern layer and the third upper insulating layer on the third upper insulating layer; Forming a fourth circuit pattern layer on the third lower insulating layer such that at least one circuit pattern is directly connected to at least one circuit pattern of the fifth circuit pattern layer by a fourth via; And forming a second reinforcing layer covering the fourth circuit pattern layer and the third lower insulating layer on the third lower insulating layer, wherein the first reinforcing layer and the second reinforcing layer are formed on the multilayer substrate It can be to reduce warfare.

At this time, the first reinforcing layer and the second reinforcing layer may be made of a material satisfying at least one of the following conditions: a coefficient of thermal expansion is 11 ppm / ° C or less and a modulus of elasticity is 25 GPa or more.

The reinforcing layer may be formed of a glass material.

The first reinforcing layer is formed on the upper surface and the lower surface of the detent core respectively. The first reinforcing layer is formed on the upper surface and the lower surface of the detent core, and is separated from the detent core after the multi- .

The third upper insulating layer and the third lower insulating layer may be formed by curing a fluid synthetic resin having no core.

The second insulating layer may be formed by curing a fluid synthetic resin containing a core material.

The step of forming the fifth circuit pattern layer on the third upper insulating layer may include forming at least one circuit pattern of the fifth circuit pattern layer on at least one circuit pattern of the third circuit pattern layer, Lt; RTI ID = 0.0 > 5 < / RTI > vias.

The present invention thus constituted provides a beneficial effect that the warpage of the multilayer substrate can be reduced.

Further, the present invention provides a beneficial effect that the manufacturing efficiency can be improved and the warpage can be reduced by optimizing the wiring pattern according to the manner in which the external electrode is formed on the electronic component.

1 is a cross-sectional view schematically showing a multilayer substrate according to an embodiment of the present invention.
2 is a cross-sectional view schematically showing a multilayer substrate according to another embodiment of the present invention.
3 is a cross-sectional view schematically showing one modification of Fig.
4 is a cross-sectional view schematically showing another modification of Fig.
FIG. 5 is a graph schematically showing a result of measurement of warpage in a multi-layered substrate according to an embodiment of the present invention while varying the coefficient of thermal expansion and the modulus of elasticity of the reinforcing layer.
6A is a cross-sectional view illustrating a method of fabricating a multilayered substrate according to an embodiment of the present invention. FIG. 6A is a view illustrating a state where a detent core having a first metal layer is provided, FIG. 6B is a cross- 6C shows a state in which the third circuit pattern layer is formed by patterning the third metal layer, FIG. 6D shows a state in which the electronic components are coupled onto the third circuit pattern layer, FIG. 6E shows a state in which the second insulating layer, FIG. 6F shows a state in which the third via, the fifth via and the fifth circuit pattern layer are formed, FIG. 6G shows a state in which the third lower insulating layer, the fourth circuit pattern layer, and the third upper insulating layer are formed, Fig. 6H is a state in which the detent core is removed, Fig. 6I is a state in which a first circuit pattern layer and a second circuit pattern layer are formed, Fig. 6J is a state in which a solder resist is formed, Are schematically illustrated respectively.
7A to 7K are cross-sectional views schematically showing a method of manufacturing a multilayered substrate according to another embodiment of the present invention, wherein FIG. 7A shows a state in which a detent core having a first metal layer is provided on both sides, FIG. FIG. 7C shows a state in which the third circuit layer is formed by patterning the third metal layer above and below the recessed core, FIG. 7D shows a state in which the third metal layer is formed above and below the recessed core, 7E shows a state in which a second insulating layer, a first insulating layer, and a third upper insulating layer are formed above and below the detent core, FIG. 7F shows a state in which the electronic component is coupled to the lower third circuit pattern layer, FIG. 7G shows a state in which the third via insulating layer, the fourth circuit pattern layer, and the second reinforcing layer are formed on the upper and lower sides of the detent core, 7H shows a state in which the detent core is removed 7I is a state in which a first circuit pattern layer and a second circuit pattern layer are formed under the detent core, FIG. 7J is a state in which a solder resist is formed, and FIG. 7K is a state in which a solder ball is formed, FIG.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terms used herein are intended to illustrate the embodiments and are not intended to limit the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is to be understood that the terms 'comprise', and / or 'comprising' as used herein may be used to refer to the presence or absence of one or more other components, steps, operations, and / Or additions.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction and the detailed description of known features and techniques may be omitted so as to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements of the drawings are not necessarily drawn to scale. For example, to facilitate understanding of embodiments of the present invention, the dimensions of some of the elements in the figures may be exaggerated relative to other elements. Like reference numerals in different drawings denote like elements, and like reference numbers may indicate similar elements, although not necessarily.

The terms "first", "second", "third", and "fourth" in the specification and claims are used to distinguish between similar components, if any, Or to describe the sequence of occurrences. It will be understood that the terminology used is such that the embodiments of the invention described herein are compatible under suitable circumstances to, for example, operate in a sequence other than those shown or described herein. Likewise, where the method is described as including a series of steps, the order of such steps presented herein is not necessarily the order in which such steps may be performed, any of the described steps may be omitted and / Any other step not described will be additive to the method.

Terms such as "left", "right", "front", "back", "upper", "bottom", "above", "below" And does not necessarily describe an unchanging relative position. It will be understood that the terminology used is intended to be interchangeable with the embodiments of the invention described herein, under suitable circumstances, for example, so as to be able to operate in a different direction than that shown or described herein. The term "connected" as used herein is defined as being directly or indirectly connected in an electrically or non-electrical manner. Objects described herein as "adjacent" may be in physical contact with one another, in close proximity to one another, or in the same general range or region as are appropriate for the context in which the phrase is used. The presence of the phrase "in one embodiment" herein means the same embodiment, although not necessarily.

Hereinafter, the configuration and operation effects of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a cross-sectional view schematically showing a multilayer substrate 100 according to an embodiment of the present invention.

Referring to FIG. 1, a multilayer substrate 100 according to an embodiment of the present invention includes a multilayer substrate 100 having a plurality of wiring layers, and a reinforcing layer 110 is formed on the outermost layer on one side and the other side.

That is, the first reinforcing layer 111 may be provided on the outermost layer of the multilayer substrate 100, and the second reinforcing layer 115 may be provided on the outermost layer of the multilayer substrate 100.

At least one layer of the circuit pattern layer and the insulating layer may be provided between the first reinforcing layer 111 and the second reinforcing layer 115.

2 is a cross-sectional view schematically showing a multilayer substrate 200 according to another embodiment of the present invention.

Referring to FIG. 2, the electronic component 10 may be embedded in the multilayer substrate 200 according to the present embodiment.

The electronic component 10 may be an active element such as a semiconductor chip or a passive element such as a capacitor. An external electrode 11 (or external terminal) for electrical connection with other devices may be provided outside the electronic component 10 .

At this time, the electronic component 10 may be located inside the first insulating layer 120 provided between the first reinforcing layer 111 and the second reinforcing layer 115. Particularly, the cavity 121 is provided in the first insulating layer 120, and at least a part of the electronic component 10 can be inserted into the cavity 121.

In addition, a second insulating layer 130 may be further provided between the first insulating layer 120 and the first reinforcing layer 111.

Here, the third circuit pattern layer P3 may be provided on the lower surface of the first reinforcing layer 111. As shown in the figure, the circuit pattern of the third circuit pattern layer P3 includes the electronic component 10 At this time, an adhesive 12 may be provided between the electronic component 10 and the circuit pattern to contribute to fixation of the electronic component 10.

In addition, a third insulating layer 140 may be further provided between the first insulating layer 120 and the second reinforcing layer 115.

Here, the third insulating layer 140 may include a third upper insulating layer 141 and a third lower insulating layer 142.

The third upper insulating layer 141 may cover the lower surface of the first insulating layer 120 and the electronic component 10 and the fifth circuit pattern layer P5 may be formed on the lower surface of the third upper insulating layer 141. [ .

The third lower insulating layer 142 may cover the lower surface of the third upper insulating layer 141 and the fifth circuit pattern layer P5 and the lower surface of the third lower insulating layer 142 may cover the fourth A circuit pattern layer P4 may be provided.

The external electrode 11 may be provided on the lower surface of the electronic component 10. A third upper insulating layer 141 may be formed between any one of the circuit patterns of the fifth circuit pattern layer P5 and the external electrode 11. [ The third vias V3 may be directly connected.

Any circuit pattern of the fifth circuit pattern layer P5 and the circuit pattern of the fourth circuit pattern layer P4 may be directly formed by the fourth vias V4 passing through the third lower insulating layer 142. [ Can be connected.

Here, the fifth circuit pattern layer P5 and the fifth circuit pattern layer P5 are formed by the fifth via-pattern layer P5 and the fourth via V4 directly connected to the external electrode 11 of the electronic component 10 by the third via V3. The fourth circuit pattern layer P4 directly connected to the first circuit pattern layer may require a higher wiring density than other circuit pattern layers.

In general, insulating materials reinforced with rigidity are used as a core material to reduce warpage. However, the circuit pattern formed on the surface of the insulating layer including the core has a limitation in miniaturizing the line width and the pitch. In addition, even when a via is formed in the insulating layer including the core material, there is a limit in reducing the via diameter.

Therefore, in implementing the third upper insulating layer 141 and the third lower insulating layer 142, it is preferable to apply a material that does not include a core material such as glass fiber.

The second reinforcing layer 115 may be provided on the lower surface of the second circuit pattern layer P2 and any one of the circuit patterns of the second circuit pattern layer P2 and the fourth circuit pattern layer P4 The circuit pattern can be directly connected by the second via V2 passing through the second stiffening layer 115. [

The first circuit pattern layer P1 may be formed on the upper surface of the first reinforcing layer 111 and the first circuit pattern layer P1 may be formed on either the first circuit pattern layer P1 or the third circuit pattern layer P3 A circuit pattern may be directly connected by the first via V1 passing through the first reinforcing layer 111. [

Any one of the circuit patterns of the fifth circuit pattern layer P5 and the third circuit pattern layer P3 may be formed on the third upper insulating layer 141, the first insulating layer 120, May be directly connected by fifth vias (V5) passing through layer (130).

The electronic components incorporated in the multilayer substrate do not all have the same complexity, and the external electrodes of the electronic component package may be formed to face in a specific direction. Therefore, in this case, it is possible to improve the manufacturing efficiency of the multilayer substrate by maintaining the complicated wiring only in the direction in which the external electrodes are oriented.

2, in the case where the external electrode 11 is formed only on the lower surface of the electronic component 10, in the direction of the third insulating layer 140 in which the external electrode 11 is formed, 11 to the outside of the multilayer substrate 100, it is necessary that relatively fine patterns are arranged with a relatively high degree of integration.

As described above, the wiring density is high in one direction and relatively low in the other direction with respect to the horizontal central axis of the multilayer substrate 200, so that the manufacturing efficiency of the multilayer substrate 200 can be improved.

However, if the degree of circuit integration of the multilayer board 200 is asymmetrically formed, the warpage phenomenon may be intensified. In the present invention, since the first reinforcing layer 111 and the second reinforcing layer 115 are provided, So that the phenomenon can be reduced.

2, the third circuit pattern layer P3 located in the direction of the top surface of the electronic component 10 in which the external electrodes 11 are not formed may be a fifth circuit pattern layer P5, The wiring density can be relatively low as compared with the fourth circuit pattern layer P4, and the pattern width can be less fine.

On the other hand, an insulating material including a core material such as a glass fiber has a high rigidity and may be advantageous in reducing warpage. However, as the surface roughness of the core material increases, there is a limit in forming a fine pattern or reducing the pattern pitch.

On the other hand, an insulating material not including a core material such as a glass fiber can minutely reduce the surface pattern and further reduce the pattern pitch, but has a disadvantage in that the rigidity is insufficient and the warpage is increased.

In consideration of these points, in the multi-layer substrate 200 according to an embodiment of the present invention, the third insulating layer 140 formed under the external electrode 11 of the electronic substrate has a circuit pattern with a relatively high wiring density And the second insulating layer 130 formed above the electronic component 10 is realized as a fluid synthetic resin including a core material so as to have a relatively high rigidity.

In addition, the first reinforcing layer 111 and the second reinforcing layer 115 are disposed symmetrically with respect to the outermost layer of the multi-layer substrate 100, thereby further reducing the warping phenomenon.

2, a solder resist SR covering the first reinforcing layer 111 and the first circuit pattern layer P1, the second reinforcing layer 115, and the second circuit pattern layer P2 is further provided . A solder ball SB which is in contact with the first circuit pattern layer P1 and the second circuit pattern layer P2 and is exposed to the outside of the solder resist SR may be further provided.

The solder resist SR may be optionally provided on the multilayer substrate 200 as required. Therefore, it should be understood that the expression of the outermost two-sided side of the multilayer substrate 200 used in this specification means the outermost side in the state excluding the solder resist SR.

Figures 3 and 4 are cross-sectional views schematically illustrating the modifications of Figure 2.

3 and 4, when efficient heat dissipation of the electronic component 10 is required, the heat-dissipating adhesive 312 is applied to the upper surface of the electronic component 10, and then the third circuit pattern layer P3 And a sixth via (V6) is provided between the circuit pattern and the circuit pattern of the first circuit pattern layer (P1) so that the heat generated in the electronic component (10) 312 and the circuit pattern of the third circuit pattern layer P3 and the circuit patterns of the sixth via pattern V6 and the first circuit pattern layer P1, have.

In the case where the electronic component 410 is a capacitor such as an MLCC having two external electrodes 411, the first additional circuit pattern P3 provided in the third circuit pattern layer P3 and electrically insulated from each other -1 and the second additional circuit pattern P3-2 and the first additional circuit pattern P3-1 is in contact with one external electrode 411 of the electronic component 410, (P3-2) can be brought into contact with other external electrodes.

At this time, a non-conductive adhesive 412 is provided between the remaining part of the electronic component 410 except for the external electrode 411 and the first additional circuit pattern P3-1 and the second additional circuit pattern P3-2 The electronic component 410 can be stably fixed.

Each of the first additional circuit pattern P3-1 and the second additional circuit pattern P3-2 may be electrically connected to any one of the first circuit pattern layers P1 and the other circuit patterns via the vias have.

5 is a graph schematically showing a result of measuring the warpage of the multilayer substrate 200 according to an embodiment of the present invention while varying the coefficient of thermal expansion and the modulus of elasticity of the reinforcing layer 110. FIG.

5, the thickness of the first reinforcing layer 111 is 20-25um, the thickness of the second insulating layer 130 is 10-20um, the thickness of the first insulating layer Layer substrate 200 having a total thickness of 14 mm x 14 mm and a thickness of 40-50 mm of the third insulating layer 140 and a thickness of 20-25 mm of the second reinforcing layer 115, Lt; 0 > C and then cooled to room temperature to measure the distance from the lowest point to the highest point of one side of the multilayer substrate 200. [

In FIG. 5, the actual data is indicated by rhombus, and the data expressed in a linear form shows the result of the simulation.

As shown in FIG. 5, when the thermal expansion coefficient of the reinforcing layer 110 is 11 ppm / ° C or lower, or when the modulus of elasticity is 25 GPa or higher, warpage below the reference value is generated.

It should be noted that the reference value at this time may vary depending on the above-described experimental conditions and the allowable range of warpage required in a product to which the multilayer board 200 is applied.

On the other hand, as a material satisfying such a condition, a glass material can be mentioned, and therefore, the first reinforcing layer 111 and the second reinforcing layer 115 can be realized with a glass material.

The glass material generally has a modulus of elasticity of 40 to 60 Gpa and a coefficient of thermal expansion of 5 ppm / ° C or less. Thus, by realizing the first reinforcing layer 111 and the second reinforcing layer 115 with a glass material, It can be remarkably reduced.

6A to 6K are process cross-sectional views schematically showing a method of manufacturing a multilayer substrate according to an embodiment of the present invention.

First, referring to FIG. 6A, a detent core DC provided with a first metal layer P1 'is provided.

Next, referring to FIG. 6B, a first reinforcing layer 111 is formed on the upper surface of the first metal layer P1 '. At this time, the first reinforcing layer 111 may be bonded on the first metal layer P1 'with the third metal layer P3' provided on the upper surface thereof, but the present invention is not limited thereto.

6C and 6D, a third circuit pattern layer P3 is formed by patterning the third metal layer P3 ', an electronic component 10 is formed on the third circuit pattern layer P3, . Here, the adhesive 12 is provided on the lower surface of the electronic component 10, so that the electronic component 10 can be stably fixed.

6E, a second insulating layer 130 covering the third circuit pattern layer P3 and the first reinforcing layer 111 can be formed. At this time, the second insulation layer 130 may be formed by applying a fluid synthetic resin containing a core material and curing the coating. At this time, the electronic component 10 can be more stably fixed by the second insulating layer 130.

Next, a first insulating layer 120 having a cavity 121 may be coupled to the second insulating layer 130.

In addition, a third upper insulating layer 141 covering the first insulating layer 120 and the electronic component 10 may be formed. Here, since the third upper insulating layer 141 is formed, the electronic component 10 can be completely sealed inside the substrate.

6F, a fifth via V5 passing through the third upper insulating layer 141, the first insulating layer 120 and the second insulating layer 130, and a third upper insulating layer 141 The third vias V3 may be formed to penetrate the first circuit pattern layer P5 and the fifth circuit pattern layer P5. At this time, the third via V3 directly connects one of the circuit patterns of the fifth circuit pattern layer P5 and the external electrode 11, and the fifth via V5 connects the other circuit pattern of the fifth circuit pattern layer P5 It may be a direct connection of any one circuit pattern of the third circuit pattern layer P3 with one circuit pattern.

Next, referring to FIG. 6G, a third lower insulating layer 142 is formed on the third upper insulating layer 141, a fourth via pattern V4 and a fourth circuit pattern layer P4 are formed And the second reinforcing layer 115 can be formed.

Referring to FIG. 6H, the detent core DC coupled to the lower surface of the first metal layer P1 'can be removed. Referring to FIG. 6I, the first metal layer P1' and the second metal layer P1 ' The first circuit pattern layer P1 and the second circuit pattern layer P2 can be formed on the first circuit pattern layer P2 '.

Next, referring to FIGS. 6J and 6K, the solder resist SR may be formed on the first circuit pattern layer P1 and the second circuit pattern layer P2, and then the solder ball SB may be formed.

As described above, the first reinforcing layer 111 and the second reinforcing layer 115 can be reduced in the warpage by a material having a coefficient of thermal expansion of less than 11 ppm / ° C or an elastic modulus of 25 GPa or more, Glass materials can be used.

7A to 7K are process cross-sectional views schematically showing a method of manufacturing a multilayer substrate 100 according to another embodiment of the present invention. Unlike the method described in Figs. 6A to 6K described above, on both surfaces of a detent core DC By forming each layer symmetrically, it is more advantageous to reduce warpage.

The remaining parts are similar to those described in the above-mentioned embodiment, and a duplicate description will be omitted.

10: Electronic component 11: External electrode
12: adhesive 100, 200, 300: multi-layer substrate
110: reinforcing layer 111: first reinforcing layer
115: second reinforcing layer 120: first insulating layer
121: cavity
130: second insulation layer 140: third insulation layer
141: third upper insulating layer 142: third lower insulating layer
P1: first circuit pattern layer P2: second circuit pattern layer
P3: third circuit pattern layer P4: fourth circuit pattern layer
P5: fifth circuit pattern layer P1 ': first metal layer
P2 ': second metal layer P3': third metal layer
V1: First Via V2: Second Via
V3: Third Via V4: Fourth Via
V5: Via Via V6: Via Via
SR: Solder resist SB: Solder ball
312: Heat dissipation adhesive 412: Nonconductive adhesive
DC: detach core

Claims (21)

1. A multilayer board comprising an electronic part having an external electrode and a first insulating layer having a cavity into which at least a part of the electronic part is inserted,
A first reinforcing layer and a second reinforcing layer respectively provided above and below the first insulating layer; And
A plurality of wiring layers provided between the first reinforcing layer and the second reinforcing layer;
≪ / RTI >
Wherein the first reinforcing layer and the second reinforcing layer are provided at the outermost portions of the multilayer substrate,
Wherein the number of wiring layers provided between the first insulating layer and the second reinforcing layer is greater than the number of wiring layers provided between the first insulating layer and the first reinforcing layer.
The method according to claim 1,
Wherein the first reinforcing layer and the second reinforcing layer are made of a material having a thermal expansion coefficient of 11 ppm / 占 폚 or less.
The method according to claim 1,
Wherein the first reinforcing layer and the second reinforcing layer are made of a material having an elastic modulus of 25 GPa or more.
The method according to claim 1,
Wherein the first reinforcing layer and the second reinforcing layer are made of a material having a thermal expansion coefficient of 11 ppm / 占 폚 or less and an elastic modulus of 25 GPa or more
Multilayer substrate.
The method according to claim 1,
Wherein the first reinforcing layer and the second reinforcing layer are made of a glass material
Multilayer substrate.
The method according to claim 1,
Wherein the outer electrode is located on an outer surface of the outer surface of the electronic component facing the second reinforcing layer
Multilayer substrate.
The method of claim 6,
Wherein the solder resist covers at least a part of one surface of the first reinforcing layer and the other surface of the second reinforcing layer
Multilayer substrate.
The method of claim 6,
A third circuit pattern layer is provided on a lower surface of the first reinforcing layer,
And a second insulating layer contacting the lower surface of the first reinforcing layer and the third circuit pattern layer is further provided between the first reinforcing layer and the first insulating layer
Multilayer substrate.
The method of claim 8,
And a third insulating layer provided between the first insulating layer and the second reinforcing layer and including a fourth circuit pattern layer in contact with the second reinforcing layer,
Multilayer substrate.
In a multilayer board including a plurality of wiring layers,
A first reinforcing layer provided on the outermost one surface of the multilayer substrate;
A second reinforcing layer provided on the outermost surface of the other surface of the multilayer substrate;
A first insulating layer disposed between the first reinforcing layer and the second reinforcing layer, wherein the first insulating layer includes an electronic part having an external electrode and a cavity into which at least a part of the electronic part is inserted;
A third insulating layer formed on the lower surface of the first reinforcing layer and contacting the lower surface of the third circuit pattern layer and the first reinforcing layer and between the first reinforcing layer and the first insulating layer; And
And a third insulating layer provided between the first insulating layer and the second reinforcing layer and including a fourth circuit pattern layer contacting the second reinforcing layer on a surface thereof,
Wherein the third insulating layer
A third upper insulating layer contacting the surfaces of the first insulating layer and the electronic component and having a fifth circuit pattern layer on the lower surface thereof; And
And a third lower insulating layer having one side in contact with the fourth circuit pattern layer and the second reinforcing layer.
The method of claim 10,
A second insulating layer, a third insulating layer, and a third insulating layer, the second insulating layer, the first insulating layer, and the third upper insulating layer, wherein at least one circuit pattern of the third circuit pattern layer and at least one circuit pattern on the fifth circuit pattern layer are directly connected 5 < / RTI > vias.
The method of claim 10,
And a third via penetrating the third upper insulating layer and directly connecting at least one circuit pattern of the fifth circuit pattern layer and the external electrode.
delete delete Mounting an electronic component having external electrodes on a first reinforcing layer having a third circuit pattern layer on one surface thereof;
Forming a second insulating layer covering the third circuit pattern layer and the first reinforcing layer and contacting the side surface of the electronic component on the first reinforcing layer;
Layering a first insulating layer having a cavity into which at least a part of the electronic component is inserted, on the second insulating layer;
Forming a third upper insulating layer on the first insulating layer to cover the electronic component and the first insulating layer and fill the gap between the cavity and the electronic component;
Forming a fifth circuit pattern layer on the third upper insulating layer in which at least one circuit pattern is directly connected to the external electrode by a third via;
Forming a third lower insulating layer covering the fifth circuit pattern layer and the third upper insulating layer on the third upper insulating layer;
Forming a fourth circuit pattern layer on the third lower insulating layer such that at least one circuit pattern is directly connected to at least one circuit pattern of the fifth circuit pattern layer by a fourth via; And
Forming a second reinforcing layer covering the fourth circuit pattern layer and the third lower insulating layer on the third lower insulating layer;
/ RTI >
Wherein the first reinforcing layer and the second reinforcing layer reduce the warpage of the multi-
A method for manufacturing a multilayer substrate.
16. The method of claim 15,
Wherein the first reinforcing layer and the second reinforcing layer are made of a material that satisfies at least one of a condition that a thermal expansion coefficient is 11 ppm / 占 폚 or less and a condition that an elastic modulus is 25 GPa or more
A method for manufacturing a multilayer substrate.
18. The method of claim 16,
The reinforcing layer is formed of a glass material
A method for manufacturing a multilayer substrate.
18. The method of claim 16,
The first reinforcing layer is formed on the upper surface and the lower surface of the detent core, and the multi-layer substrate manufacturing method is performed on the detent core in the top and bottom directions, respectively,
A method for manufacturing a multilayer substrate.
18. The method of claim 16,
The third upper insulating layer and the third lower insulating layer are formed by curing a fluid synthetic resin having no core material
A method for manufacturing a multilayer substrate.
18. The method of claim 16,
The second insulation layer is formed by curing a fluid synthetic resin containing a core material
A method for manufacturing a multilayer substrate.
18. The method of claim 16,
The step of forming the fifth circuit pattern layer on the third upper insulating layer may include:
Forming a fifth via that directly connects at least one circuit pattern of the fifth circuit pattern layer with at least one circuit pattern of the third circuit pattern layer
A method for manufacturing a multilayer substrate.

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