JP2011113568A5 - - Google Patents
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- Publication number
- JP2011113568A5 JP2011113568A5 JP2010263433A JP2010263433A JP2011113568A5 JP 2011113568 A5 JP2011113568 A5 JP 2011113568A5 JP 2010263433 A JP2010263433 A JP 2010263433A JP 2010263433 A JP2010263433 A JP 2010263433A JP 2011113568 A5 JP2011113568 A5 JP 2011113568A5
- Authority
- JP
- Japan
- Prior art keywords
- sync
- data
- clock
- response
- upsizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 52
- 230000004044 response Effects 0.000 claims description 44
- 238000012856 packing Methods 0.000 claims description 10
- 230000004913 activation Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 3
- 230000006870 function Effects 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- MHABMANUFPZXEB-UHFFFAOYSA-N O-demethyl-aloesaponarin I Natural products O=C1C2=CC=CC(O)=C2C(=O)C2=C1C=C(O)C(C(O)=O)=C2C MHABMANUFPZXEB-UHFFFAOYSA-N 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2009-0115414 | 2009-11-26 | ||
| KR1020090115414A KR20110058575A (ko) | 2009-11-26 | 2009-11-26 | 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2011113568A JP2011113568A (ja) | 2011-06-09 |
| JP2011113568A5 true JP2011113568A5 (https=) | 2014-01-30 |
Family
ID=44062069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010263433A Pending JP2011113568A (ja) | 2009-11-26 | 2010-11-26 | 帯域幅同期化回路及び帯域幅同期化方法とこれを含むデータプロセッシングシステム |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8582709B2 (https=) |
| JP (1) | JP2011113568A (https=) |
| KR (1) | KR20110058575A (https=) |
| CN (1) | CN102083196B (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8959398B2 (en) * | 2012-08-16 | 2015-02-17 | Advanced Micro Devices, Inc. | Multiple clock domain debug capability |
| US20160103778A1 (en) * | 2013-06-28 | 2016-04-14 | Hewlett-Packard Development Company, L.P. | Memory component capable to communicate at multiple data widths |
| US20150199286A1 (en) * | 2014-01-10 | 2015-07-16 | Samsung Electronics Co., Ltd. | Network interconnect with reduced congestion |
| KR102206313B1 (ko) | 2014-02-07 | 2021-01-22 | 삼성전자주식회사 | 시스템 인터커넥트 및 시스템 인터커넥트의 동작 방법 |
| US9489009B2 (en) * | 2014-02-20 | 2016-11-08 | Samsung Electronics Co., Ltd. | System on chip, bus interface and method of operating the same |
| KR102588600B1 (ko) * | 2018-11-12 | 2023-10-16 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 동작 방법, 이를 포함하는 스토리지 시스템 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3956580A (en) * | 1970-12-30 | 1976-05-11 | Ricoh Co., Ltd. | System for reducing the transmission time of similar portions of visible images |
| JP2632395B2 (ja) * | 1988-12-01 | 1997-07-23 | 富士通株式会社 | バス接続装置 |
| JP3528198B2 (ja) * | 1993-04-08 | 2004-05-17 | 富士ゼロックス株式会社 | 計算機システム |
| JPH0916511A (ja) | 1995-07-04 | 1997-01-17 | Toshiba Corp | Ｃｐｕバスとローカルバスの変換方式 |
| KR0157924B1 (ko) * | 1995-12-23 | 1998-12-15 | 문정환 | 데이타 전송 시스템 및 그 방법 |
| JPH11126483A (ja) * | 1997-10-20 | 1999-05-11 | Fujitsu Ltd | 省電力同期回路及びそれを有する半導体記憶装置 |
| JP2001134420A (ja) * | 1999-11-02 | 2001-05-18 | Hitachi Ltd | データ処理装置 |
| JP3580242B2 (ja) * | 2000-10-25 | 2004-10-20 | セイコーエプソン株式会社 | シリアル／パラレル変換回路、データ転送制御装置及び電子機器 |
| US6718449B2 (en) * | 2001-07-09 | 2004-04-06 | Sony Corporation | System for data transfer between different clock domains, and for obtaining status of memory device during transfer |
| JP2006164119A (ja) | 2004-12-10 | 2006-06-22 | Renesas Technology Corp | データ処理装置 |
| KR20060103683A (ko) | 2005-03-28 | 2006-10-04 | 엘지전자 주식회사 | Ｃｐｕ를 내장한 ｓｏｃ 구조 |
| US7454632B2 (en) * | 2005-06-16 | 2008-11-18 | Intel Corporation | Reducing computing system power through idle synchronization |
| EP1994668A2 (en) * | 2005-11-23 | 2008-11-26 | Nxp B.V. | A data processor system and a method for communicating data |
-
2009
- 2009-11-26 KR KR1020090115414A patent/KR20110058575A/ko not_active Withdrawn
-
2010
- 2010-10-01 US US12/896,213 patent/US8582709B2/en active Active
- 2010-11-26 JP JP2010263433A patent/JP2011113568A/ja active Pending
- 2010-11-26 CN CN201010566410.4A patent/CN102083196B/zh active Active
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