KR20110058575A - 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법 - Google Patents

데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법 Download PDF

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Publication number
KR20110058575A
KR20110058575A KR1020090115414A KR20090115414A KR20110058575A KR 20110058575 A KR20110058575 A KR 20110058575A KR 1020090115414 A KR1020090115414 A KR 1020090115414A KR 20090115414 A KR20090115414 A KR 20090115414A KR 20110058575 A KR20110058575 A KR 20110058575A
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KR
South Korea
Prior art keywords
data
clock
upsizer
bit width
sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020090115414A
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English (en)
Korean (ko)
Inventor
윤재근
정현욱
엄준형
심성훈
홍성민
정법철
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020090115414A priority Critical patent/KR20110058575A/ko
Priority to US12/896,213 priority patent/US8582709B2/en
Priority to CN201010566410.4A priority patent/CN102083196B/zh
Priority to JP2010263433A priority patent/JP2011113568A/ja
Publication of KR20110058575A publication Critical patent/KR20110058575A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
KR1020090115414A 2009-11-26 2009-11-26 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법 Withdrawn KR20110058575A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020090115414A KR20110058575A (ko) 2009-11-26 2009-11-26 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법
US12/896,213 US8582709B2 (en) 2009-11-26 2010-10-01 Bandwidth synchronization circuit and bandwidth synchronization method
CN201010566410.4A CN102083196B (zh) 2009-11-26 2010-11-26 带宽同步电路和带宽同步方法
JP2010263433A JP2011113568A (ja) 2009-11-26 2010-11-26 帯域幅同期化回路及び帯域幅同期化方法とこれを含むデータプロセッシングシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090115414A KR20110058575A (ko) 2009-11-26 2009-11-26 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법

Publications (1)

Publication Number Publication Date
KR20110058575A true KR20110058575A (ko) 2011-06-01

Family

ID=44062069

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090115414A Withdrawn KR20110058575A (ko) 2009-11-26 2009-11-26 데이터 프로세싱 시스템에서의 대역폭 동기화 회로 및 그에 따른 대역폭 동기화 방법

Country Status (4)

Country Link
US (1) US8582709B2 (https=)
JP (1) JP2011113568A (https=)
KR (1) KR20110058575A (https=)
CN (1) CN102083196B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200054538A (ko) * 2018-11-12 2020-05-20 에스케이하이닉스 주식회사 데이터 저장 장치 및 동작 방법, 이를 포함하는 스토리지 시스템

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959398B2 (en) * 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability
US20160103778A1 (en) * 2013-06-28 2016-04-14 Hewlett-Packard Development Company, L.P. Memory component capable to communicate at multiple data widths
US20150199286A1 (en) * 2014-01-10 2015-07-16 Samsung Electronics Co., Ltd. Network interconnect with reduced congestion
KR102206313B1 (ko) 2014-02-07 2021-01-22 삼성전자주식회사 시스템 인터커넥트 및 시스템 인터커넥트의 동작 방법
US9489009B2 (en) * 2014-02-20 2016-11-08 Samsung Electronics Co., Ltd. System on chip, bus interface and method of operating the same

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
US3956580A (en) * 1970-12-30 1976-05-11 Ricoh Co., Ltd. System for reducing the transmission time of similar portions of visible images
JP2632395B2 (ja) * 1988-12-01 1997-07-23 富士通株式会社 バス接続装置
JP3528198B2 (ja) * 1993-04-08 2004-05-17 富士ゼロックス株式会社 計算機システム
JPH0916511A (ja) 1995-07-04 1997-01-17 Toshiba Corp Ｃｐｕバスとローカルバスの変換方式
KR0157924B1 (ko) * 1995-12-23 1998-12-15 문정환 데이타 전송 시스템 및 그 방법
JPH11126483A (ja) * 1997-10-20 1999-05-11 Fujitsu Ltd 省電力同期回路及びそれを有する半導体記憶装置
JP2001134420A (ja) * 1999-11-02 2001-05-18 Hitachi Ltd データ処理装置
JP3580242B2 (ja) * 2000-10-25 2004-10-20 セイコーエプソン株式会社 シリアル／パラレル変換回路、データ転送制御装置及び電子機器
US6718449B2 (en) * 2001-07-09 2004-04-06 Sony Corporation System for data transfer between different clock domains, and for obtaining status of memory device during transfer
JP2006164119A (ja) 2004-12-10 2006-06-22 Renesas Technology Corp データ処理装置
KR20060103683A (ko) 2005-03-28 2006-10-04 엘지전자 주식회사 Ｃｐｕ를 내장한 ｓｏｃ 구조
US7454632B2 (en) * 2005-06-16 2008-11-18 Intel Corporation Reducing computing system power through idle synchronization
EP1994668A2 (en) * 2005-11-23 2008-11-26 Nxp B.V. A data processor system and a method for communicating data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200054538A (ko) * 2018-11-12 2020-05-20 에스케이하이닉스 주식회사 데이터 저장 장치 및 동작 방법, 이를 포함하는 스토리지 시스템

Also Published As

Publication number Publication date
CN102083196B (zh) 2015-07-08
JP2011113568A (ja) 2011-06-09
US8582709B2 (en) 2013-11-12
CN102083196A (zh) 2011-06-01
US20110122982A1 (en) 2011-05-26

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20091126

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid