JP2011049340A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011049340A
JP2011049340A JP2009196210A JP2009196210A JP2011049340A JP 2011049340 A JP2011049340 A JP 2011049340A JP 2009196210 A JP2009196210 A JP 2009196210A JP 2009196210 A JP2009196210 A JP 2009196210A JP 2011049340 A JP2011049340 A JP 2011049340A
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stress adjusting
adjusting material
semiconductor device
stress
semiconductor element
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Shinji Hiramitsu
真二 平光
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Hitachi Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of securing high reliability even at a high temperature by lowering a heat stress generated in a connection part at the change of temperature as much as possible in a structure where two kinds of materials, such as a semiconductor element and an electrode, are connected on surfaces. <P>SOLUTION: The semiconductor device includes: a semiconductor element; a first stress adjuster, which is connected with the semiconductor element via a connection member and on which holes are formed; a second stress adjuster where protrusions to be pressed into the holes are provided; and a heat conductive material filled in between the first stress adjuster and the second stress adjuster. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置、特に高温で動作するパワー半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device that operates at a high temperature.

図5は、従来のパワー半導体装置の例としてIGBTモジュールの要部断面を示した図である。図5において、1はIGBT,FWDなどの半導体素子、5は接合材、7は銅箔により両面に回路を形成した絶縁基板、8は放熱ベース、9は電極である。なお、モジュールの外囲ケースなどは省略して描かれてない。図5に示すように、半導体装置(特にパワー半導体装置)においては、半導体素子を含むいくつかの部品を面で接合する構造をとるのが一般的である。また、半導体素子は線膨張係数が非常に小さく、電極やベースは半導体素子の数倍の線膨張係数を有することが多い。そのため、半導体装置に温度変化を与えた場合、接合材には、半導体素子と電極などの線膨張係数差に起因する熱応力が発生する。この熱応力が繰り返し負荷されると、接合部が破壊に至る恐れがある。接合部の信頼性を確保するための構造として、特許文献1には、半導体素子と部品の中間の線膨張係数を有する部品を挿入し熱応力を分散する構造が開示されている。また、特許文献2には、接合部を樹脂封止することで熱応力を低減する構造が開示されている。   FIG. 5 is a view showing a cross section of a main part of an IGBT module as an example of a conventional power semiconductor device. In FIG. 5, 1 is a semiconductor element such as IGBT or FWD, 5 is a bonding material, 7 is an insulating substrate having a circuit formed on both sides by copper foil, 8 is a heat dissipation base, and 9 is an electrode. In addition, the outer case of the module is not omitted. As shown in FIG. 5, a semiconductor device (particularly a power semiconductor device) generally has a structure in which several parts including a semiconductor element are joined on a surface. Moreover, the semiconductor element has a very small linear expansion coefficient, and the electrode and the base often have a linear expansion coefficient several times that of the semiconductor element. Therefore, when a temperature change is given to the semiconductor device, thermal stress resulting from a difference in coefficient of linear expansion between the semiconductor element and the electrode is generated in the bonding material. When this thermal stress is repeatedly applied, the joint may be broken. As a structure for ensuring the reliability of the joint, Patent Document 1 discloses a structure in which a component having a linear expansion coefficient intermediate between the semiconductor element and the component is inserted to disperse the thermal stress. Patent Document 2 discloses a structure that reduces thermal stress by resin-sealing a joint.

特開2005−56873号公報JP 2005-56873 A 特開2006−179732号公報JP 2006-179732 A

近年、パワー半導体分野では、SiC素子やGaN素子の開発を背景に、従来以上の高温域での動作に対する要求が高まってきている。パワー半導体装置の使用温度が高くなると、接合部に発生する熱応力も大きくなるために、特許文献1,2に開示された構造では、接合部の信頼性を十分に確保できないのが現状である。   In recent years, in the field of power semiconductors, there has been an increasing demand for operation in a higher temperature range than before, against the background of development of SiC elements and GaN elements. When the operating temperature of the power semiconductor device is increased, the thermal stress generated in the joint portion also increases. Therefore, in the structures disclosed in Patent Documents 1 and 2, the reliability of the joint portion cannot be sufficiently ensured at present. .

本発明の目的は上記課題に鑑みて成されたものであり、半導体素子と電極のような2種類の材質を面で接合した構造において、温度変化時に接合部に発生する熱応力を極力低減し、高温域でも高い信頼性を確保することが可能な半導体装置を提供することにある。   The object of the present invention has been made in view of the above problems, and in a structure in which two kinds of materials such as a semiconductor element and an electrode are joined on the surface, the thermal stress generated at the joint when the temperature changes is reduced as much as possible. Another object is to provide a semiconductor device capable of ensuring high reliability even in a high temperature range.

本発明は、上記課題を解決するために、半導体素子と、前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、前記穴に圧入される突起が設けられた第二の応力調節材と、前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材とを有する。また、半導体素子と、前記半導体素子に、接合材を介して接続されたリードフレームと、前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、前記穴に圧入される突起が設けられた第二の応力調節材と、前記第二の応力調節材に、接合材を介して接続された絶縁基板と、前記絶縁基板に、接合材を介して接続された放熱ベースと、前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材を有する。さらに、前記第一の応力調節材の線膨張係数は、前記第二の応力調節材の線膨張係数よりも小さい。さらに、前記第一の応力調節材の線膨張係数が10ppm/℃以下である。さらに、前記第二の応力調節材と前記放熱ベースとが同じ材質である。さらに、前記穴は、前記第一の応力調節材の中央部に形成され、前記突起は、前記第二の応力調節材の中央部に設けられる。さらに、前記穴と前記突起は、前記半導体素子と重なる領域に設けられる。さらに、前記穴と前記突起がネジ構造である。さらに、前記穴は、前記第一の応力調節材を貫通していない。また、半導体素子と、前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、前記穴に圧入される突起が設けられた第二の応力調節材と、前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材を有し、前記半導体素子を軸として、前記半導体素子の両側に、前記第一の応力調節材,前記熱伝導材及び前記第二の応力調節材が対称に配置される。   In order to solve the above problems, the present invention provides a semiconductor element, a first stress adjusting material connected to the semiconductor element via a bonding material and having a hole formed therein, and a protrusion press-fitted into the hole. A second stress adjusting material provided; and a heat conductive material filled between the first stress adjusting material and the second stress adjusting material. Further, a semiconductor element, a lead frame connected to the semiconductor element via a bonding material, a first stress adjusting material connected to the semiconductor element via a bonding material and having a hole formed therein, A second stress adjusting material provided with a protrusion press-fitted into the hole; an insulating substrate connected to the second stress adjusting material via a bonding material; and connected to the insulating substrate via a bonding material. And a heat conducting material filled between the first stress adjusting material and the second stress adjusting material. Furthermore, the linear expansion coefficient of the first stress adjusting material is smaller than the linear expansion coefficient of the second stress adjusting material. Furthermore, the linear expansion coefficient of the first stress adjusting material is 10 ppm / ° C. or less. Furthermore, the second stress adjusting material and the heat dissipation base are the same material. Further, the hole is formed in a central portion of the first stress adjusting material, and the protrusion is provided in a central portion of the second stress adjusting material. Further, the hole and the protrusion are provided in a region overlapping with the semiconductor element. Furthermore, the hole and the protrusion have a screw structure. Further, the hole does not penetrate the first stress adjusting material. A semiconductor element; a first stress adjusting material connected to the semiconductor element via a bonding material; and a hole formed therein; a second stress adjusting material provided with a protrusion press-fitted into the hole; The first stress adjusting material has a heat conductive material filled between the first stress adjusting material and the second stress adjusting material, and the first stress adjusting material is formed on both sides of the semiconductor element with the semiconductor element as an axis. The material, the heat conducting material and the second stress adjusting material are arranged symmetrically.

本発明によれば、半導体素子と電極のような2種類の材質を面で接合した構造において、温度変化時に接合部に発生する熱応力を極力低減し、高温域でも高い信頼性を確保することが可能な半導体装置を提供することが可能となる。   According to the present invention, in a structure in which two kinds of materials such as a semiconductor element and an electrode are bonded on the surface, the thermal stress generated in the bonded portion when temperature changes is reduced as much as possible, and high reliability is ensured even in a high temperature range. It is possible to provide a semiconductor device capable of performing the above.

実施例1の半導体装置の斜視図である。1 is a perspective view of a semiconductor device of Example 1. FIG. 実施例1の半導体装置の平面図である。1 is a plan view of a semiconductor device of Example 1. FIG. 図2のA−A線における断面図である。It is sectional drawing in the AA of FIG. 実施例1の半導体装置の分解斜視図である。1 is an exploded perspective view of a semiconductor device of Example 1. FIG. 従来技術による半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device by a prior art. 実施例2の半導体装置の要部断面図および平面図である。FIG. 6 is a cross-sectional view and a plan view of main parts of a semiconductor device of Example 2. 実施例3の半導体装置の要部断面図および平面図である。FIG. 6 is a cross-sectional view and a plan view of a main part of a semiconductor device of Example 3. 実施例4の半導体装置の要部断面図および平面図である。FIG. 10 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 4; 実施例5の半導体装置の要部断面図である。FIG. 10 is a main part sectional view of a semiconductor device according to Example 5; 実施例6の半導体装置の要部断面図および平面図である。FIG. 16 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 6. 実施例7の半導体装置の要部断面図である。FIG. 10 is a main-portion cross-sectional view of a semiconductor device in Example 7. 実施例8の半導体装置の要部断面図である。FIG. 10 is a main part sectional view of a semiconductor device in Example 8; 実施例9の半導体装置の要部断面図および平面図である。FIG. 20 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 9; 実施例10の半導体装置の要部断面図および平面図である。FIG. 16 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 10; 実施例11の半導体装置の要部断面図および平面図である。FIG. 44 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 11; 実施例12の半導体装置の要部断面図である。FIG. 34 is a main-portion cross-sectional view of the semiconductor device of Example 12; 実施例13の半導体装置の要部断面図および平面図である。FIG. 44 is a cross-sectional view and a plan view of main parts of a semiconductor device according to Example 13; 実施例14の半導体装置の要部断面図である。FIG. 40 is a main-portion cross-sectional view of the semiconductor device of Example 14; 実施例15の半導体装置の要部断面図である。FIG. 40 is a main-portion cross-sectional view of the semiconductor device of Example 15;

図1は、実施例1の半導体装置の斜視図である。図1に示す半導体装置は、半導体素子1,第一の応力調節材2,第二の応力調節材3,電極4,接合材5,熱伝導材6からなる。なお、モジュールの外囲ケースなどは省略して描かれてない。図2は、実施例1の半導体装置の平面図である。図3は、図2のA−A線における断面図である。図4は、実施例1の半導体装置の分解斜視図である。半導体素子1と第一の応力調節材2,第二の応力調節材3と電極4は、それぞれ接合材5で接続され、第一の応力調節材2と第二の応力調節材3は、突起3aを第一の応力調節材2の穴に圧入することで機械的に接続され、その間には熱伝導材6が充填されている。   FIG. 1 is a perspective view of the semiconductor device according to the first embodiment. The semiconductor device shown in FIG. 1 includes a semiconductor element 1, a first stress adjusting material 2, a second stress adjusting material 3, an electrode 4, a bonding material 5, and a heat conducting material 6. In addition, the outer case of the module is not omitted. FIG. 2 is a plan view of the semiconductor device according to the first embodiment. 3 is a cross-sectional view taken along line AA in FIG. FIG. 4 is an exploded perspective view of the semiconductor device according to the first embodiment. The semiconductor element 1, the first stress adjusting material 2, the second stress adjusting material 3 and the electrode 4 are respectively connected by a bonding material 5, and the first stress adjusting material 2 and the second stress adjusting material 3 are projected. 3a is mechanically connected by press-fitting into the hole of the first stress adjusting material 2, and a heat conducting material 6 is filled between them.

ここで、半導体素子1にはSiを用いているが、SiCやGaNを用いてもよい。第一の応力調節材2にはMoを用いているが、線膨張係数が10ppm/℃以下の材質であればよく、W,Fe−Ni合金,前述した金属(Mo,W,Fe−Ni合金)とCuとの複合材(合金,積層材,混合焼結材),ダイヤモンドを用いてもよい。第二の応力調節材3と電極4は同じ材質であることが好ましく、実施例1ではいずれも銅を用いている。さらに、第一の応力調節材2の線膨張係数よりも第二の応力調節材3の線膨張係数の方が大きいことが好ましい。接合材5にはAgの焼結材を使用しているが、Sn−Sb系はんだ,Sn−Cu系はんだ,Bi−Ag系はんだ,Zn−Al系はんだ,AgやCuのロウ材,焼結材,ペースト材を用いてもよい。熱伝導材6は、サーマルコンパウンドを用いているが、はんだ材やAgペースト材を用いてもよい。   Here, although Si is used for the semiconductor element 1, SiC or GaN may be used. Mo is used for the first stress adjusting material 2, but any material having a linear expansion coefficient of 10 ppm / ° C. or less may be used. W, Fe—Ni alloy, metal (Mo, W, Fe—Ni alloy) ) And Cu composite material (alloy, laminated material, mixed sintered material) or diamond may be used. The second stress adjusting material 3 and the electrode 4 are preferably made of the same material, and in Example 1, both are made of copper. Furthermore, it is preferable that the linear expansion coefficient of the second stress adjusting material 3 is larger than the linear expansion coefficient of the first stress adjusting material 2. The bonding material 5 uses an Ag sintered material, but it is Sn-Sb solder, Sn-Cu solder, Bi-Ag solder, Zn-Al solder, Ag or Cu brazing material, sintered. A material or a paste material may be used. Although the thermal conductive material 6 uses a thermal compound, a solder material or an Ag paste material may be used.

図6は、実施例2の半導体装置の要部断面図および平面図である。図6に示す半導体装置は、リードフレーム電極9,半導体素子1,第一の応力調節材2,第二の応力調節材3,絶縁材両面に銅箔で回路を形成した絶縁基板7,放熱ベース8を積層し、第一の応力調節材2と第二の応力調節材3の間には熱伝導材6を充填し、それ以外の部材間を接合材5で接続した構造となっている。なお、モジュールの外囲ケースなどは省略して描かれてない。図1との相違は、絶縁基板7やリードフレーム電極9が構造に含まれている点であり、IGBTモジュール等への適用可能であることを示す一例である。このとき、絶縁基板7の半導体素子側に形成されている回路7aと第二の応力調節材3が一体となっていてもよい。また、図6において、第一の応力調節材2の穴と、第二の応力調節材3の突起は4つとなっているが、4つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 6 is a cross-sectional view and a plan view of the main part of the semiconductor device according to the second embodiment. 6 includes a lead frame electrode 9, a semiconductor element 1, a first stress adjusting material 2, a second stress adjusting material 3, an insulating substrate 7 having a circuit formed of copper foil on both surfaces of the insulating material, and a heat dissipation base. 8 is laminated, a heat conductive material 6 is filled between the first stress adjusting material 2 and the second stress adjusting material 3, and the other members are connected by a bonding material 5. In addition, the outer case of the module is not omitted. The difference from FIG. 1 is that the insulating substrate 7 and the lead frame electrode 9 are included in the structure, which is an example showing that the structure can be applied to an IGBT module or the like. At this time, the circuit 7a formed on the semiconductor element side of the insulating substrate 7 and the second stress adjusting material 3 may be integrated. In FIG. 6, the number of the holes of the first stress adjusting material 2 and the number of the protrusions of the second stress adjusting material 3 are four, but it is not necessary to be four. The shape of the holes and protrusions need not be cylindrical.

図7は、実施例3の半導体装置の要部断面図および平面図である。図6との相違は、第一の応力調節材2と第二の応力調節材3を接続する突起3aが接合の外周付近ではなく接合の中央部(第二の応力調節材3の中央部)に、1つだけ設けられている点である。また、これに伴い、第一の応力調節材2の穴は、第一の応力調節材2の中央部に形成されている。これにより、第二の応力調節材3の熱膨張により第一の応力調節材2が引っ張られ、第一の応力調節材2が本来の熱膨張分以上に変形することを防ぐことができる。   FIG. 7 is a cross-sectional view and plan view of the main part of the semiconductor device according to the third embodiment. The difference from FIG. 6 is that the protrusion 3a connecting the first stress adjusting material 2 and the second stress adjusting material 3 is not in the vicinity of the outer periphery of the joint, but in the center of the joint (the center of the second stress adjusting material 3). In addition, only one is provided. Accordingly, the hole of the first stress adjusting material 2 is formed in the central portion of the first stress adjusting material 2. Thereby, the 1st stress adjustment material 2 is pulled by the thermal expansion of the 2nd stress adjustment material 3, and it can prevent that the 1st stress adjustment material 2 deform | transforms more than original thermal expansion.

図8は、実施例4の半導体装置の要部断面図および平面図である。図7との相違は、第二の応力調節材3の突起3bがネジとなっており、第一の応力調節材2と第二の応力調節材3がネジ構造により締結されて、接続されている点である。これにより、第一の応力調節材2と第二の応力調節材3の組付けを簡便にすることができる。   FIG. 8 is a cross-sectional view and plan view of the main part of the semiconductor device according to the fourth embodiment. The difference from FIG. 7 is that the protrusion 3b of the second stress adjusting material 3 is a screw, and the first stress adjusting material 2 and the second stress adjusting material 3 are fastened and connected by a screw structure. It is a point. Thereby, the assembly | attachment of the 1st stress adjusting material 2 and the 2nd stress adjusting material 3 can be simplified.

図9は、実施例5の半導体装置の要部断面図および平面図である。図6との相違は、第二の応力調節材3の突起3aが半導体素子1と重なる領域に配置されている点である。これにより、半導体素子1で発生する熱を第二の応力調節材3側にある放熱ベース8まで効率よく逃がすことができる。また、図9において、第一の応力調節材2の穴と、第二の応力調節材3の突起は4つとなっているが、4つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 9 is a cross-sectional view and plan view of the main part of the semiconductor device of Example 5. The difference from FIG. 6 is that the protrusion 3 a of the second stress adjusting material 3 is arranged in a region overlapping the semiconductor element 1. Thereby, the heat generated in the semiconductor element 1 can be efficiently released to the heat dissipation base 8 on the second stress adjusting material 3 side. In FIG. 9, the number of the holes of the first stress adjusting material 2 and the number of the protrusions of the second stress adjusting material 3 are four, but it is not necessary to be four. The shape of the holes and protrusions need not be cylindrical.

図10は、実施例6の半導体装置の要部断面図である。図9との相違は、接合中央部に1つだけ配置されている点である。これにより、半導体素子1で発生する熱を第二の応力調節材3側にある放熱ベース8まで効率よく逃がすことができ、かつ、接合材端部に発生する熱応力を低減することができる。   FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Example 6. The difference from FIG. 9 is that only one is arranged at the center of the joint. Thereby, the heat generated in the semiconductor element 1 can be efficiently released to the heat dissipation base 8 on the second stress adjusting material 3 side, and the thermal stress generated at the end of the bonding material can be reduced.

図11は、実施例7の半導体装置の要部断面図および平面図である。図10との相違は、第二の応力調節材3の突起3aがネジとなっており、かつ、第一の応力調節材2を貫通していない点である。これにより、半導体素子1と第一の応力調節材2の間の接合材5の中央付近での劣化を防ぐことができる。   FIG. 11 is a cross-sectional view and plan view of the main part of the semiconductor device according to the seventh embodiment. The difference from FIG. 10 is that the protrusion 3 a of the second stress adjusting material 3 is a screw and does not penetrate the first stress adjusting material 2. Thereby, deterioration of the bonding material 5 between the semiconductor element 1 and the first stress adjusting material 2 near the center can be prevented.

図12は、実施例8の半導体装置の要部断面図である。図12に示す半導体装置は、放熱ベース8,絶縁材両面に銅箔で回路を形成した絶縁基板7,第二の応力調節材3,第一の応力調節材2,半導体素子1,第一の応力調節材2,第二の応力調節材3,絶縁材両面に銅箔で回路を形成した絶縁基板7,放熱ベース8を積層し、第一の応力調節材2と第二の応力調節材3の間には熱伝導材6を充填し、それ以外の部材間を接合材5で接続した構造となっている。なお、モジュールの外囲ケースなどは省略して描かれてない。図6との相違は、半導体素子1を軸としてその両側に対称となるように、一対の応力調節材2,3,一対の絶縁基板7,一対の放熱ベース8が配置されている点である。これにより放熱面積が2倍になるので、放熱性が向上する。また、図12において、第一の応力調節材2の穴と、第二の応力調節材3の突起は2つであるが、2つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 12 is a cross-sectional view of a principal part of the semiconductor device according to the eighth embodiment. The semiconductor device shown in FIG. 12 includes a heat dissipation base 8, an insulating substrate 7 having a circuit formed of copper foil on both sides of the insulating material, a second stress adjusting material 3, a first stress adjusting material 2, a semiconductor element 1, a first element. A stress adjusting material 2, a second stress adjusting material 3, an insulating substrate 7 having a circuit formed of copper foil on both sides of the insulating material, and a heat dissipation base 8 are laminated, and the first stress adjusting material 2 and the second stress adjusting material 3 are laminated. Between them, the heat conductive material 6 is filled, and the other members are connected by the bonding material 5. In addition, the outer case of the module is not omitted. A difference from FIG. 6 is that a pair of stress adjusting materials 2, 3, a pair of insulating substrates 7, and a pair of heat dissipation bases 8 are arranged so as to be symmetrical on both sides of the semiconductor element 1 as an axis. . This doubles the heat dissipation area, improving heat dissipation. In FIG. 12, the number of the holes in the first stress adjusting material 2 and the number of the protrusions in the second stress adjusting material 3 are two, but it is not necessary to be two. The shape of the holes and protrusions need not be cylindrical.

図13は、実施例9の半導体装置の要部断面図である。図13に示す半導体装置は、リードフレーム電極9,半導体素子1,絶縁材両面に銅箔で回路を形成した絶縁基板7,第一の応力調節材2,第二の応力調節材3を積層し、第一の応力調節材2と第二の応力調節材3の間には熱伝導材6を充填し、それ以外の部材間を接合材5で接続した構造となっている。なお、モジュールの外囲ケースなどは省略して描かれてない。図1との相違は、絶縁基板7やリードフレーム電極9が構造に含まれており、かつ放熱ベース8が削減されている点であり、図6と異なる構造でもIGBTモジュール等への適用可能であることを示す一例である。このとき、第二の応力調節材3が放熱ベースの役割を果たせるよう、突起3aが配置された面と反対側に放熱用のフィンを設けてもよい。また、図13において、第一の応力調節材2の穴と、第二の応力調節材3の突起は4つとなっているが、4つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 13 is a cross-sectional view of a principal part of the semiconductor device according to the ninth embodiment. The semiconductor device shown in FIG. 13 includes a lead frame electrode 9, a semiconductor element 1, an insulating substrate 7 having a circuit formed of copper foil on both surfaces of the insulating material, a first stress adjusting material 2, and a second stress adjusting material 3. The first stress adjusting material 2 and the second stress adjusting material 3 are filled with a heat conductive material 6 and the other members are connected by a bonding material 5. In addition, the outer case of the module is not omitted. The difference from FIG. 1 is that the structure includes an insulating substrate 7 and a lead frame electrode 9 and the heat dissipation base 8 is reduced. Even a structure different from FIG. 6 can be applied to an IGBT module or the like. It is an example which shows that there is. At this time, a fin for heat radiation may be provided on the side opposite to the surface on which the protrusion 3a is arranged so that the second stress adjusting material 3 can serve as a heat radiation base. In FIG. 13, there are four holes in the first stress adjusting material 2 and four protrusions in the second stress adjusting material 3, but it is not necessary to have four. The shape of the holes and protrusions need not be cylindrical.

図14は、実施例10の半導体装置の要部断面図および平面図である。図13との相違は、第一の応力調節材2と第二の応力調節材3を接続する突起3aが接合の外周付近ではなく接合中央部に1つだけ配置されている点である。これにより、第二の応力調節材3の熱膨張により第一の応力調節材2が引っ張られ、第一の応力調節材2が本来の熱膨張分以上に変形することを防ぐことができる。   FIG. 14 is a cross-sectional view and plan view of the main part of the semiconductor device of Example 10. The difference from FIG. 13 is that only one protrusion 3a connecting the first stress adjusting material 2 and the second stress adjusting material 3 is disposed not in the vicinity of the outer periphery of the joint but in the center of the joint. Thereby, the 1st stress adjustment material 2 is pulled by the thermal expansion of the 2nd stress adjustment material 3, and it can prevent that the 1st stress adjustment material 2 deform | transforms more than original thermal expansion.

図15は、実施例11の半導体装置の要部断面図および平面図である。図14との相違は、第二の応力調節材3の突起3aがネジとなっており、第一の応力調節材2と第二の応力調節材3がネジ締結により接続されている点である。これにより、第一の応力調節材2と第二の応力調節材3の組付けを簡便にすることができる。   FIG. 15 is a cross-sectional view and plan view of the principal part of the semiconductor device of Example 11. The difference from FIG. 14 is that the protrusion 3a of the second stress adjusting material 3 is a screw, and the first stress adjusting material 2 and the second stress adjusting material 3 are connected by screw fastening. . Thereby, the assembly | attachment of the 1st stress adjusting material 2 and the 2nd stress adjusting material 3 can be simplified.

図16は、実施例12の半導体装置の要部断面図および平面図である。図13との相違は、第二の応力調節材3の突起3aが半導体素子1に重なるように配置されている点である。これにより、半導体素子1で発生する熱を第二の応力調節材3側にある放熱ベース8まで効率よく逃がすことができる。また、図16において、第一の応力調節材2の穴と、第二の応力調節材3の突起は4つとなっているが、4つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 16 is a cross-sectional view and plan view of the main part of the semiconductor device of Example 12. A difference from FIG. 13 is that the protrusion 3 a of the second stress adjusting material 3 is arranged so as to overlap the semiconductor element 1. Thereby, the heat generated in the semiconductor element 1 can be efficiently released to the heat dissipation base 8 on the second stress adjusting material 3 side. In FIG. 16, the number of the holes of the first stress adjusting material 2 and the number of the protrusions of the second stress adjusting material 3 are four, but it is not necessary to be four. The shape of the holes and protrusions need not be cylindrical.

図17は、実施例13の半導体装置の要部断面図および平面図である。図15との相違は、第二の応力調節材3の突起3aが半導体素子1に重なり、かつ、接合中央部に1つだけ配置されている点である。これにより、半導体素子1で発生する熱を第二の応力調節材3側にある放熱ベース8まで効率よく逃がすことができ、かつ、接合材端部に発生する熱応力を低減することができる。   FIG. 17 is a cross-sectional view and plan view of the principal part of the semiconductor device of Example 13. The difference from FIG. 15 is that the protrusion 3 a of the second stress adjusting material 3 overlaps with the semiconductor element 1 and only one protrusion 3 a is disposed at the center of the junction. Thereby, the heat generated in the semiconductor element 1 can be efficiently released to the heat dissipation base 8 on the second stress adjusting material 3 side, and the thermal stress generated at the end of the bonding material can be reduced.

図18は、実施例14の半導体装置の要部断面図である。図17との相違は、第二の応力調節材3の突起3cがネジとなっており、かつ、第一の応力調節材2を貫通していない点である。これにより、半導体素子1と第一の応力調節材2の間の接合材5の中央付近での劣化を防ぐことができる。   FIG. 18 is a fragmentary cross-sectional view of the semiconductor device of Example 14. The difference from FIG. 17 is that the protrusion 3 c of the second stress adjusting material 3 is a screw and does not penetrate the first stress adjusting material 2. Thereby, deterioration of the bonding material 5 between the semiconductor element 1 and the first stress adjusting material 2 near the center can be prevented.

図19は、実施例15の半導体装置の要部断面図および平面図である。図19に示す半導体装置は、第二の応力調節材3,第一の応力調節材2,絶縁材両面に銅箔で回路を形成した絶縁基板7,半導体素子1,絶縁材両面に銅箔で回路を形成した絶縁基板7,第一の応力調節材2,第二の応力調節材3を積層し、第一の応力調節材2と第二の応力調節材3の間には熱伝導材6を充填し、それ以外の部材間を接合材5で接続した構造となっている。なお、モジュールの外囲ケースなどは省略して描かれてない。図13との相違は、両側に絶縁基板7,応力調節材2,3が配置されている点である。これにより放熱面積が2倍になるので、放熱性が向上する。また、図19において、第一の応力調節材2の穴と、第二の応力調節材3の突起は2つとなっているが、2つである必要はない。穴と突起の形状も円柱である必要はない。   FIG. 19 is a cross-sectional view and plan view of the principal part of the semiconductor device of Example 15. The semiconductor device shown in FIG. 19 includes a second stress adjusting material 3, a first stress adjusting material 2, an insulating substrate 7 having a circuit formed of copper foil on both surfaces of the insulating material, a semiconductor element 1, and copper foil on both surfaces of the insulating material. The insulating substrate 7 on which the circuit is formed, the first stress adjusting material 2 and the second stress adjusting material 3 are laminated, and the heat conducting material 6 is interposed between the first stress adjusting material 2 and the second stress adjusting material 3. The other members are connected by a bonding material 5. In addition, the outer case of the module is not omitted. The difference from FIG. 13 is that insulating substrates 7 and stress adjusting materials 2 and 3 are arranged on both sides. This doubles the heat dissipation area, improving heat dissipation. In FIG. 19, the number of the holes of the first stress adjusting material 2 and the number of the protrusions of the second stress adjusting material 3 are two, but it is not necessary to be two. The shape of the holes and protrusions need not be cylindrical.

以上記載した実施例によれば、半導体装置の温度が上昇して接続部周辺の各部材が熱膨張しても、半導体素子と半導体素子に近い線膨張係数を有する板との間の膨張量差は小さいので、その間の接合材に発生する熱応力は小さくなる。さらに、電極と電極に近い線膨張係数を有する板との間の膨張量差も小さいので、その代打の接合材に発生する熱応力は同様に小さくなる。また、挿入した2つの板の間は機械的に接続されている上に、穴の内側にある突起が熱膨張することで両者の接触面圧は大きくなるので、両者は熱的にも機械的にもより強く接続されることとなり、繰り返しの熱変化による各接続部の劣化は少なくなる。   According to the embodiment described above, even if the temperature of the semiconductor device rises and each member around the connection portion thermally expands, the difference in expansion amount between the semiconductor element and the plate having a linear expansion coefficient close to the semiconductor element. Is small, the thermal stress generated in the bonding material therebetween is small. Further, since the difference in expansion amount between the electrode and a plate having a linear expansion coefficient close to the electrode is small, the thermal stress generated in the substitute material for the impact is similarly reduced. In addition, the two inserted plates are mechanically connected to each other, and the protrusions inside the holes are thermally expanded to increase the contact surface pressure between them. The connection is stronger, and the deterioration of each connection portion due to repeated heat changes is reduced.

1 半導体素子
2 第一の応力調節材
3 第二の応力調節材
3a 接続用突起
4 電極
5 接合材
6 熱伝導材
7 両面に回路が形成された絶縁基板
7a,7b 絶縁基板に形成された回路
8 放熱ベース
9 リードフレーム電極
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 1st stress adjusting material 3 2nd stress adjusting material 3a Connection protrusion 4 Electrode 5 Bonding material 6 Thermal conductive material 7 Insulated substrates 7a and 7b having circuits formed on both surfaces 8 Heat dissipation base 9 Lead frame electrode

Claims (10)

半導体素子と、
前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、
前記穴に圧入される突起が設けられた第二の応力調節材と、
前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材とを有することを特徴とする半導体装置。
A semiconductor element;
A first stress adjusting material connected to the semiconductor element via a bonding material and having a hole;
A second stress adjusting material provided with a protrusion press-fitted into the hole;
A semiconductor device comprising: a heat conductive material filled between the first stress adjusting material and the second stress adjusting material.
半導体素子と、
前記半導体素子に、接合材を介して接続されたリードフレーム電極と、
前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、
前記穴に圧入される突起が設けられた第二の応力調節材と、
前記第二の応力調節材に、接合材を介して接続された絶縁基板と、
前記絶縁基板に、接合材を介して接続された放熱ベースと、
前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材を有することを特徴とする半導体装置。
A semiconductor element;
A lead frame electrode connected to the semiconductor element via a bonding material;
A first stress adjusting material connected to the semiconductor element via a bonding material and having a hole;
A second stress adjusting material provided with a protrusion press-fitted into the hole;
An insulating substrate connected to the second stress adjusting material via a bonding material;
A heat dissipation base connected to the insulating substrate via a bonding material;
A semiconductor device comprising: a heat conductive material filled between the first stress adjusting material and the second stress adjusting material.
請求項1又は2に記載の半導体装置において、
前記第一の応力調節材の線膨張係数は、前記第二の応力調節材の線膨張係数よりも小さいことを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein a linear expansion coefficient of the first stress adjusting material is smaller than a linear expansion coefficient of the second stress adjusting material.
請求項3に記載の半導体装置において、
前記第一の応力調節材の線膨張係数が10ppm/℃以下であることを特徴とする半導体装置。
The semiconductor device according to claim 3.
A semiconductor device, wherein the first stress adjusting material has a linear expansion coefficient of 10 ppm / ° C. or less.
請求項2に記載の半導体装置において、
前記第二の応力調節材と前記放熱ベースとが同じ材質であることを特徴とする半導体装置。
The semiconductor device according to claim 2,
The semiconductor device, wherein the second stress adjusting material and the heat dissipation base are made of the same material.
請求項1又は2に記載の半導体装置において、
前記穴は、前記第一の応力調節材の中央部に形成され、
前記突起は、前記第二の応力調節材の中央部に設けられたことを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
The hole is formed in a central portion of the first stress adjusting material,
The semiconductor device according to claim 1, wherein the protrusion is provided at a central portion of the second stress adjusting material.
請求項1又は2に記載の半導体装置において、
前記穴と前記突起は、前記半導体素子と重なる領域に設けられたことを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the hole and the protrusion are provided in a region overlapping with the semiconductor element.
請求項1又は2に記載の半導体装置において、
前記穴と前記突起がネジ構造であることを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the hole and the protrusion have a screw structure.
請求項8に記載の半導体装置において、
前記穴は、前記第一の応力調節材を貫通していないことを特徴とする半導体装置。
The semiconductor device according to claim 8,
The semiconductor device according to claim 1, wherein the hole does not penetrate the first stress adjusting material.
半導体素子と、
前記半導体素子に、接合材を介して接続され、穴が形成された第一の応力調節材と、
前記穴に圧入される突起が設けられた第二の応力調節材と、
前記第一の応力調節材と前記第二の応力調節材との間に充填された熱伝導材を有し、
前記半導体素子を軸として、前記半導体素子の両側に、前記第一の応力調節材、前記熱伝導材及び前記第二の応力調節材が対称に配置されたことを特徴とする半導体装置。
A semiconductor element;
A first stress adjusting material connected to the semiconductor element via a bonding material and having a hole;
A second stress adjusting material provided with a protrusion press-fitted into the hole;
A heat conductive material filled between the first stress adjusting material and the second stress adjusting material;
A semiconductor device, wherein the first stress adjusting material, the heat conducting material, and the second stress adjusting material are symmetrically arranged on both sides of the semiconductor element with the semiconductor element as an axis.
JP2009196210A 2009-08-27 2009-08-27 Semiconductor device Pending JP2011049340A (en)

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