JP2017135183A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily inhibit the occurrence of a crack in a solder central part by increasing downward pressure.SOLUTION: A semiconductor device 100 comprises a housing 21, a semiconductor element 16, a retainer plate 18 and a pushing member 19. The housing 21 includes an insulating substrate 13. The semiconductor element 16 is joined to one principal surface 13a of the insulating substrate 13 by solder 15. The retainer plate 18 is arranged on the semiconductor element 16 on one principal surface 16a side opposite to the surface joined with the insulating substrate 13 so as to overlap the central part of the semiconductor element 16 in plan view. The pushing member 19 can press the retainer plate 18 from one principal surface 18a side of the retainer plate 18 opposite to the side where the semiconductor element 16 is located to the semiconductor element 16 side. The pushing member 19 can press the retainer plate 18 to the semiconductor element 16 side in a state of being fastened to the housing 21.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a power module.

  The operation of the semiconductor element mounted on the power module is exposed to a temperature cycle in which the temperature fluctuates because the main current is switched at high speed. Various materials exposed to a high temperature state or a temperature cycle generate stress load on the joint due to a change in structure and a difference in linear expansion coefficient, and voids, cracks, or peeling occur in various places. In the members constituting the power module, the portions where defects are likely to occur are the joint portions, and particularly the solder joint portions that join the substrates are most likely to deteriorate.

  For example, when a silicon substrate and a copper substrate are joined together by solder, which are members with significantly different linear expansion coefficients, shear stress is generated at the solder joint, and cracks occur almost parallel to the joint surface from the outer periphery of the solder toward the center. Lateral cracks occur as the process progresses. When transverse cracks occur in the solder portion, the thermal resistance for releasing the heat generated in the semiconductor element to the outside increases, and the semiconductor element and the like are destroyed. In order to avoid this problem, it is preferable to reduce the difference in coefficient of linear expansion between materials to be joined by soldering in the power module. Thereby, since the generated thermal stress is reduced, the risk of joint failure is greatly reduced, and lateral cracking can be suppressed.

  However, when a temperature cycle is applied to a power module with a small difference in coefficient of linear expansion between the materials to be joined, a small void is formed in the center of the solder, and a number of these small voids are connected in a direction perpendicular to the substrate surface. There is. Thereby, the vertical crack which is a crack perpendicular | vertical to a substrate surface becomes easy to generate | occur | produce. The voids or cracks due to the vertical cracks are scattered in the center of the solder, but eventually the cracks due to the vertical cracks are connected in a network and spread to the periphery. Longitudinal cracks, like horizontal cracks, increase the thermal resistance of solder and become one of the causes of power module failures.

  In order to prevent such vertical cracks, for example, in Japanese Patent Application Laid-Open No. 2008-277335 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2008-300792 (Patent Document 2), the most current and There has been proposed a technique for performing solder bonding using a different bonding material between a central portion of a semiconductor element having a high heat generation density and its peripheral portion.

  However, when such a bonding material is used, it is necessary to mutually adjust the optimum bonding profile of each material, which causes a problem that the bonding process becomes complicated. Therefore, for example, in Japanese Patent Application Laid-Open No. 60-70749 (Patent Document 3), a housing cover, which is a holding plate, is disposed on a semiconductor element with a resin block of Teflon (registered trademark), which is an insulating material, interposed therebetween. Yes. And the presser plate presses the upper and lower solder layers of the semiconductor element to strengthen its durability.

JP 2008-277335 A JP 2008-300792 A JP-A-60-70749

  However, when only the pressing plate is used as in JP-A-60-70749, the downward pressing force may not be sufficient.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can easily suppress the occurrence of cracks at the center of the solder by further increasing the downward pressing force. That is.

  The semiconductor device of the present invention includes a housing, a semiconductor element, a pressing plate, and a pushing member. The housing includes an insulating substrate. The semiconductor element is bonded to one main surface of the insulating substrate by solder. The pressing plate is arranged on one main surface side opposite to the surface bonded to the insulating substrate in the semiconductor element so as to overlap the central portion of the semiconductor element in plan view. The pressing member can press the pressing plate to the semiconductor element side from the one main surface side opposite to the side where the semiconductor element is located. The pressing member can press the pressing plate toward the semiconductor element while being fixed to the housing.

  According to the present invention, the pressing member presses the pressing plate so that the semiconductor element and the insulating substrate are more closely attached. Thereby, since it controls so that the thickness of the solder between an insulating substrate and a semiconductor element does not increase, the vertical crack of a solder center part can be suppressed. For this reason, generation | occurrence | production of the crack of a solder center part can be suppressed, without passing through a complicated process.

1 is a schematic perspective view showing a configuration of a power module according to a first embodiment. It is a schematic sectional drawing which shows the structure of the part which follows the II-II line | wire of FIG. FIG. 6 is a schematic perspective view showing a configuration of a power module according to a second embodiment. It is a schematic sectional drawing which shows the structure of the part which follows the IV-IV line | wire of FIG. FIG. 6 is a schematic perspective view showing a configuration of a power module according to a third embodiment. It is a schematic sectional drawing which shows the structure of the part which follows the VI-VI line of FIG. FIG. 6 is a schematic perspective view showing a configuration of a power module according to a fourth embodiment. It is a schematic sectional drawing which shows the structure of the part which follows the VIII-VIII line of FIG. FIG. 10 is a schematic perspective view showing a configuration of a power module according to a fifth embodiment. It is a schematic sectional drawing which shows the structure of the part which follows the XX line of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, the configuration of a power module as a semiconductor device of the present embodiment will be described with reference to FIGS.

  1 is a perspective view of the semiconductor device of the present embodiment, and FIG. 2 is a cross-sectional view of the semiconductor device of the present embodiment. In FIG. Is omitted from the viewpoint of making the drawing easier to see. The same applies to the subsequent perspective views.

  Referring to FIGS. 1 and 2, a completed product of power module 100 as a semiconductor device according to the present embodiment includes a base plate 10, an insulating substrate 13, solder 15, a semiconductor element 16, a pressing plate 18, It mainly has a pressing plate pressing member 19 and a wire 20. Further, in the power module 100, each member described above is housed in the case portion 21.

  The base plate 10 is, for example, a flat plate member having, for example, a rectangular shape in plan view, having one main surface 10a facing the upper side in FIG. 2 and the other main surface 10b facing the lower side in FIG. . The base plate 10 is preferably formed of, for example, copper, but may be formed of aluminum in addition to copper.

The insulating substrate 13 has a ceramic substrate 131, a circuit pattern 132, and a heat dissipation copper foil portion 133. The ceramic substrate 131 is a flat plate member made of aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ) or the like, and one and the other main surfaces have, for example, a rectangular shape in plan view. . A circuit pattern 132 is formed on one main surface of the ceramic substrate 131, that is, the upper main surface in FIG. This is a conductive thin film as a circuit for inputting / outputting electric signals to / from the semiconductor element 16 and is formed of, for example, copper. A heat radiating copper foil 133 is formed on the other main surface of the ceramic substrate 131, that is, on the lower main surface of FIG. This is a conductive thin film for transmitting heat generated from the semiconductor element 16 or the like to the lower base plate 10 side in the figure, and is made of, for example, copper. Circuit pattern 132 may also be formed on the other main surface of ceramic substrate 131. The circuit pattern 132 and the heat dissipation copper foil part 133 are joined to the ceramic substrate 131 by brazing, for example.

  The insulating substrate 13 has one main surface 13a of the whole, that is, the upper main surface of, for example, the circuit pattern 132 of FIG. 1, and the other main surface 13b of the whole, that is, for example, the lower side of the heat dissipation copper foil portion 133 of FIG. Main surface.

  One main surface 10 a of the base plate 10 and the other main surface 13 b of the insulating substrate 13, that is, the heat-dissipating copper foil portion 133 are joined by solder 11. Further, one main surface 13a of the insulating substrate 13, that is, the circuit pattern 132, and the semiconductor element 16 are joined by solder 15, that is, by die bonding.

  The heat generation density of the semiconductor element 16 increases as the development of miniaturization proceeds. For this reason, the heat resistance and heat dissipation of the member 15 on which the semiconductor element 16 is mounted, in particular, the solder 15 disposed immediately below the semiconductor element 16 and joining it are important.

  Since the solders 11 and 15 are required to be lead-free and have high heat resistance, tin (Sn) solder is used. In addition, tin solders 11 and 15 are added with antimony (Sb), silver (Ag), copper (Cu), etc. from the viewpoint of having stress relaxation properties, heat resistance and fatigue strength, It is preferred that The solders 11 and 15 having the above composition are reflowed together with a material to be joined such as the semiconductor element 16, thereby joining the insulating substrate 13 and the semiconductor element 16 to each other.

  As the bonding material for die bonding, in addition to the solder 15, for example, an alloy such as copper-tin bonded by TLP bonding (transitional liquid phase sintering method) may be used. Silver which is a sintered type bonding material using nanoparticles may be used. However, by using solder, cost reduction and process stability can be ensured.

  The semiconductor element 16 is a member equipped with a power device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). It is a chip-shaped member formed by the above, and has a rectangular shape or a square shape in plan view. The semiconductor element 16 has, for example, one main surface 16a facing the upper side in FIG. 2 and the other main surface 16b facing the lower side in FIG.

When silicon or silicon carbide is used as the material of the semiconductor element 16, the linear expansion coefficient is 3 × 10 ⁻⁶ / K or more and 5 × 10 ⁻⁶ / K or less. From this viewpoint, the linear expansion coefficient of the semiconductor element 16 is preferably 3 × 10 ⁻⁶ / K or more and 5 × 10 ⁻⁶ / K or less.

It is preferable that the insulating substrate 13 and the semiconductor element 16 joined by the solder 15 have a small difference in linear expansion coefficient. In this way, the shear stress to the solder 15 constituting the power module 100 can be reduced by joining the semiconductor element 16 to the insulating substrate 13. Specifically, for example, when the linear expansion coefficient of the semiconductor element 16 is 3 × 10 ⁻⁶ / K or more and 5 × 10 ⁻⁶ / K or less, the linear expansion coefficient of the insulating substrate 13 is 10 × 10 ⁻⁶ / K or less. It is preferable that Here, the linear expansion coefficient of the insulating substrate 13 is an overall linear expansion coefficient of the ceramic substrate 131, the circuit pattern 132, and the heat-dissipating copper foil portion 133. For this reason, in order to make the linear expansion coefficient of the insulating substrate 13 within the above numerical range, it is preferable to adjust the ratio of the thickness of each of the ceramic substrate 131, the circuit pattern 132, and the copper foil portion 133 for heat dissipation. By adjusting the thickness of each layer such as the ceramic substrate 131 to adjust the linear expansion coefficient of the entire insulating substrate 13, the value of the linear expansion coefficient of the insulating substrate 13 can be brought close to the value of the linear expansion coefficient of the semiconductor element 16. it can.

  For example, it is preferable that the thickness of the aluminum nitride ceramic substrate 131 is 0.635 mm, the thickness of the copper circuit pattern 132 is 0.32 mm, and the thickness of the copper radiating copper foil portion 133 is 0.32 mm. In this way, the difference in the coefficient of linear expansion between the semiconductor element 16 and the insulating substrate 13 is sufficiently small, so that the solder 15 that joins these is a crack extending in the direction along the joint surface with the semiconductor element 16 and the like. It is possible to suppress the occurrence of certain lateral cracks.

  The pressing plate 18 is disposed on one main surface 16a opposite to the surface bonded to the insulating substrate 13 in the semiconductor element 16, that is, on the upper main surface of the semiconductor element 16 in FIG. It is arranged so as to overlap the central part. Specifically, the presser plate 18 has a flat surface in which at least a part of one main surface 18a, for example, in a rectangular shape in plan view is at least a part of a central portion of one main surface 16a, for example, a rectangular shape, of the semiconductor element 16. It arrange | positions so that it may overlap in view. The pressing plate 18 is disposed on one main surface 16a side of the semiconductor element 16, that is, on the upper side in FIG.

  Here, the central portion of the semiconductor element 16 refers to a direction in which one main surface 16a extends along the direction in which the wire 20 in FIG. 1 extends from the central point on the one main surface 16a of the semiconductor element 16. The distance in the direction perpendicular to the sheet of FIG. 2 is the entire region in which one main surface 16a of the semiconductor element 16 is within 15% of the dimension in the direction along the extension of the wire 20.

  However, as shown in FIGS. 1 and 2, the pressing plate 18 basically has one main surface 16a of the semiconductor element 16 as a whole along the one main surface 16a and in the direction intersecting the direction in which the wire 20 extends. It extends to overlap. Therefore, if this is combined with the fact that the distance in the direction extending along the wire 20 from the center point of the semiconductor element 16 is within 15% of the overall dimension of the one main surface 16a as described above, the semiconductor element The center portion of 16 can be said to be a region in which the area of one main surface 16a is 30% with the center point of the semiconductor element 16 as the center. The pressing plate 18 may have a size that covers the region outside the central portion of the semiconductor element 16.

  The insulating layer 17 is sandwiched between the semiconductor element 16 and the pressing plate 18 in order to suppress electrical continuity. That is, the insulating layer 17 is disposed so that at least a part thereof overlaps at least a part of both the semiconductor element 16 and the pressing plate 18. The insulating layer 17 is, for example, a flat plate member having a rectangular shape in plan view, and is formed of a material such as heat-resistant ceramic, epoxy resin, or Teflon (registered trademark). The dimension of the long side direction in plan view of the insulating layer 17 is that of the guard ring formed on one main surface 16a along the one main surface 16a of the semiconductor element 16 and in the direction intersecting the direction in which the wire 20 extends. It is preferable that the dimension fits inside the outer frame without overlapping the guard ring. The dimension of the insulating layer 17 in the short side direction in plan view is surrounded by each of a plurality of wires 20 to be described later and one main surface 16a of the semiconductor element 16 to which one end and the other end thereof are connected. It is preferable that the insulating layer 17 be dimensioned to fit inside the loop formed as described above.

  The pressing plate 18 has, for example, one main surface 18a facing the upper side in FIG. 2 and the other main surface 18b facing the lower side in FIG. 2 on the opposite side, and has a rectangular shape in plan view, for example. It is. The pressing plate 18 is preferably formed of any one selected from the group consisting of metal materials such as copper or aluminum, ceramics, and resin materials. However, the presser plate 18 is more preferably formed of a highly rigid material. It is preferable that the presser plate 18 is disposed so that the long side direction of the presser plate 18 in plan view corresponds to a direction along the one main surface 16a and intersecting the direction in which the wire 20 extends. Further, the dimension in the long side direction is a dimension that overlaps with the whole of one main surface 16a of the semiconductor element 16 in the direction along the one main surface 16a and intersecting the direction in which the wire 20 extends as described above. preferable. In other words, the dimension in the long side direction in plan view of the pressing plate 18 is preferably longer than the one main surface 16a in the direction along the one main surface 16a and intersecting the direction in which the wire 20 extends. However, the dimension of the holding plate 18 in the long side direction in plan view is such that at least the outside of the wire 20 arranged at one end and the outside of the wire 20 arranged at the other end of the array of the plurality of wires 20. It is preferable that the dimension is such that it can overlap with a pressing plate pressing member 19 to be described later disposed on both sides. In other words, it is preferable that the long side direction of the pressing plate 18 basically has a length that allows the semiconductor element 16 to be straddled in plan view. What is necessary is just to have a dimension which can straddle the arrangement | sequence of 20 and the pressing plate pressing member arrange | positioned at the both ends of the arrangement.

  Further, it is preferable that the pressing plate 18 is arranged so that the short side direction of the pressing plate 18 in plan view corresponds to the direction along the one main surface 16a and the direction in which the wire 20 extends. The dimension in the short side direction is the same as the dimension in the short side direction in plan view of the insulating layer 17. Each of the plurality of wires 20 and one main element of the semiconductor element 16 to which one end and the other end thereof are connected. It is preferable that the pressing plate 18 fits inside a loop formed so as to be surrounded by the surface 16a and the like. That is, the insulating layer 17 and the pressing plate 18 are formed by a surface sandwiched between a point on the surface connected to one end of each of the plurality of wires 20 and a point on the surface connected to the other end of the wire 20, and the wire The short side dimension is such that it is housed inside a loop formed by being surrounded by 20. Therefore, neither the insulating layer 17 nor the pressing plate 18 is in contact with each of the plurality of wires 20.

  As an example, the thickness of the pressing plate 18 in a plan view is preferably set to 500 μm or more from the viewpoint of securing the strength of the flat plate member constituting the pressing plate 18. Moreover, it is preferable to provide the length of the pressing plate 18 in the short side direction, for example, 1 mm or more. As described above, the pressing plate 18 has a thickness that is about half of the length in the short side direction. The power module 100 of the present embodiment has a flat plate-shaped pressing plate 18 having such dimensions and a wire 20 that can be straddled across the pressing plate 18 with a space therebetween. ing.

  The insulating layer 17 and the one main surface 16a of the semiconductor element 16 that can come into contact with the insulating layer 17 do not necessarily have to be joined to each other, but are preferably fixed to each other with a joining strength of a temporary fixing degree. . Thereby, the positional accuracy of the wire 20 and the case part 21 which are mentioned later is improved. The insulating layer 17 and the other main surface 18b of the pressing plate 18 that can come into contact with the insulating layer 17 do not necessarily have to be joined to each other. preferable.

  The plurality of wires 20 are thin line members for electrically connecting an IGBT, a MOSFET, and the like mounted on one main surface 16 a of the semiconductor element 16 and the outside of the semiconductor element 16. In FIG. 1 and FIG. 2, as an example, five wires 20 are spaced apart from each other, and one end of each of them is connected to one main surface 16a of the semiconductor element 16 and the other end. Is connected on the circuit pattern 132 on one main surface 13a of the insulating substrate 13. Thereby, each of the five wires 20 electrically connects the semiconductor element 16 and the circuit pattern 132. Each wire 20 extends along the short side direction of the pressing plate 18 and is disposed so as to straddle the pressing plate 18 in the short side direction of the pressing plate 18. That is, each wire 20 extends so that the pressing plate 18 is disposed between the semiconductor element 16 and the wire 20 and passes directly above the pressing plate 18 without contacting the pressing plate 18. . However, the connection mode of the wire 20 is not limited to the above mode. The wire 20 is preferably connected onto the semiconductor element 16 after the placement of the pressing plate 18 is completed.

  In general, the wire 20 is preferably formed of aluminum or copper, and the cross section thereof is preferably a circle having a diameter of, for example, about 100 μm to 400 μm. Such a wire 20 is connected to the said location by the wedge bonding using an ultrasonic wave and a pressure, for example.

  At least one of the one end or the other end of the wire 20 is preferably connected to a region close to the central portion of one main surface 16 a of the semiconductor element 16, that is, a region adjacent to the central portion of the semiconductor element 16. . Thus, it is preferable that the one end or the other end of the wire 20, that is, the portion where the wire 20 is connected to the one main surface 16 a of the semiconductor element 16, etc., be located as close to the holding plate 18 as possible. For this reason, the insulating layer 17 and the pressing plate 18 may have a structure in which the corners of the ridges near the region where the wires 20 pass are removed and the corners are tapered.

  The power module 100 includes a case portion 21 that houses a laminated structure composed of the base plate 10, the insulating substrate 13, the semiconductor element 16, and the like. The case portion 21 together with the insulating substrate 13 constitutes a housing of the power module 100 here. As shown in FIG. 2, the case portion 21 has, for example, a rectangular parallelepiped box shape whose planar shape is a rectangle. The case portion 21 accommodates a part of one main surface 10 a side of the base plate 10, the insulating substrate 13, the semiconductor element 16, the pressing plate 18, and the pressing plate pressing member 19. The surface 10b side and the other part of the pressing plate pressing member 19 may be exposed to the outside.

  The case portion 21 is filled with a sealing resin 22. The sealing resin 22 is for preventing discharge in the case portion 21, and is preferably a silicone gel, for example. However, the sealing resin 22 may be a potting resin such as an epoxy resin.

  In a direction intersecting with the extending direction of the plurality of wires 20 in a plan view, that is, a direction in which the plurality of wires 20 are arranged, a pair of pressing plate presses so as to overlap, for example, regions adjacent to one end and the other end of the pressing plate 18 A member 19 (pushing member) is disposed. However, the number of pressing plate pressing members 19 is not limited to this. The pressing plate pressing member 19 is disposed on one main surface 18a side, that is, the upper side in FIG. 2, which is the opposite side of the pressing plate 18 from the lower side where the semiconductor element 16 is located.

  For example, as shown in FIGS. 1 and 2, when the pressing plate 18 has a longer dimension than the semiconductor element 16 in the direction in which the plurality of wires 20 are arranged, the pressing plate pressing member 19 does not overlap the semiconductor element 16. In other words, it is arranged at a position overlapping with the circuit pattern 132 arranged on the outside of the semiconductor element 16, for example, in a plane.

  Specifically, a bolt or a screw made of a normal steel material is used as the pressing plate pressing member 19, and in the direction in which the base plate 10, the insulating substrate 13, the semiconductor element 16, and the like are stacked, that is, in the vertical direction in FIG. It extends. The upper end portion of the pressing plate pressing member 19 in FIGS. 1 and 2 is the head of a bolt or screw and can be exposed to the outside of the case portion 21. Further, the region other than the bolt or screw head constituting the pressing plate pressing member 19 can be accommodated in the case portion 21 as shown in FIG.

  As described above, the region other than the head portion of the pressing plate pressing member 19 penetrates the uppermost member of the case portion 21, and a part of the head portion of the pressing plate pressing member 19 becomes the uppermost member of the case portion 21. In contact. In this way, the pressing plate pressing member 19 is fixed to the case portion 21 which is a part of the housing. Thereby, the positional accuracy between the pressing plate pressing member 19 and the case portion 21 can be increased.

  For example, the presser plate pressing member 19 is turned and tightened, and the presser plate pressing member 19 applies a pressing force downward in FIG. 2, so that the lower end portion of the presser plate pressing member 19 is on one main surface 18 a of the presser plate 18. Thus, the pressing plate 18 can be pressed from the upper side of FIG. 2 toward the lower side of FIG. 2, that is, the semiconductor element 16 side. As a result, the semiconductor element 16 and the members below the semiconductor element 16 receive downward pressure in FIG. 2, and the solder 15 and 11 are suppressed from becoming excessively thick in the vertical direction in FIG. 2.

  The pressure with which the pressing plate pressing member 19 presses the pressing plate 18 downward is preferably higher. However, from the viewpoint of suppressing the solder 15 and 11 from extending in the vertical direction (vertical direction in FIG. 2), that is, from increasing the thickness of the solder 15 and 11, each of the pair of pressing plate pressing members 19 is at least about 1 MPa. It is preferable to apply the pressure downward.

  As described above, the pressing plate pressing member 19 is fixed to the case portion 21 which is a part of the casing (including the insulating substrate 13), and the pressing plate 18 is placed on the semiconductor element 16 side, that is, the lower side in FIG. It can be pressed.

  In this embodiment, a pressing plate 18 made of a conductive material is formed, and an insulating layer 17 for avoiding electrical conduction between the pressing plate 18 and the semiconductor element 16 is formed between the pressing plate 18 and the semiconductor element 16. It is sandwiched between. However, in the present embodiment, a pressing plate 18 made of an insulating material such as ceramics is disposed directly on the semiconductor element 16 without sandwiching the insulating layer 17 so that the semiconductor element 16 can be pressed. It may be.

  Here, the effects of the present embodiment will be described while explaining the background of the present embodiment.

  First, in general, a power module is used to efficiently control electric power of industrial equipment, automobiles, railways, and the like. Power modules, which are key parts for energy saving, are required to be smaller, more efficient, and have higher output density. A semiconductor element made of silicon carbide (SiC) or the like and capable of high temperature operation has been developed. Along with this, high heat resistance and high reliability are increasingly required for various components around the semiconductor element such as solder for mounting, an insulating substrate as an insulating member, and a sealing resin.

  In general, a power module has an insulating substrate bonded to one main surface of a base plate such as copper or aluminum with a bonding material such as solder, and a semiconductor using a bonding material such as solder on one main surface of the insulating substrate. The element is mounted. On one main surface of the semiconductor element, wiring for inputting / outputting a control signal and a main current is attached, and the periphery of these semiconductor elements and the insulating substrate is sealed with resin in order to maintain insulation. Yes.

  In the semiconductor element included in the power module, the main current is switched at high speed. For this reason, in the power module, the mounting solder around the semiconductor element is repeatedly exposed to a high temperature state and a low temperature state, and the solder is likely to cause defects such as voids, cracks, and peeling due to temperature stress. Become.

  Therefore, as a method of confirming the reliability of the solder 15 to which the semiconductor element 16 is bonded and the power module 100 as shown in FIGS. 1 and 2, there is a power cycle test. For example, in the power module 100 of FIGS. 1 and 2 described above, the power cycle test 100 is performed by intermittently passing a current through the semiconductor element 16, thereby causing the semiconductor element 16 and its surrounding solder 15, the insulating substrate 13, and the base plate. 10 is a test in which local and steep temperature stress is repeatedly applied to 10. Each member subjected to such temperature stress repeatedly expands and contracts, a stress load is generated, and the joint portion such as the solder 15 is deteriorated.

  Of the deterioration of the solder 15 caused by the above-described temperature stress, the lateral cracks spreading from the outer peripheral part to the central part in the plan view of the solder 15 are the semiconductor element 16 and the insulating substrate joined to the solder 15 as described above. It can suppress by making the difference of a linear expansion coefficient with 13 small. However, even if the difference in the coefficient of linear expansion between the semiconductor element 16 and the insulating substrate 13 is reduced and lateral cracking of the solder 15 is suppressed, vertical cracks are generated from the center of the solder 15 by the power cycle test. Longitudinal cracks in the solder 15 are caused by many fine voids generated in the solder 15 due to the aggregation of additives and the growth of crystal grain boundaries in the solder 15, which are connected along the direction perpendicular to the main surface of the solder 15. It is thought that it is formed by. Cracks due to vertical cracks may spread from the central portion in the plan view of the solder 15 toward the outer peripheral portion in a mesh shape. If this happens, it will cause an increase in the thermal resistance and electrical resistance of the solder 15. This causes cracks and lift-off of the wire 20 and causes the power module 100 to malfunction due to excessive heat generation of the semiconductor element 16.

  In addition, when a vertical crack occurs in the solder 15, it has been confirmed that the thickness of the solder 15 increases as compared to the original thickness at which the solder 15 is joined. For this reason, generation | occurrence | production of the vertical crack of the solder 15 can be suppressed by suppressing the increase in the thickness of the solder 15 compulsorily.

  Therefore, in the power module 100 of the present embodiment, the pressing plate 18 is disposed on one main surface 16a of the semiconductor element 16 so as to overlap at least the central portion in plan view, and the pressing plate 18 is also shown in FIG. 2 has a structure that can be pressed toward the semiconductor element 16 side, that is, the lower side of FIG. For this reason, when the pressing plate 18 presses the semiconductor element 16 and the insulating substrate 13 downward by the pressing plate pressing member 19, a compressive force in the thickness direction is applied to the solder 15 between the semiconductor element 16 and the insulating substrate 13. Join.

  Thus, in this embodiment, not only the pressing plate 18 applies a compressive force in the thickness direction to the solder 15, but the pressing plate pressing member 19 has a role of assisting the pressing of the pressing plate 18 downward. Yes. In this way, both the pressing plate 18 and the pressing plate pressing member 19 apply a pressing force to the solder 15, thereby preventing an increase in the thickness of the solder 15, thereby starting the central portion of the solder 15. The occurrence of vertical cracks can be suppressed. If the solder 15 does not cause vertical cracks, the path through which heat generated during operation of the semiconductor element 16 is dissipated through the solder 15 toward the lower base plate 10 in FIG. 2 is not blocked. For this reason, excessive heat generation of the semiconductor element 16 can be suppressed, and failure of the power module 100 can be suppressed. As a result, the life of the power module 100 can be extended.

  In particular, the pressing plate 18 of the present embodiment is disposed so as to overlap the central portion of the semiconductor element 16 in plan view. For this reason, for example, a region other than the central portion in plan view of the semiconductor element 16 can be configured not to be directly pressed by the pressing plate 18 from directly above. Therefore, it is possible to secure a wide region for connecting the wire 20 to a region other than the central portion of the semiconductor element 16, and without reducing the degree of design freedom on the one main surface 16 a of the semiconductor element 16. The vertical cracking of the solder 15 by 18 can be suppressed. For this reason, the versatility in the mounting aspect of the wire 20 can be improved.

  The power module 100 according to the present embodiment also includes a wire 20 that connects the circuit pattern 132 formed on one main surface 13 a of the insulating substrate 13 and the semiconductor element 16. The wire 20 extends so as to pass directly above the pressing plate 18 with a space from the pressing plate 18 so that the pressing plate 18 is disposed between the semiconductor element 16 and the wire 20. The pressing plate 18 can apply a pressing force to the semiconductor element 16 without receiving interference between the semiconductor element 16 and the wire 20. That is, the vertical cracking of the solder 15 by the pressing plate 18 can be suppressed without reducing the design freedom on the one main surface 16a of the semiconductor element 16.

(Embodiment 2)
First, the configuration of a power module as a semiconductor device of the present embodiment will be described with reference to FIGS.

  3 is a perspective view of the semiconductor device of the present embodiment, and FIG. 4 is a cross-sectional view in the depth direction of FIG. 3, that is, the long side direction in plan view. Referring to FIG. 3 and FIG. 4, the completed product of power module 200 as the semiconductor device of the present embodiment basically has the same configuration as that of power module 100, and thus the same elements are denoted by the same reference numerals. The description is not repeated. In the power module 200 of the present embodiment, as in the power module 100, the wire 20 connects the circuit pattern 132 on the one main surface 13a of the insulating substrate 13 and the semiconductor element 16. The wire 20 is not arranged so as to pass directly above the pressing plate 18, but is located in a region near one central portion of one main surface 16 a of the semiconductor element 16, that is, a region adjacent to the central portion of the semiconductor element 16. It is connected. In this respect, the present embodiment is structurally different from the first embodiment in which the wire 20 is connected so as to pass over the pressing plate 18 and straddle the pressing plate 18.

  In this embodiment, since the wire 20 does not pass right above the pressing plate 18, the pressing plate 18 may be arranged and fixed after the wire 20 is first connected to the semiconductor element 16, or the embodiment. Similarly to 1, the wire 20 may be connected after the placement of the presser plate 18 is completed first.

  As in the present embodiment, the wire 20 does not necessarily have to be configured to pass directly above the pressing plate 18. At least the wire 20 may be connected to a region adjacent to the pressing plate 18, that is, a region adjacent to the central portion of the semiconductor element 16 in plan view. By connecting the wire 20 near the pressing plate 18, the pressing plate 18 is arranged in a region where the current flowing through the wire 20 is concentrated and the temperature is likely to rise excessively. For this reason, when the pressing plate 18 prevents the thickness of the solder 15 from increasing, vertical cracks of the solder 15 are suppressed, and an increase in the thermal resistance of the solder 15 can be suppressed. Therefore, since the heat dissipation effect of the solder 15 can be maintained, the effect of dissipating a large amount of heat generated in the wire 20 on the solder 15 via the solder 15 can be maintained.

(Embodiment 3)
First, the configuration of a power module as a semiconductor device of the present embodiment will be described with reference to FIGS.

  FIG. 5 is a perspective view of the semiconductor device of the present embodiment, and FIG. 6 is a cross-sectional view in the width direction of FIG. 5, that is, the short side direction in plan view. Referring to FIGS. 5 and 6, the completed product of power module 300 as the semiconductor device of the present embodiment basically has the same configuration as power module 100, and thus the same components are denoted by the same reference numerals. The description is not repeated. However, the power module 300 according to the present embodiment is the power module according to the first embodiment in which the pressing plate pressing member 19 is fixed to the case portion 21 in that the pressing plate pressing member 19 is fixed to the insulating substrate 13. 100 is different in structure.

  That is, in the present embodiment, the size of the holding plate 18 in the long side direction in plan view is one main surface 16a with respect to the direction along one main surface 16a of the semiconductor element 16 and the direction in which the wire 20 extends. Longer than. That is, the pressing plate 18 has a length that can straddle the semiconductor element 16 in the long side direction in plan view. A pair of pressing plate pressing members 19 are arranged so as to overlap with the region adjacent to the one end and the other end in the long side direction of the pressing plate 18.

  As in the first embodiment, the pressing plate pressing member 19 is disposed on one main surface 18a side of the pressing plate 18, that is, on the upper side in FIG. The pressing plate pressing member 19 is arranged at a position outside the semiconductor element 16 so as not to overlap the semiconductor element 16, in other words, a position overlapping the circuit pattern 132 arranged outside the semiconductor element 16, for example.

  The region other than the head portion of the pressing plate pressing member 19 penetrates the pressing plate 18 and further passes through, for example, the circuit pattern 132 and the ceramic substrate 131 which are part of the insulating substrate 13 directly below the insulating plate 13. It has the structure fixed to. It is preferable that at least the pressing plate pressing member 19 has such a length that a part thereof can reach the ceramic substrate 131.

  That is, in the power module 300 of the present embodiment, the entire pressing plate pressing member 19 is disposed inside the case portion 21, and a part of its head as in the power module 100 of the first embodiment. Is not exposed to the outside of the case portion 21. Therefore, the pressing plate pressing member 19 is not fixed to the case portion 21. Then, the presser plate pressing member 19 is turned and tightened, for example, to apply a pressing force downward, so that the lower end portion of the presser plate pressing member 19 comes into contact with a part of the insulating substrate 13 (for example, the ceramic substrate 131). Thus, the pressing plate 18 fixed by the pressing plate pressing member 19 at its head can be pressed toward the lower side of FIG. 6, that is, the semiconductor element 16 side.

  In FIG. 6, the pressing plate pressing member 19 has a length that reaches the heat dissipation copper foil portion 133 of the insulating substrate 13. However, the length of the pressing plate pressing member 19 is not limited to this, and may be, for example, a length reaching the base plate 10. However, in the present embodiment, the pressing plate pressing member 19 is formed of an insulating material such as ceramic.

Next, the effect of this Embodiment is demonstrated.
In the present embodiment, the pressing plate pressing member 19 is fixed to the insulating substrate 13 without receiving interference from the case portion 21. For this reason, the positional accuracy between the pressing plate pressing member 19 and the case portion 21 is not required, and positioning when the pressing plate pressing member 19 is attached becomes easy. In the present embodiment, before placing the uppermost lid of the case portion 21, a defective portion or the like in the laminated structure of the base plate 10, the insulating substrate 13, the semiconductor element 16, and the like formed in the previous steps is visually confirmed. Therefore, management in manufacturing becomes easy.

(Embodiment 4)
First, the configuration of a power module as a semiconductor device of the present embodiment will be described with reference to FIGS.

  FIG. 7 is a perspective view of the semiconductor device of the present embodiment, and FIG. 8 is a cross-sectional view in the width direction of FIG. 7, that is, the short side direction in plan view. Referring to FIGS. 7 and 8, the completed product of power module 400 as the semiconductor device of the present embodiment basically has the same configuration as power module 100, and thus the same components are denoted by the same reference numerals. The description is not repeated. However, in the power module 400 of the present embodiment, one end of each of the plurality of wires 20 is connected to one main surface 18 a of the pressing plate 18. The other end of each wire is connected to a circuit pattern 132 corresponding to one main surface 13a, for example, as in the first embodiment. Further, the point that the pressing plate 18 is arranged on one main surface 16a side, that is, the upper side of the semiconductor element 16 so as to overlap with the central portion in plan view of the semiconductor element 16 is the same as that of the first embodiment. A conductive layer 23 as a bonding material made of solder or the like is sandwiched between the pressing plate 18 instead of the insulating layer 17. That is, it is preferable that the semiconductor element 16 and the pressing plate 18 are joined by solder. Also in this case, since the conductive layer 23 electrically connects the semiconductor element 16 and the pressing plate 18, the conductive layer 23 is connected to one main surface 16 a of the semiconductor element 16 and the other main surface 18 b of the pressing plate 18. It is sandwiched so that it touches both sides.

  From the viewpoint of electrically connecting the pressing plate 18 and the semiconductor element 16, the pressing plate 18 is preferably formed of a conductive material such as copper or aluminum. However, since one end of the wire 20 is connected to one main surface 18 a of the pressing plate 18, it is preferable that nickel plating is applied to the surface of the pressing plate 18. The present embodiment is different from the first embodiment in the above points.

  Also in the present embodiment, as in the power module 300 of the third embodiment, the pressing plate pressing member 19 may be fixed to the insulating substrate 13. In the present embodiment, the pressing plate pressing member 19 is formed of an insulating material such as ceramic as in the third embodiment.

Next, the effect of this Embodiment is demonstrated.
The semiconductor element 16 and the circuit pattern 132 can be electrically connected by connecting one end of the wire 20 to one main surface 18a of the pressing plate 18 as in the present embodiment. This is because the pressing plate 18 of the present embodiment is formed of a metal material, and the conductive layer 23 in contact with both is disposed between the pressing plate 18 and the semiconductor element 16.

  In the power module 400 of the present embodiment, the wire 20 is connected to one main surface 18a of the pressing plate 18 and the wire 20 is connected to the vicinity of the pressing plate 18, so that the pressing plate 18 is connected to the wire 20. The flowing current is concentrated and the temperature is likely to rise excessively. For this reason, when the pressing plate 18 prevents the thickness of the solder 15 from increasing, vertical cracks of the solder 15 are suppressed, and an increase in the thermal resistance of the solder 15 can be suppressed. Therefore, since the heat dissipation effect of the solder 15 can be maintained, the effect of dissipating a large amount of heat generated in the wire 20 on the solder 15 via the solder 15 can be maintained.

(Embodiment 5)
First, the configuration of a power module as a semiconductor device of this embodiment will be described with reference to FIGS.

  FIG. 9 is a perspective view of the semiconductor device of the present embodiment, and FIG. 10 is a cross-sectional view in the width direction of FIG. 9, that is, the short side direction in plan view. Referring to FIGS. 9 and 10, the completed product of power module 500 as the semiconductor device of the present embodiment basically has the same configuration as that of power module 100, and thus the same elements are denoted by the same reference numerals. The description is not repeated. However, in the power module 500 of the present embodiment, a through-hole 24 that penetrates the presser plate 18 is formed so as to reach from the one main surface 18a of the presser plate 18 to the other main surface 18b. The planar shape of the through hole 24 is rectangular in FIG. 9, but is not limited to this and is arbitrary. The through-hole 24 penetrates not only the pressing plate 18 but also the insulating layer 17 immediately below it, and reaches one main surface 16 a of the semiconductor element 16. One end of each of the plurality of wires 20 is connected to one main surface 16 a of the semiconductor element 16 through the through hole 24. The other end of each wire is connected to a circuit pattern 132 corresponding to one main surface 13a, for example, as in the first embodiment.

  In the present embodiment, the area where the pressing plate 18 applies a pressing force to the semiconductor element 16 or the like in plan view is reduced by the amount of the pressing plate 18 having the through hole 24. However, in the present embodiment, as in the other embodiments, the central portion of the semiconductor element 16, that is, the region of 30% or more of the area of the one main surface 16 a of the semiconductor element 16 directly applies the pressing force of the pressing plate 18. It is preferable to receive. Accordingly, the pressing plate 18 of the present embodiment is a region that overlaps the semiconductor element 16 in a plan view by increasing the width in the direction in which the wire 20 extends, for example, compared to the pressing plate 18 of the other embodiments. Is preferably adjusted to be 30% or more of one main surface 16a.

Next, the effect of this Embodiment is demonstrated.
As in the present embodiment, one end of the wire 20 passes through the through hole 24 and is connected to one main surface 16a of the semiconductor element 16, so that the semiconductor element 16 directly connected to the wire 20 having a large amount of heat generation is connected. The holding plate 18 is disposed so as to surround the region in plan view. Therefore, the press plate 18 prevents an increase in the thickness of the solder 15, thereby suppressing vertical cracks in the solder 15 and suppressing an increase in the thermal resistance of the solder 15. Therefore, since the heat dissipation effect of the solder 15 can be maintained, the effect of dissipating a large amount of heat generated in the wire 20 on the solder 15 via the solder 15 can be maintained.

  Also in the present embodiment, for example, in order to provide the pressing plate 18 that overlaps the central portion of the semiconductor element 16 in plan view (the area from the central point is 30% or more of the area of the one main surface 16a), It is necessary to increase the width of the plate 18 in the extending direction of the wire 20. As a result, since the region where the pressing plate 18 presses the semiconductor element 16 and the like can be widened particularly in the direction in which the wire 20 extends, the pressing force is distributed over a wide range, and the thickness of the solder 15 is increased more reliably. Longitudinal cracks can be suppressed.

  Furthermore, even if the aspect of the present embodiment is applied, the position where one end of the wire 20 is connected in a plan view is compared to the case where the wire 20 straddles the pressing plate 18 as in the first embodiment, for example. It will change slightly, but it will not change greatly. For this reason, it is not necessary to redesign the connection mode of the wire 20 of the present embodiment, and the power module 500 of the present embodiment can be obtained by diverting the module design similar to that of the first embodiment.

  You may apply so that the characteristic described in each embodiment described above may be combined suitably in the range with no technical contradiction.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 10 Base plate, 10a, 13a, 16a, 18a One main surface, 10b, 13b, 16b, 18b The other main surface, 11, 15 Solder, 12 Heat dissipation copper foil part, 13 Insulating substrate, 16 Semiconductor element, 17 Insulating layer , 18 pressure plate, 19 pressure plate pressing member, 20 wire, 21 case portion, 22 sealing resin, 23 conductive layer, 24 through hole, 100, 200, 300, 400, 500 power module, 131 ceramic substrate, 132 circuit Pattern, 133 Copper foil part for heat dissipation.

Claims (9)

A housing including an insulating substrate;
A semiconductor element joined by solder on one main surface of the insulating substrate;
A pressing plate disposed on one main surface side opposite to the surface bonded to the insulating substrate in the semiconductor element so as to overlap a central portion in plan view of the semiconductor element;
A pressing member capable of pressing the pressing plate against the semiconductor element side from one main surface side opposite to the side where the semiconductor element is located of the pressing plate;
The semiconductor device, wherein the pressing member is capable of pressing the pressing plate toward the semiconductor element while being fixed to the housing. The semiconductor device according to claim 1, wherein the insulating substrate has a linear expansion coefficient of 10 × 10 ⁻⁶ / K or less. The semiconductor device according to claim 1, wherein a linear expansion coefficient of the semiconductor element is 3 × 10 ⁻⁶ / K or more and 5 × 10 ⁻⁶ / K or less. The housing further includes a case portion capable of storing the semiconductor element,
The semiconductor device according to claim 1, wherein the push-in member is fixed to the case portion.   The semiconductor device according to claim 1, wherein the pushing member is fixed to the insulating substrate.   The semiconductor device according to claim 1, further comprising a wire connecting a circuit pattern formed on the one main surface of the insulating substrate and the semiconductor element.   7. The wire according to claim 6, wherein the wire extends so as to pass right above the pressure plate with a space from the pressure plate so that the pressure plate is disposed between the semiconductor element and the wire. Semiconductor device. A conductive layer sandwiched between the semiconductor element and the pressing plate so as to be in contact with both the semiconductor element and the pressing plate;
The holding plate is made of a conductive material,
The semiconductor device according to claim 6, wherein one end of the wire is connected to the one main surface of the pressing plate. A through hole is formed through the pressing plate so as to reach from the one main surface of the pressing plate to the other main surface opposite to the one main surface,
The semiconductor device according to claim 6, wherein one end of the wire is connected to the one main surface of the semiconductor element through the through hole.

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