JP2011048838A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2011048838A5 JP2011048838A5 JP2010214177A JP2010214177A JP2011048838A5 JP 2011048838 A5 JP2011048838 A5 JP 2011048838A5 JP 2010214177 A JP2010214177 A JP 2010214177A JP 2010214177 A JP2010214177 A JP 2010214177A JP 2011048838 A5 JP2011048838 A5 JP 2011048838A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- slave
- master
- requested
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 4
- 230000003111 delayed effect Effects 0.000 claims 3
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/055,922 | 2005-02-10 | ||
| US11/055,922 US7246188B2 (en) | 2005-02-10 | 2005-02-10 | Flow control method to improve bus utilization in a system-on-a-chip integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007555297A Division JP4861339B2 (ja) | 2005-02-10 | 2006-02-09 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011048838A JP2011048838A (ja) | 2011-03-10 |
| JP2011048838A5 true JP2011048838A5 (enExample) | 2011-04-21 |
| JP5456632B2 JP5456632B2 (ja) | 2014-04-02 |
Family
ID=36588894
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007555297A Active JP4861339B2 (ja) | 2005-02-10 | 2006-02-09 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
| JP2010214177A Expired - Fee Related JP5456632B2 (ja) | 2005-02-10 | 2010-09-24 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
| JP2011197213A Expired - Fee Related JP5456743B2 (ja) | 2005-02-10 | 2011-09-09 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007555297A Active JP4861339B2 (ja) | 2005-02-10 | 2006-02-09 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011197213A Expired - Fee Related JP5456743B2 (ja) | 2005-02-10 | 2011-09-09 | スイッチマトリックス経由のデータ転送を改善するフロー制御方法 |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US7246188B2 (enExample) |
| EP (1) | EP1846831B1 (enExample) |
| JP (3) | JP4861339B2 (enExample) |
| KR (1) | KR100932408B1 (enExample) |
| CN (1) | CN100595744C (enExample) |
| AT (1) | ATE491993T1 (enExample) |
| DE (1) | DE602006018862D1 (enExample) |
| ES (1) | ES2355054T3 (enExample) |
| IL (1) | IL185067A0 (enExample) |
| MX (1) | MX2007009732A (enExample) |
| PL (1) | PL1846831T3 (enExample) |
| WO (1) | WO2006086732A1 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2407662B (en) * | 2003-11-03 | 2006-02-22 | Compxs Uk Ltd | Two way serial communication |
| US7788625B1 (en) * | 2005-04-14 | 2010-08-31 | Xilinx, Inc. | Method and apparatus for precharacterizing systems for use in system level design of integrated circuits |
| DE102005026436B4 (de) * | 2005-06-08 | 2022-08-18 | Austriamicrosystems Ag | Schnittstellenanordnung, insbesondere für ein System-on-Chip, und deren Verwendung |
| US20070255874A1 (en) * | 2006-04-28 | 2007-11-01 | Jennings Kevin F | System and method for target device access arbitration using queuing devices |
| US7908412B2 (en) * | 2006-05-10 | 2011-03-15 | Microsoft Corporation | Buffer passing mechanisms |
| KR100854973B1 (ko) * | 2007-02-13 | 2008-08-28 | 삼성전자주식회사 | 버스 매트릭스를 포함하는 시스템 |
| DE102007015122A1 (de) * | 2007-03-29 | 2008-10-02 | Bayerische Motoren Werke Aktiengesellschaft | Verfahren zum Transfer von Daten in mehrere Steuergeräte |
| US20100115323A1 (en) * | 2007-04-11 | 2010-05-06 | Panasonic Corporation | Data store system, data restoration system, data store method, and data restoration method |
| US8156273B2 (en) * | 2007-05-10 | 2012-04-10 | Freescale Semiconductor, Inc. | Method and system for controlling transmission and execution of commands in an integrated circuit device |
| CN101453313B (zh) * | 2007-12-06 | 2013-03-20 | 鸿富锦精密工业(深圳)有限公司 | 主从设备通信电路 |
| EP2416253B1 (en) * | 2009-03-31 | 2014-07-23 | Fujitsu Limited | Data transmission circuit and data transmission method |
| US8984195B2 (en) * | 2011-12-02 | 2015-03-17 | Atmel Corporation | Microcontroller including alternative links between peripherals for resource sharing |
| KR102169340B1 (ko) * | 2012-10-19 | 2020-10-23 | 페어차일드 세미컨덕터 코포레이션 | 단일 전도체 인터페이스 작동 및 스위칭 장치 및 그 방법 |
| US20160062930A1 (en) * | 2013-03-25 | 2016-03-03 | Mitsubishi Electric Corporation | Bus master, bus system, and bus control method |
| GB2540610B (en) * | 2015-07-23 | 2017-12-06 | Advanced Risc Mach Ltd | Gathering monitoring data relating to the operation of a data processing system |
| GB2551806B (en) * | 2016-06-30 | 2020-06-03 | Advanced Risc Mach Ltd | Interface with buffered and direct pathways |
| CN111797051B (zh) * | 2020-06-04 | 2022-05-17 | 深圳云天励飞技术股份有限公司 | 片上系统、数据传送方法及广播模块 |
| DE102021106379A1 (de) | 2021-03-16 | 2022-09-22 | Infineon Technologies Ag | Master, Slave, Master-Slave-Kommunikations-System, On-Chip-Interconnect-System, Verfahren zum Betreiben eines Masters, Verfahren zum Betreiben eines Slaves, Verfahren zum Betreiben eines Master-Slave-Kommunikations-Systems und Verfahren zum Betreiben eines On-Chip-Interconnect-Systems |
| CN113765824A (zh) * | 2021-10-15 | 2021-12-07 | 合肥移瑞通信技术有限公司 | 基于mbim接口的响应消息发送方法、装置、mbb设备及介质 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5956524A (en) * | 1990-04-06 | 1999-09-21 | Micro Technology Inc. | System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources |
| DE69323861T2 (de) | 1993-01-25 | 1999-10-07 | Bull Hn Information Systems Italia S.P.A., Pregnana Milanese | Multiprozessorsystem mit gemeinsamem Speicher |
| US5581729A (en) * | 1995-03-31 | 1996-12-03 | Sun Microsystems, Inc. | Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system |
| US5907485A (en) | 1995-03-31 | 1999-05-25 | Sun Microsystems, Inc. | Method and apparatus for flow control in packet-switched computer system |
| US5761516A (en) * | 1996-05-03 | 1998-06-02 | Lsi Logic Corporation | Single chip multiprocessor architecture with internal task switching synchronization bus |
| US6065077A (en) * | 1997-12-07 | 2000-05-16 | Hotrail, Inc. | Apparatus and method for a cache coherent shared memory multiprocessing system |
| US6516442B1 (en) * | 1997-12-07 | 2003-02-04 | Conexant Systems, Inc. | Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system |
| US6347344B1 (en) * | 1998-10-14 | 2002-02-12 | Hitachi, Ltd. | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor |
| US6715023B1 (en) * | 1999-09-23 | 2004-03-30 | Altera Corporation | PCI bus switch architecture |
| US6441479B1 (en) * | 2000-03-02 | 2002-08-27 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
| KR100716950B1 (ko) * | 2000-08-11 | 2007-05-10 | 삼성전자주식회사 | 버스 시스템 |
| JP4024484B2 (ja) * | 2001-03-13 | 2007-12-19 | 株式会社リコー | バスアービタ |
| JP2003030134A (ja) * | 2001-07-12 | 2003-01-31 | Matsushita Electric Ind Co Ltd | バスアービタ及びバスアービトレーション方法 |
| IL144789A0 (en) | 2001-08-07 | 2002-06-30 | Broadlight Ltd | System architecture of a high bit rate switch module between functional units in a system on a chip |
| US6857035B1 (en) * | 2001-09-13 | 2005-02-15 | Altera Corporation | Methods and apparatus for bus mastering and arbitration |
| EP1376373B1 (en) * | 2002-06-20 | 2006-05-31 | Infineon Technologies AG | Arrangement having a first device and a second device connected via a cross bar switch |
| JP2004126646A (ja) * | 2002-09-30 | 2004-04-22 | Canon Inc | バス制御方法 |
| JP2005234932A (ja) * | 2004-02-20 | 2005-09-02 | Oki Electric Ind Co Ltd | マトリックス状バス接続システムとその低電力方法 |
-
2005
- 2005-02-10 US US11/055,922 patent/US7246188B2/en not_active Expired - Lifetime
-
2006
- 2006-02-09 ES ES06720664T patent/ES2355054T3/es active Active
- 2006-02-09 AT AT06720664T patent/ATE491993T1/de not_active IP Right Cessation
- 2006-02-09 WO PCT/US2006/004936 patent/WO2006086732A1/en not_active Ceased
- 2006-02-09 DE DE602006018862T patent/DE602006018862D1/de active Active
- 2006-02-09 MX MX2007009732A patent/MX2007009732A/es active IP Right Grant
- 2006-02-09 KR KR1020077020415A patent/KR100932408B1/ko not_active Expired - Fee Related
- 2006-02-09 PL PL06720664T patent/PL1846831T3/pl unknown
- 2006-02-09 JP JP2007555297A patent/JP4861339B2/ja active Active
- 2006-02-09 CN CN200680009670A patent/CN100595744C/zh not_active Expired - Fee Related
- 2006-02-09 EP EP06720664A patent/EP1846831B1/en not_active Not-in-force
-
2007
- 2007-08-06 IL IL185067A patent/IL185067A0/en unknown
-
2010
- 2010-09-24 JP JP2010214177A patent/JP5456632B2/ja not_active Expired - Fee Related
-
2011
- 2011-09-09 JP JP2011197213A patent/JP5456743B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2011048838A5 (enExample) | ||
| IL185067A0 (en) | Flow control method to improve data transfer via a switch matrix | |
| US10061729B2 (en) | Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller | |
| US7506089B2 (en) | Bus system and method thereof | |
| US8145815B2 (en) | Data processing system | |
| US9229896B2 (en) | Systems and methods for maintaining an order of read and write transactions in a computing system | |
| JP2010282405A5 (enExample) | ||
| CN112106032A (zh) | I/o主设备和cpu之间优化数据共享的有序写存储的高性能流 | |
| CN101132336A (zh) | 异构多核处理器高速异步互连通信网络 | |
| TW201418988A (zh) | 主機與外圍裝置之間的通訊設備、系統及其方法 | |
| TW201007463A (en) | Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock | |
| JP3562583B2 (ja) | プロセッサ・ローカル・バスを管理する装置、方法およびコンピュータ・プログラム・プロダクト | |
| CN101930422A (zh) | 一种基于多层ahb总线的多核cpu互连结构 | |
| TWI540438B (zh) | 記憶體控制元件 | |
| US9588734B2 (en) | Translation layer for controlling bus access | |
| EP1434137A1 (en) | Bus architecture with primary bus and secondary bus for microprocessor systems | |
| EP3191971A1 (en) | Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media | |
| CN1326058C (zh) | 数据传输控制装置 | |
| TW201916644A (zh) | 匯流排系統 | |
| TW200428279A (en) | An apparatus and method for address bus power control | |
| US20130185468A1 (en) | Semiconductor device | |
| JP2007122410A (ja) | バス調停回路及びバス調停方法 | |
| JP2008158585A5 (enExample) | ||
| JP5648472B2 (ja) | 半導体装置及び制御方法 | |
| JP2012173847A (ja) | バス調停装置およびバス調停方法 |