CN100595744C - 芯片上系统集成电路、电子系统及在其内传送数据的方法 - Google Patents

芯片上系统集成电路、电子系统及在其内传送数据的方法 Download PDF

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Publication number
CN100595744C
CN100595744C CN200680009670A CN200680009670A CN100595744C CN 100595744 C CN100595744 C CN 100595744C CN 200680009670 A CN200680009670 A CN 200680009670A CN 200680009670 A CN200680009670 A CN 200680009670A CN 100595744 C CN100595744 C CN 100595744C
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data
slave
devices
master
ready
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Chinese (zh)
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CN101203839A (zh
Inventor
J·普拉喀什·苏布拉马尼亚姆·贾纳桑
佩里·威尔曼·小雷马克吕斯
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Qualcomm Inc
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Qualcomm Inc
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038System on Chip
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Credit Cards Or The Like (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Optical Communication System (AREA)
  • Small-Scale Networks (AREA)
CN200680009670A 2005-02-10 2006-02-09 芯片上系统集成电路、电子系统及在其内传送数据的方法 Expired - Fee Related CN100595744C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/055,922 US7246188B2 (en) 2005-02-10 2005-02-10 Flow control method to improve bus utilization in a system-on-a-chip integrated circuit
US11/055,922 2005-02-10
PCT/US2006/004936 WO2006086732A1 (en) 2005-02-10 2006-02-09 Flow control method to improve data transfer via a switch matrix

Publications (2)

Publication Number Publication Date
CN101203839A CN101203839A (zh) 2008-06-18
CN100595744C true CN100595744C (zh) 2010-03-24

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CN200680009670A Expired - Fee Related CN100595744C (zh) 2005-02-10 2006-02-09 芯片上系统集成电路、电子系统及在其内传送数据的方法

Country Status (12)

Country Link
US (1) US7246188B2 (enExample)
EP (1) EP1846831B1 (enExample)
JP (3) JP4861339B2 (enExample)
KR (1) KR100932408B1 (enExample)
CN (1) CN100595744C (enExample)
AT (1) ATE491993T1 (enExample)
DE (1) DE602006018862D1 (enExample)
ES (1) ES2355054T3 (enExample)
IL (1) IL185067A0 (enExample)
MX (1) MX2007009732A (enExample)
PL (1) PL1846831T3 (enExample)
WO (1) WO2006086732A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2407662B (en) * 2003-11-03 2006-02-22 Compxs Uk Ltd Two way serial communication
US7788625B1 (en) * 2005-04-14 2010-08-31 Xilinx, Inc. Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
DE102005026436B4 (de) * 2005-06-08 2022-08-18 Austriamicrosystems Ag Schnittstellenanordnung, insbesondere für ein System-on-Chip, und deren Verwendung
US20070255874A1 (en) * 2006-04-28 2007-11-01 Jennings Kevin F System and method for target device access arbitration using queuing devices
US7908412B2 (en) * 2006-05-10 2011-03-15 Microsoft Corporation Buffer passing mechanisms
KR100854973B1 (ko) * 2007-02-13 2008-08-28 삼성전자주식회사 버스 매트릭스를 포함하는 시스템
DE102007015122A1 (de) * 2007-03-29 2008-10-02 Bayerische Motoren Werke Aktiengesellschaft Verfahren zum Transfer von Daten in mehrere Steuergeräte
US20100115323A1 (en) * 2007-04-11 2010-05-06 Panasonic Corporation Data store system, data restoration system, data store method, and data restoration method
US8156273B2 (en) * 2007-05-10 2012-04-10 Freescale Semiconductor, Inc. Method and system for controlling transmission and execution of commands in an integrated circuit device
CN101453313B (zh) * 2007-12-06 2013-03-20 鸿富锦精密工业(深圳)有限公司 主从设备通信电路
WO2010113291A1 (ja) * 2009-03-31 2010-10-07 富士通株式会社 データ転送回路及びデータ転送方法
US8984195B2 (en) * 2011-12-02 2015-03-17 Atmel Corporation Microcontroller including alternative links between peripherals for resource sharing
TWI617164B (zh) * 2012-10-19 2018-03-01 菲爾卻德半導體公司 用於操作與切換一單一導體介面之裝置及方法
WO2014156282A1 (ja) * 2013-03-25 2014-10-02 三菱電機株式会社 バスマスタ、バスシステム及びバス制御方法
GB2540610B (en) * 2015-07-23 2017-12-06 Advanced Risc Mach Ltd Gathering monitoring data relating to the operation of a data processing system
GB2551806B (en) * 2016-06-30 2020-06-03 Advanced Risc Mach Ltd Interface with buffered and direct pathways
CN111797051B (zh) * 2020-06-04 2022-05-17 深圳云天励飞技术股份有限公司 片上系统、数据传送方法及广播模块
DE102021106379A1 (de) * 2021-03-16 2022-09-22 Infineon Technologies Ag Master, Slave, Master-Slave-Kommunikations-System, On-Chip-Interconnect-System, Verfahren zum Betreiben eines Masters, Verfahren zum Betreiben eines Slaves, Verfahren zum Betreiben eines Master-Slave-Kommunikations-Systems und Verfahren zum Betreiben eines On-Chip-Interconnect-Systems
CN113765824A (zh) * 2021-10-15 2021-12-07 合肥移瑞通信技术有限公司 基于mbim接口的响应消息发送方法、装置、mbb设备及介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735476A1 (en) * 1995-03-31 1996-10-02 Sun Microsystems, Inc. Method and apparatus for flow control in a packet-switched computer system
CN1337628A (zh) * 2000-08-11 2002-02-27 三星电子株式会社 总线系统
WO2003014948A1 (en) * 2001-08-07 2003-02-20 Broadlight Ltd. System architecture of a high bit rate switch module between functional units in a system on a chip
EP1376373A1 (en) * 2002-06-20 2004-01-02 Infineon Technologies AG Arrangement having a first device and a second device connected via a cross bar switch

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
DE69323861T2 (de) 1993-01-25 1999-10-07 Bull Hn Information Systems Italia S.P.A., Pregnana Milanese Multiprozessorsystem mit gemeinsamem Speicher
US5581729A (en) * 1995-03-31 1996-12-03 Sun Microsystems, Inc. Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
US5761516A (en) * 1996-05-03 1998-06-02 Lsi Logic Corporation Single chip multiprocessor architecture with internal task switching synchronization bus
US6516442B1 (en) * 1997-12-07 2003-02-04 Conexant Systems, Inc. Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
US6065077A (en) * 1997-12-07 2000-05-16 Hotrail, Inc. Apparatus and method for a cache coherent shared memory multiprocessing system
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
US6715023B1 (en) * 1999-09-23 2004-03-30 Altera Corporation PCI bus switch architecture
US6441479B1 (en) * 2000-03-02 2002-08-27 Micron Technology, Inc. System-on-a-chip with multi-layered metallized through-hole interconnection
JP4024484B2 (ja) * 2001-03-13 2007-12-19 株式会社リコー バスアービタ
JP2003030134A (ja) * 2001-07-12 2003-01-31 Matsushita Electric Ind Co Ltd バスアービタ及びバスアービトレーション方法
US6857035B1 (en) * 2001-09-13 2005-02-15 Altera Corporation Methods and apparatus for bus mastering and arbitration
JP2004126646A (ja) * 2002-09-30 2004-04-22 Canon Inc バス制御方法
JP2005234932A (ja) * 2004-02-20 2005-09-02 Oki Electric Ind Co Ltd マトリックス状バス接続システムとその低電力方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735476A1 (en) * 1995-03-31 1996-10-02 Sun Microsystems, Inc. Method and apparatus for flow control in a packet-switched computer system
CN1337628A (zh) * 2000-08-11 2002-02-27 三星电子株式会社 总线系统
WO2003014948A1 (en) * 2001-08-07 2003-02-20 Broadlight Ltd. System architecture of a high bit rate switch module between functional units in a system on a chip
EP1376373A1 (en) * 2002-06-20 2004-01-02 Infineon Technologies AG Arrangement having a first device and a second device connected via a cross bar switch

Also Published As

Publication number Publication date
JP5456632B2 (ja) 2014-04-02
WO2006086732A1 (en) 2006-08-17
JP2012038325A (ja) 2012-02-23
MX2007009732A (es) 2007-09-26
EP1846831B1 (en) 2010-12-15
PL1846831T3 (pl) 2011-04-29
JP2008530694A (ja) 2008-08-07
ES2355054T3 (es) 2011-03-22
JP2011048838A (ja) 2011-03-10
WO2006086732A9 (en) 2006-10-19
CN101203839A (zh) 2008-06-18
HK1114213A1 (zh) 2008-10-24
EP1846831A1 (en) 2007-10-24
ATE491993T1 (de) 2011-01-15
US7246188B2 (en) 2007-07-17
KR20070104929A (ko) 2007-10-29
DE602006018862D1 (de) 2011-01-27
JP4861339B2 (ja) 2012-01-25
KR100932408B1 (ko) 2009-12-17
IL185067A0 (en) 2007-12-03
US20060179192A1 (en) 2006-08-10
JP5456743B2 (ja) 2014-04-02

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