JP2011018893A - Insulation material, electronic element incorporation type printed board, and method of manufacturing the same - Google Patents

Insulation material, electronic element incorporation type printed board, and method of manufacturing the same Download PDF

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JP2011018893A
JP2011018893A JP2010128810A JP2010128810A JP2011018893A JP 2011018893 A JP2011018893 A JP 2011018893A JP 2010128810 A JP2010128810 A JP 2010128810A JP 2010128810 A JP2010128810 A JP 2010128810A JP 2011018893 A JP2011018893 A JP 2011018893A
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insulator
cavity
core substrate
electronic element
resin layer
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JP5202579B2 (en
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Sang-Chul Lee
相 ▲徹▼ 李
栗 ▲教▼ ▲鄭▼
Yul-Kyo Chung
Doo Hwan Lee
斗 煥 李
Sangjin Baek
▲尚▼ 津 白
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Priority claimed from KR1020090114119A external-priority patent/KR101056156B1/en
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Abstract

PROBLEM TO BE SOLVED: To provide an insulation material, an electronic element incorporation type printed board, and a method of manufacturing the same.SOLUTION: The method of manufacturing an electronic element incorporation type printed board includes steps of: providing a core board penetrated by a cavity and having a circuit pattern formed on a surface thereof; sticking an adhesive layer on the undersurface of the core board to cover the cavity; arranging an electronic element on an upper surface of the adhesive layer corresponding to the cavity; covering the circuit pattern by laminating a first insulation material without being impregnated with a reinforcing material on the upper surface of the core board to fill the cavity; and laminating a second insulation material impregnated with the reinforcing material on the upper and lower sides of the core board.

Description

本発明は、絶縁体、電子素子内蔵型印刷回路基板、及び電子素子内蔵型印刷回路基板の製造方法に関する。   The present invention relates to an insulator, an electronic element-embedded printed circuit board, and a method for manufacturing an electronic element-embedded printed circuit board.

電子産業の発達に伴って電子部品の高機能化、小型化がますます求められる傾向にあり、特に個人携帯端末機の軽薄短小化への市場の動きが印刷回路基板の薄型化につながっている。ここで、従来の素子実装方式とは異なる方式の素子実装方式が注目を浴びており、ICのような能動部品(Active devices)またはMLCC形態のキャパシタなどの受動部品(Passive devices)を印刷回路基板の内部に実装することにより、部品の高密度化及び信頼性の向上、またはこれらの有機的な結合によるパッケージ自体の性能向上などを求めるエンベデッド印刷回路基板がそれである。   With the development of the electronic industry, there is a tendency for electronic components to become highly functional and miniaturized. Especially, the movement of the market to make personal portable terminals lighter and thinner has led to thinner printed circuit boards. . Here, an element mounting method different from the conventional element mounting method has attracted attention, and an active component such as an IC or a passive component such as an MLCC type capacitor is used as a printed circuit board. This is an embedded printed circuit board that requires a higher density of components and an improvement in reliability by being mounted inside the package, or an improvement in the performance of the package itself by organic coupling of these components.

本発明は、部品内蔵基板の作製時、高さの高い電子素子を内蔵することから発生する問題点を解決するためのものであって、その問題点は次の通りである。   The present invention is intended to solve the problems that arise from the incorporation of a high electronic component when a component-embedded substrate is manufactured. The problems are as follows.

従来技術によれば、200μm〜1000μm未満の高さを有する電子素子(例えば、MLCC:積層セラミックコンデンサ)をコア基板に内蔵する場合、図1に示すように、接着層20を用いて、キャビティ14と回路12が形成されたコア基板10内に電子素子30を内蔵した後、基板の反りなどを低減する目的で樹脂42にガラス繊維44(Glass fabric)を含浸させた絶縁体40を積層するが、この場合、電子素子30の高さが高いことから、図2に示すように、電子素子の周辺及びビアホールが絶縁体の樹脂42で完全に充填されないことがある。すなわち、内部にボイド50が発生してしまう。これは信頼性不良に至ることになり、これに対する改善が望まれている。   According to the prior art, when an electronic device (for example, MLCC: multilayer ceramic capacitor) having a height of 200 μm to less than 1000 μm is built in the core substrate, the adhesive layer 20 is used to form the cavity 14 as shown in FIG. After the electronic element 30 is built in the core substrate 10 on which the circuit 12 is formed, an insulator 40 in which a glass fiber 44 (Glass fabric) is impregnated with a resin 42 is laminated for the purpose of reducing warpage of the substrate. In this case, since the height of the electronic element 30 is high, the periphery of the electronic element and the via hole may not be completely filled with the insulating resin 42 as shown in FIG. That is, the void 50 is generated inside. This leads to poor reliability, and improvements to this are desired.

これらの問題を解決するために、図3に示すように、厚い樹脂42’を含む絶縁体40’を用いる方法が提示されているが、これは、図4に示すように印刷回路基板が全体的に過度に厚くなるという問題点を引き起こす。   In order to solve these problems, as shown in FIG. 3, a method using an insulator 40 ′ including a thick resin 42 ′ is proposed. This is because the printed circuit board is entirely formed as shown in FIG. Cause the problem of excessively thickening.

こうした従来技術の問題点に鑑み、本発明は、薄型の絶縁体を用いてレイアップ工程を行う場合であっても、樹脂含量の低下から電子素子の周辺及び回路パターン間に発生するボイドを防止することができ、レイアップ工程時に絶縁体に含浸された補強材のために電子素子が損傷する問題点を解決することができる、絶縁体、電子素子内蔵型印刷回路基板、及びその製造方法を提供することを目的とする。   In view of such problems of the prior art, the present invention prevents voids generated around the electronic element and between circuit patterns from the decrease in the resin content even when the lay-up process is performed using a thin insulator. An insulator, a printed circuit board with a built-in electronic element, and a method for manufacturing the same, which can solve the problem that the electronic element is damaged due to the reinforcing material impregnated in the insulator during the layup process The purpose is to provide.

本発明の一実施形態によれば、キャビティにより貫通され、表面に回路パターンが設けられたコア基板を提供する工程と、上記コア基板の下面に上記キャビティをカバーするように接着層を付着する工程と、上記キャビティに対応する上記接着層の上面に電子素子を配置する工程と、上記キャビティが充填されるように、上記コア基板の上面に補強材が含浸されていない第1絶縁体を積層して上記回路パターンをカバーする工程と、上記コア基板の上下側に、補強材が含浸された第2絶縁体を積層する工程と、を含む電子素子内蔵型印刷回路基板の製造方法が提供される。   According to an embodiment of the present invention, a step of providing a core substrate that is penetrated by a cavity and provided with a circuit pattern on a surface thereof, and a step of attaching an adhesive layer to the lower surface of the core substrate so as to cover the cavity And a step of disposing an electronic element on the upper surface of the adhesive layer corresponding to the cavity, and laminating a first insulator not impregnated with a reinforcing material on the upper surface of the core substrate so as to fill the cavity. There is provided a method for manufacturing a printed circuit board with a built-in electronic element, comprising: a step of covering the circuit pattern; and a step of laminating a second insulator impregnated with a reinforcing material on the upper and lower sides of the core substrate. .

また、本発明の他の実施形態によれば、キャビティにより貫通され、表面に内層回路が設けられたコア基板と、上記キャビティに内蔵される電子素子と、上記キャビティを充填しかつ上記内層回路をカバーするように、上記コア基板の上面に積層された、補強材が含浸されていない第1絶縁体と、上記コア基板の上下側にそれぞれ積層された、補強材が含浸された第2絶縁体と、上記第2絶縁体に形成された回路パターンと、を含む電子素子内蔵型印刷回路基板が提供される。   According to another embodiment of the present invention, a core substrate that is penetrated by a cavity and provided with an inner layer circuit on a surface thereof, an electronic element that is built in the cavity, and that fills the cavity and includes the inner layer circuit. A first insulator that is laminated on the upper surface of the core substrate so as to cover and is not impregnated with a reinforcing material, and a second insulator that is laminated on the upper and lower sides of the core substrate and impregnated with a reinforcing material. And a printed circuit board with a built-in electronic element including the circuit pattern formed on the second insulator.

このとき、上記第1絶縁体と上記第2絶縁体の樹脂は同じ材質であってもよい。   At this time, the resin of the first insulator and the second insulator may be the same material.

本発明のまた他の実施形態によれば、キャビティにより貫通され、表面に回路パターンが設けられたコア基板を提供する工程と、上記コア基板の下面に上記キャビティをカバーする接着層を付着する工程と、上記キャビティに対応する上記接着層の上面に電子素子を配置する工程と、上記キャビティが充填されるように、補強材を中心として上下にそれぞれ上部樹脂層と下部樹脂層とが形成された絶縁体を上記コア基板の上面に積層する工程と、を含み、上記絶縁体は、上記下部樹脂層が上記上部樹脂層よりも厚い非対称形状であることを特徴とする電子素子内蔵型印刷回路基板の製造方法が提供される。   According to still another embodiment of the present invention, a step of providing a core substrate that is penetrated by a cavity and provided with a circuit pattern on a surface thereof, and a step of attaching an adhesive layer that covers the cavity to the lower surface of the core substrate. And a step of disposing an electronic device on the upper surface of the adhesive layer corresponding to the cavity, and an upper resin layer and a lower resin layer are formed vertically around the reinforcing material so as to fill the cavity. A step of laminating an insulator on the upper surface of the core substrate, wherein the insulator has an asymmetric shape in which the lower resin layer is thicker than the upper resin layer. A manufacturing method is provided.

また、本発明のまた他の実施形態によれば、印刷回路基板の製造に用いられる絶縁体であって、補強材の上下にそれぞれ積層された上部樹脂層と下部樹脂層を含み、上記下部樹脂層が上記上部樹脂層よりも厚いことを特徴とする絶縁体が提供される。   According to another embodiment of the present invention, the insulator is used for manufacturing a printed circuit board, and includes an upper resin layer and a lower resin layer respectively laminated on the upper and lower sides of the reinforcing material, and the lower resin An insulator is provided wherein the layer is thicker than the upper resin layer.

ここで、上記下部樹脂層の厚さは上記上部樹脂層の厚さの2〜5倍であってもよい。   Here, the thickness of the lower resin layer may be 2 to 5 times the thickness of the upper resin layer.

本発明の好ましい実施例によれば、薄型の絶縁体を用いてレイアップ工程を行う場合であっても、樹脂含量の低下から電子素子の周辺及び回路パターン間に発生するボイドを防止することができる。また、レイアップ工程時、絶縁体に含浸させた補強材のために電子素子が損傷する問題点を解決することができる。
なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。
According to a preferred embodiment of the present invention, even when a lay-up process is performed using a thin insulator, it is possible to prevent voids generated around the electronic device and between circuit patterns due to a decrease in the resin content. it can. In addition, it is possible to solve the problem that the electronic element is damaged due to the reinforcing material impregnated in the insulator during the layup process.
It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

従来技術に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a diagram illustrating a method for manufacturing a printed circuit board with a built-in electronic device according to the related art. 従来技術に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a diagram illustrating a method for manufacturing a printed circuit board with a built-in electronic device according to the related art. 従来技術に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a diagram illustrating a method for manufacturing a printed circuit board with a built-in electronic device according to the related art. 従来技術に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a diagram illustrating a method for manufacturing a printed circuit board with a built-in electronic device according to the related art. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す順序図である。FIG. 3 is a flowchart illustrating a method for manufacturing a printed circuit board with a built-in electronic element according to an embodiment of the present invention. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。1 is a view illustrating a method of manufacturing an electronic device built-in type printed circuit board according to an embodiment of the present invention. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。1 is a view illustrating a method of manufacturing an electronic device built-in type printed circuit board according to an embodiment of the present invention. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。1 is a view illustrating a method of manufacturing an electronic device built-in type printed circuit board according to an embodiment of the present invention. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。1 is a view illustrating a method of manufacturing an electronic device built-in type printed circuit board according to an embodiment of the present invention. 本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。1 is a view illustrating a method of manufacturing an electronic device built-in type printed circuit board according to an embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す順序図である。FIG. 6 is a flow chart illustrating a method for manufacturing an electronic element built-in type printed circuit board according to another embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a view illustrating a method of manufacturing a printed circuit board with built-in electronic elements according to another embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a view illustrating a method of manufacturing a printed circuit board with built-in electronic elements according to another embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a view illustrating a method of manufacturing a printed circuit board with built-in electronic elements according to another embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a view illustrating a method of manufacturing a printed circuit board with built-in electronic elements according to another embodiment of the present invention. 本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。6 is a view illustrating a method of manufacturing a printed circuit board with built-in electronic elements according to another embodiment of the present invention.

本発明は多様な変換を加えることができ、様々な実施例を有することができるため、本願では特定実施例を図面に例示し、詳細に説明する。しかし、これは本発明を特定の実施形態に限定するものではなく、本発明の思想及び技術範囲に含まれるあらゆる変換、均等物及び代替物を含むものとして理解されるべきである。   Since the present invention can be modified in various ways and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail herein. However, this is not to be construed as limiting the invention to the specific embodiments, but is to be understood as including all transformations, equivalents, and alternatives falling within the spirit and scope of the invention.

以下、本発明に係る電子素子内蔵型印刷回路基板の製造方法の実施例を添付図面を参照して詳細に説明するが、添付図面を参照して説明することにおいて、同一かつ対応する構成要素は同一の図面番号を付し、これに対する重複説明は省略する。   Hereinafter, an embodiment of a method of manufacturing an electronic element built-in type printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same and corresponding components are as follows. The same drawing number is attached and the duplicate description for this is omitted.

図5は、本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す順序図であり、図6から図10は、本発明の一実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。   FIG. 5 is a flowchart illustrating a method of manufacturing a printed circuit board with a built-in electronic device according to an embodiment of the present invention. FIGS. 6 to 10 illustrate a printed circuit with a built-in electronic device according to an embodiment of the present invention. It is drawing which shows the manufacturing method of a board | substrate.

まず、図6に示すように、ステップS110で、キャビティ114により貫通され、表面に内層回路112が設けられたコア基板110を用意した後、ステップS120で、コア基板110の下面にキャビティ114をカバーするように接着層120を付着する。コア基板110としては銅張積層板(CCL)を用いることができ、その他にも剛性を補強するためにガラス繊維が含浸されたエポキシ樹脂を用いることもできる。このようなコア基板110の表面には内層回路112が設けられる。   First, as shown in FIG. 6, after preparing the core substrate 110 penetrating by the cavity 114 and having the inner layer circuit 112 provided on the surface in step S110, the cavity 114 is covered on the lower surface of the core substrate 110 in step S120. Then, the adhesive layer 120 is attached. As the core substrate 110, a copper clad laminate (CCL) can be used, and in addition, an epoxy resin impregnated with glass fibers can be used to reinforce the rigidity. An inner layer circuit 112 is provided on the surface of the core substrate 110.

コア基板110として銅張積層板を用いる場合、その表面に内層回路112を形成するためには、銅張積層板の両面に無電解メッキによるシード層を形成した後に選択的な電解メッキで回路パターンを形成する方法を用いることができる。その他にも銅張積層板の両面に形成された銅箔の一部をエッチングして内層回路112を形成する方法を用いることもできる。   When a copper clad laminate is used as the core substrate 110, in order to form the inner layer circuit 112 on the surface, a circuit pattern is formed by selective electroplating after forming a seed layer by electroless plating on both sides of the copper clad laminate. The method of forming can be used. In addition, a method of forming the inner layer circuit 112 by etching a part of the copper foil formed on both surfaces of the copper clad laminate can be used.

コア基板110の所定の位置(例えば、中央部分)にはキャビティ114が加工される。キャビティ114は電子素子140が内蔵される空間であって、機械的なドリルまたはレーザードリルなどを用いた加工方法で形成可能である。このように加工されたキャビティ114の下側は接着層120により遮蔽される。   A cavity 114 is processed at a predetermined position (for example, a central portion) of the core substrate 110. The cavity 114 is a space in which the electronic element 140 is built, and can be formed by a processing method using a mechanical drill or a laser drill. The lower side of the cavity 114 thus processed is shielded by the adhesive layer 120.

次に、ステップS130で、図6に示すように、キャビティ114に対応する接着層120の上面に電子素子140を配置する。このように電子素子140を配置すると、電子素子140がキャビティ114に露出している接着層120の上面に付着され固定される。   Next, in step S130, the electronic element 140 is disposed on the upper surface of the adhesive layer 120 corresponding to the cavity 114, as shown in FIG. When the electronic element 140 is arranged in this way, the electronic element 140 is attached and fixed to the upper surface of the adhesive layer 120 exposed to the cavity 114.

その後 、ステップS140で、図6及び図7に示すように、キャビティ114が充填されるように、コア基板110の上面に補強材が含浸されていない第1絶縁体130を積層して内層回路112をカバーする。   Thereafter, in step S140, as shown in FIGS. 6 and 7, the inner layer circuit 112 is formed by laminating the first insulator 130 that is not impregnated with the reinforcing material on the upper surface of the core substrate 110 so that the cavity 114 is filled. Cover.

このように表面に内層回路112が形成されたコア基板110の上面に補強材が含浸されていない第1絶縁体130(例えば、プライマーレジンなど)を積層して上部に平坦面を形成すると、第1絶縁体130でキャビティ114の残存空間が充填されることになり、電子素子140を固定できるだけでなく、ビアホールの内部も第1絶縁体130で充填されることになる。   When the first insulator 130 (for example, a primer resin) that is not impregnated with the reinforcing material is laminated on the upper surface of the core substrate 110 having the inner layer circuit 112 formed on the surface in this manner, a flat surface is formed on the upper portion. The remaining space of the cavity 114 is filled with the 1 insulator 130, and not only the electronic element 140 can be fixed, but also the inside of the via hole is filled with the first insulator 130.

また、コア基板110の上面に形成された内層回路112は第1絶縁体130でカバーされる。さらに、電子素子140の電極(図示せず)が全て上向きに配置された場合、すなわち、電子素子140がフェースアップ(face−up)方式で内蔵された場合は電子素子140の電極(図示せず)も樹脂でカバーされる。   Further, the inner layer circuit 112 formed on the upper surface of the core substrate 110 is covered with a first insulator 130. Further, when all the electrodes (not shown) of the electronic element 140 are arranged upward, that is, when the electronic element 140 is built in a face-up manner, the electrodes (not shown) of the electronic element 140 are arranged. ) Is also covered with resin.

このように、剛性を確保するための補強材が含浸された第2絶縁体150(図9参照)を用いるレイアップの工程の前に、補強材が含浸されていない別の第1絶縁体130をコア基板110に積層することにより、キャビティ114の残存空間、ビアホール内部の空間、回路パターン112間の空間、回路パターン112と電子素子140の電極との間の空間を全て満たすことができ、後に樹脂含量の低い薄型の第2絶縁体150を積層する場合にも、キャビティ114、ビアホール内部、回路パターン112間の空間、回路パターン112と電子素子140の電極(図示せず)との間の空間にボイドが発生することを防止することができる。   Thus, before the lay-up process using the second insulator 150 (see FIG. 9) impregnated with the reinforcing material for ensuring rigidity, another first insulator 130 not impregnated with the reinforcing material is used. Is stacked on the core substrate 110, so that the remaining space of the cavity 114, the space inside the via hole, the space between the circuit patterns 112, and the space between the circuit pattern 112 and the electrodes of the electronic element 140 can be filled. Even when the thin second insulator 150 having a low resin content is stacked, the space between the cavity 114, the via hole, the circuit pattern 112, and the circuit pattern 112 and the electrode (not shown) of the electronic element 140 is also used. It is possible to prevent the generation of voids.

その後、ステップS150で、図8に示すように、接着層120を除去し、ステップS160で、図9に示すように、コア基板110の上下側に補強材154が含浸された第2絶縁体150を積層する。このとき、第2絶縁体150の樹脂152としては、上述した第1絶縁体130と同じ材質からなるものを用いることができる。すなわち、キャビティ114及びビアホールの充填に用いられた第1絶縁体130と同じ材質を含む第2絶縁体150を用いればよい。このように同じ材質を含む絶縁体を用いることにより、第1絶縁体130と第2絶縁体150との界面にて熱膨張係数の差による反り(warpage)の発生可能性を低減することができ、これらの間の強固な接着力を確保することもできる。その結果、層間デラミネーションの問題を解消することができる。   Thereafter, in step S150, the adhesive layer 120 is removed as shown in FIG. 8, and in step S160, the second insulator 150 in which the reinforcing material 154 is impregnated on the upper and lower sides of the core substrate 110 as shown in FIG. Are laminated. At this time, the resin 152 of the second insulator 150 may be made of the same material as that of the first insulator 130 described above. That is, the second insulator 150 including the same material as the first insulator 130 used for filling the cavity 114 and the via hole may be used. By using an insulator including the same material as described above, it is possible to reduce the possibility of warpage due to a difference in thermal expansion coefficient at the interface between the first insulator 130 and the second insulator 150. Further, it is possible to secure a strong adhesive force between them. As a result, the problem of interlayer delamination can be solved.

また、第1絶縁体130でキャビティ114の内部、ビアホールの内部、回路パターン112間の空隙などが全て満たされるため、ボイドが発生することなく、樹脂152の含量の低い薄型の第2絶縁体150を使用できるようになり、印刷回路基板をより薄く実現することができる。さらに、既に形成された第1絶縁体130が、第2絶縁体150内に含浸された補強材154と電子素子140の電極及び/または回路パターン112との間で緩衝機能を発揮するため、含浸された補強材154が電子素子140の電極(図示せず)及び/または回路パターン112と接触して電子素子140及び/または回路パターン112が損傷することを解消することができる。   In addition, since the first insulator 130 fills all of the inside of the cavity 114, the inside of the via hole, the gap between the circuit patterns 112, etc., the thin second insulator 150 having a low resin 152 content without generating voids. The printed circuit board can be made thinner. Furthermore, since the first insulator 130 that has already been formed exhibits a buffering function between the reinforcing material 154 impregnated in the second insulator 150 and the electrode and / or circuit pattern 112 of the electronic element 140, the impregnation is performed. It is possible to eliminate the damage of the electronic element 140 and / or the circuit pattern 112 due to the reinforcing member 154 in contact with the electrode (not shown) and / or the circuit pattern 112 of the electronic element 140.

次に、図10に示すように、第2絶縁体150の上面に他の回路パターン162を形成する。第2絶縁体150の上面に形成された回路パターン162は、図10に示すようにソルダーレジスト160により保護されることができる。より高い層数の印刷回路基板を製造しようとする場合は、ソルダーレジスト160を形成せずにレイアップ工程をさらに行えばよいことは、言うまでもない。   Next, as shown in FIG. 10, another circuit pattern 162 is formed on the upper surface of the second insulator 150. The circuit pattern 162 formed on the upper surface of the second insulator 150 can be protected by a solder resist 160 as shown in FIG. Needless to say, when a printed circuit board having a higher number of layers is to be manufactured, the lay-up process may be further performed without forming the solder resist 160.

図11は、本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す順序図であり、図12から図16は本発明の他の実施例に係る電子素子内蔵型印刷回路基板の製造方法を示す図面である。   FIG. 11 is a flowchart illustrating a method of manufacturing a printed circuit board with a built-in electronic device according to another embodiment of the present invention. FIGS. 12 to 16 illustrate a printed circuit with a built-in electronic device according to another embodiment of the present invention. It is drawing which shows the manufacturing method of a circuit board.

まず、ステップS210で、図12に示すように、キャビティ114により貫通され、表面に内層回路112が設けられたコア基板110を用意し、ステップS220で、コア基板110の下面にキャビティ114をカバーするように接着層120を付着する。コア基板110としては銅張積層板(CCL)を用いることができ、その他にも剛性を補強するためにガラス繊維が含浸されたエポキシ樹脂を用いることができる。このようなコア基板110の表面には内層回路112が設けられる。   First, in step S210, as shown in FIG. 12, the core substrate 110 penetrating through the cavity 114 and having the inner layer circuit 112 provided on the surface is prepared. In step S220, the cavity 114 is covered on the lower surface of the core substrate 110. The adhesive layer 120 is attached as described above. As the core substrate 110, a copper clad laminate (CCL) can be used, and in addition, an epoxy resin impregnated with glass fibers can be used to reinforce the rigidity. An inner layer circuit 112 is provided on the surface of the core substrate 110.

コア基板110として銅張積層板を用いる場合、その表面に内層回路112を形成するために銅張積層板の両面に無電解メッキによるシード層を形成した後に選択的な電解メッキで回路パターンを形成する方法を用いることができる。その他にも銅張積層板の両面に形成された銅箔の一部をエッチングして内層回路112を形成する方法を用いることもできる。   When a copper clad laminate is used as the core substrate 110, a circuit pattern is formed by selective electroplating after forming a seed layer by electroless plating on both sides of the copper clad laminate to form an inner layer circuit 112 on the surface of the core substrate 110. Can be used. In addition, a method of forming the inner layer circuit 112 by etching a part of the copper foil formed on both surfaces of the copper clad laminate can be used.

コア基板110の所定の位置(例えば中央部分)にはキャビティ114が加工される。キャビティ114は電子素子140が内蔵される空間であって、機械的なドリルまたはレーザードリルなどを用いた加工方法で形成可能である。このように加工されたキャビティ114の下側は接着層120により遮蔽される。   A cavity 114 is processed at a predetermined position (for example, the central portion) of the core substrate 110. The cavity 114 is a space in which the electronic element 140 is built, and can be formed by a processing method using a mechanical drill or a laser drill. The lower side of the cavity 114 thus processed is shielded by the adhesive layer 120.

その後、ステップS230で、図12に示すように、キャビティ114に対応する接着層120の上面に電子素子140を配置する。このように電子素子140を配置すると、電子素子140がキャビティ114に露出している接着層120の上面に付着され固定される。   Thereafter, in step S230, the electronic element 140 is disposed on the upper surface of the adhesive layer 120 corresponding to the cavity 114, as shown in FIG. When the electronic element 140 is arranged in this way, the electronic element 140 is attached and fixed to the upper surface of the adhesive layer 120 exposed to the cavity 114.

その後、ステップS240で、図13及び図14に示すように、キャビティが充填されるように、補強材232を中心として上下にそれぞれ上部樹脂層236と下部樹脂層234が形成された第1絶縁体230をコア基板110の上面に積層する。このとき、コア基板110の上面に積層される第1絶縁体230は、下部樹脂層234が上部樹脂層236よりも厚い非対称形状を有する。   Thereafter, in step S240, as shown in FIG. 13 and FIG. 14, the first insulator in which the upper resin layer 236 and the lower resin layer 234 are formed in the vertical direction around the reinforcing material 232 so as to fill the cavity. 230 is stacked on the upper surface of the core substrate 110. At this time, the first insulator 230 stacked on the upper surface of the core substrate 110 has an asymmetric shape in which the lower resin layer 234 is thicker than the upper resin layer 236.

このように表面に内層回路112が形成されたコア基板110の上面に、下部樹脂層234が上部樹脂層236よりも厚い構造を有する第1絶縁体230を積層すると、相対的に厚い下部樹脂層234でキャビティ114の残存空間が充填されることになり、電子素子140を固定できるだけでなく、ビアホールの内部も下部樹脂層234で充填されることになる。また、コア基板110の上面に形成された内層回路112が下部樹脂層234でカバーされる。   When the first insulator 230 having a structure in which the lower resin layer 234 is thicker than the upper resin layer 236 is laminated on the upper surface of the core substrate 110 having the inner layer circuit 112 formed on the surface in this manner, a relatively thick lower resin layer is formed. In 234, the remaining space of the cavity 114 is filled, and not only the electronic element 140 can be fixed, but also the inside of the via hole is filled with the lower resin layer 234. Further, the inner layer circuit 112 formed on the upper surface of the core substrate 110 is covered with the lower resin layer 234.

さらに、電子素子140の電極(図示せず)が全て上向きに配置された場合、すなわち、電子素子140がフェースアップ方式で内蔵された場合は電子素子140の電極(図示せず)も下部樹脂層234でカバーされる。   Further, when all the electrodes (not shown) of the electronic element 140 are arranged upward, that is, when the electronic element 140 is built up in a face-up manner, the electrode (not shown) of the electronic element 140 is also a lower resin layer. 234.

このように、下部樹脂層234が上部樹脂層236よりも厚い非対称構造の第1絶縁体230を用いることにより、キャビティ114内部の残存空間、ビアホールの内部の空間、内層回路112間の空間、内層回路112と電子素子140の電極との間の空間が全て満たされることになり、キャビティ114、ビアホール内部、内層回路112間の空間、内層回路112と電子素子140の電極(図示せず)との間の空間にボイドが発生することを防止することができる。   Thus, by using the first insulator 230 having an asymmetric structure in which the lower resin layer 234 is thicker than the upper resin layer 236, the remaining space inside the cavity 114, the space inside the via hole, the space between the inner layer circuits 112, the inner layer The space between the circuit 112 and the electrode of the electronic element 140 is all filled, and the space between the cavity 114, the via hole, the inner layer circuit 112, the inner layer circuit 112 and the electrode of the electronic element 140 (not shown). It is possible to prevent voids from occurring in the space between.

このとき、下部樹脂層234の厚さは上記上部樹脂層236の厚さの2倍〜5倍であることが好ましい。下部樹脂層が上部樹脂層の2倍〜5倍の厚さを有すると、樹脂不足によるボイドの発生をより効果的に防止することができるとともに、印刷回路基板が全体的に過度に厚くなることを防止することができる。   At this time, the thickness of the lower resin layer 234 is preferably 2 to 5 times the thickness of the upper resin layer 236. If the lower resin layer has a thickness twice to five times that of the upper resin layer, voids due to insufficient resin can be more effectively prevented, and the printed circuit board becomes excessively thick overall. Can be prevented.

次に、ステップS250で、図15に示すように、接着層120を除去し、ステップS260で、図16に示すように、コア基板110の下側に第2絶縁体230’を積層する。このとき、第2絶縁体230’にはガラス繊維のような補強材232’が含浸されていてもよく、含浸されていなくてもよい。図16に示すように、補強材232’が含浸された場合、補強材の両面に積層された樹脂層234’,236’の厚さは、互いに同一であってもよく、必要により、異なってもよい。   Next, in step S250, the adhesive layer 120 is removed as shown in FIG. 15, and in step S260, a second insulator 230 'is stacked on the lower side of the core substrate 110 as shown in FIG. At this time, the second insulator 230 'may or may not be impregnated with a reinforcing material 232' such as glass fiber. As shown in FIG. 16, when the reinforcing material 232 ′ is impregnated, the thicknesses of the resin layers 234 ′ and 236 ′ laminated on both surfaces of the reinforcing material may be the same as each other, and may differ depending on necessity. Also good.

その後、図16に示すように、第1絶縁体230の表面及び第2絶縁体230’の表面に回路パターン162を形成する。第1絶縁体230の表面及び第2絶縁体の表面に形成された回路パターン162はソルダーレジスト160で保護されることができる。より高い層数の印刷回路基板を製造しようとする場合は、ソルダーレジスト160を形成せずにレイアップ工程をさらに行えばよいことは、言うまでもない。   Thereafter, as shown in FIG. 16, a circuit pattern 162 is formed on the surface of the first insulator 230 and the surface of the second insulator 230 '. The circuit pattern 162 formed on the surface of the first insulator 230 and the surface of the second insulator can be protected by the solder resist 160. Needless to say, when a printed circuit board having a higher number of layers is to be manufactured, the lay-up process may be further performed without forming the solder resist 160.

ここで、本実施例の絶縁体、電子素子内蔵型印刷回路基板、電子素子内蔵型印刷回路基板の製造方法は、例えば、コア基板を提供する工程、接着層を付着する工程等の各工程は駆動制御部(図示せず)の駆動により行われるものである。各工程の工程順等のプログラム(命令)が記憶されたメモリ(図示せず)からCPU(図示せず)は、プログラムを読み出して制御信号を当該駆動制御部(図示せず)等に送信することにより各工程が実行される。   Here, the manufacturing method of the insulator, the electronic element built-in type printed circuit board, and the electronic element built-in type printed circuit board according to the present embodiment includes, for example, a step of providing a core substrate and a step of attaching an adhesive layer This is performed by driving a drive control unit (not shown). A CPU (not shown) reads a program from a memory (not shown) in which a program (command) such as a process order of each process is stored, and transmits a control signal to the drive control unit (not shown). Thus, each process is executed.

以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加えることが可能であることが当業者に明らかである。その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、特許請求の範囲の記載から明らかである。   As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

110 コア基板
120 接着層
130,230 第1絶縁体
140 電子素子
150 第2絶縁体
154 補強材
110 Core substrate 120 Adhesive layer 130, 230 First insulator 140 Electronic element 150 Second insulator 154 Reinforcing material

Claims (8)

キャビティにより貫通され、表面に回路パターンが設けられたコア基板を提供する工程と、
前記コア基板の下面に前記キャビティをカバーするように接着層を付着する工程と、
前記キャビティに対応する前記接着層の上面に電子素子を配置する工程と、
前記キャビティが充填されるように、前記コア基板の上面に補強材が含浸されていない第1絶縁体を積層して前記回路パターンをカバーする工程と、
前記コア基板の上下側に、補強材が含浸された第2絶縁体を積層する工程と、
を含むことを特徴とする電子素子内蔵型印刷回路基板の製造方法。
Providing a core substrate penetrated by the cavity and provided with a circuit pattern on the surface;
Attaching an adhesive layer to cover the cavity on the lower surface of the core substrate;
Disposing an electronic element on the upper surface of the adhesive layer corresponding to the cavity;
Stacking a first insulator that is not impregnated with a reinforcing material on an upper surface of the core substrate so as to fill the cavity, and covering the circuit pattern;
Laminating a second insulator impregnated with a reinforcing material on the upper and lower sides of the core substrate;
The manufacturing method of the printed circuit board with a built-in electronic element characterized by including these.
前記第1絶縁体と前記第2絶縁体の樹脂が同じ材質であることを特徴とする請求項1に記載の電子素子内蔵型印刷回路基板の製造方法。   The method of manufacturing a printed circuit board with built-in electronic elements according to claim 1, wherein the resin of the first insulator and the second insulator are made of the same material. キャビティにより貫通され、表面に内層回路が設けられたコア基板と、
前記キャビティに内蔵される電子素子と、
前記キャビティを充填しかつ前記内層回路をカバーするように、前記コア基板の上面に積層された、補強材が含浸されていない第1絶縁体と、
前記コア基板の上下側にそれぞれ積層された、補強材が含浸された第2絶縁体と、
前記第2絶縁体に形成された回路パターンと、
を含むことを特徴とする電子素子内蔵型印刷回路基板。
A core substrate penetrated by a cavity and provided with an inner layer circuit on its surface;
An electronic element built in the cavity;
A first insulator that is laminated on an upper surface of the core substrate so as to fill the cavity and cover the inner layer circuit, and is not impregnated with a reinforcing material;
A second insulator that is respectively laminated on the upper and lower sides of the core substrate and impregnated with a reinforcing material;
A circuit pattern formed on the second insulator;
A printed circuit board with a built-in electronic element, comprising:
前記第1絶縁体と前記第2絶縁体の樹脂が同じ材質であることを特徴とする請求項3に記載の電子素子内蔵型印刷回路基板。   The printed circuit board with built-in electronic elements according to claim 3, wherein the resin of the first insulator and the second insulator are made of the same material. キャビティにより貫通され、表面に回路パターンが設けられたコア基板を提供する工程と、
前記コア基板の下面に前記キャビティをカバーする接着層を付着する工程と、
前記キャビティに対応する前記接着層の上面に電子素子を配置する工程と、
前記キャビティが充填されるように、補強材を中心として上下にそれぞれ上部樹脂層と下部樹脂層が形成された絶縁体を前記コア基板の上面に積層する工程と、を含み、
前記絶縁体は、前記下部樹脂層が前記上部樹脂層よりも厚い非対称形状であることを特徴とする電子素子内蔵型印刷回路基板の製造方法。
Providing a core substrate penetrated by the cavity and provided with a circuit pattern on the surface;
Attaching an adhesive layer covering the cavity to the lower surface of the core substrate;
Disposing an electronic element on the upper surface of the adhesive layer corresponding to the cavity;
Laminating an insulator in which an upper resin layer and a lower resin layer are formed on the upper and lower sides around a reinforcing material so as to fill the cavity, respectively, on the upper surface of the core substrate,
The method of manufacturing a printed circuit board with built-in electronic elements, wherein the insulator has an asymmetric shape in which the lower resin layer is thicker than the upper resin layer.
前記下部樹脂層の厚さが、前記上部樹脂層の厚さの2倍〜5倍であることを特徴とする請求項5に記載の電子素子内蔵型印刷回路基板の製造方法。   6. The method of manufacturing a printed circuit board with built-in electronic elements according to claim 5, wherein the thickness of the lower resin layer is 2 to 5 times the thickness of the upper resin layer. 印刷回路基板の製造に用いられる絶縁体であって、
補強材の上下にそれぞれ積層された上部樹脂層と下部樹脂層を含み、
前記下部樹脂層が前記上部樹脂層よりも厚いことを特徴とする絶縁体。
An insulator used in the manufacture of printed circuit boards,
Including an upper resin layer and a lower resin layer respectively laminated on the top and bottom of the reinforcing material,
The insulator, wherein the lower resin layer is thicker than the upper resin layer.
前記下部樹脂層の厚さが、前記上部樹脂層の厚さの2倍〜5倍であることを特徴とする請求項7に記載の絶縁体。   The insulator according to claim 7, wherein the thickness of the lower resin layer is 2 to 5 times the thickness of the upper resin layer.
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JP2013197136A (en) * 2012-03-16 2013-09-30 Ngk Spark Plug Co Ltd Component built-in wiring board manufacturing method
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