JP2011014713A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2011014713A
JP2011014713A JP2009157497A JP2009157497A JP2011014713A JP 2011014713 A JP2011014713 A JP 2011014713A JP 2009157497 A JP2009157497 A JP 2009157497A JP 2009157497 A JP2009157497 A JP 2009157497A JP 2011014713 A JP2011014713 A JP 2011014713A
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Prior art keywords
plate thickness
semiconductor device
lead
lead frame
semiconductor
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JP5072911B2 (en
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Shinya Nakagawa
信也 中川
Hisashi Kawato
寿 川藤
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing temperature rise in a substrate junction by inhibiting heat generated by a semiconductor chip from being transmitted to an outer terminal, without loss of an effective area for chip mounting.SOLUTION: The semiconductor device includes a leadframe 4 and a semiconductor chip 2 as a semiconductor element mounted on the leadframe 4. The leadframe 4 includes: a chip mount 4c as a semiconductor element mount having a board thickness t1 as a first thickness on which the semiconductor chip 2 is mounted; a bridge 4b extending from the chip mount 4c and having a board thickness t2 as a second thickness which is less than the thickness t1; and a lead 4a extending from the bridge 4b and having a board thickness t3 as a third thickness which is more than the thickness t2.

Description

本発明は半導体装置に関し、特に半導体チップが搭載されたリードフレームを備える電力用半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device including a lead frame on which a semiconductor chip is mounted.

半導体装置の一例としての電力用半導体装置であるトランスファーモールド構造パッケージのＤＩＰＩＰＭ（デュアルインラインパッケージインテリジェントパワーモジュール）では、内部絶縁距離の確保と、放熱する放熱ブロック（ヒートシンク）との高さ調整とを行うために、半導体チップを搭載したダイパットを沈める処理を行う（特許文献１参照）。   In a transfer mold structure package DIPIPM (dual inline package intelligent power module) which is a power semiconductor device as an example of a semiconductor device, an internal insulation distance is secured and a height of a heat dissipation block (heat sink) is adjusted. Therefore, a process of sinking a die pad on which a semiconductor chip is mounted is performed (see Patent Document 1).

特開２００３−３１７５２号公報JP 2003-31752 A

ダイパットを沈める方法としては、曲げディプレス処理（プレス加工によりダイパット部分を沈める処理）による方法がとられるが、この曲げディプレス処理で曲げた部分のおよそ０．３ｍｍ付近のエリアは、曲げディプレス処理時の肉寄りの影響でチップ搭載部として活用できない領域となり、チップ搭載有効エリアのロスが生じてしまうという問題があった。また、曲げた部分であるダイパット端のフレーム厚みは、ダイパットを含めた他の部分の板厚とほぼ同等であり、半導体チップの発熱がフレームを介してアウター端子へ伝わり、半導体装置が搭載される基板との接合部の温度が上昇するという問題があった。   As a method of sinking the die pad, a method by bending depressing treatment (processing of sinking the die pad portion by pressing) is adopted, but the area around 0.3 mm of the bent portion by this bending depressing treatment is bent bending press. There is a problem that it becomes an area that cannot be used as a chip mounting portion due to the influence of the meat at the time of processing, resulting in a loss of the chip mounting effective area. The frame thickness at the end of the die pad, which is a bent portion, is almost the same as the plate thickness of other portions including the die pad, and the heat generated by the semiconductor chip is transmitted to the outer terminal through the frame, so that the semiconductor device is mounted. There was a problem that the temperature of the junction with the substrate increased.

本発明は上記のような問題を解決するためになされたものであり、半導体チップによる発熱がフレームを介してアウター端子に伝わることを抑制することにより基板接合部の温度上昇を防ぎ、またチップ搭載有効エリアをロスしない半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and prevents the temperature rise of the substrate bonding portion by suppressing the heat generated by the semiconductor chip from being transmitted to the outer terminal via the frame. It is an object to provide a semiconductor device that does not lose an effective area.

この発明は、リードフレームと、前記リードフレーム上に搭載された半導体素子とを備える半導体装置であって、前記リードフレームは、前記半導体素子を搭載し、第１の板厚を有する半導体素子搭載部と、前記半導体素子搭載部から延在し、前記第１の板厚より薄い第２の板厚を有する架橋部と、前記架橋部から延在し、前記第２の板厚より厚い第３の板厚を有するリード部とを備える。   The present invention is a semiconductor device comprising a lead frame and a semiconductor element mounted on the lead frame, wherein the lead frame mounts the semiconductor element and has a first plate thickness A bridging portion extending from the semiconductor element mounting portion and having a second plate thickness that is smaller than the first plate thickness; and a third bridging portion extending from the bridging portion and thicker than the second plate thickness. A lead portion having a plate thickness.

この発明によれば、リードフレームと、前記リードフレーム上に搭載された半導体素子とを備える半導体装置であって、前記リードフレームは、前記半導体素子を搭載し、第１の板厚を有する半導体素子搭載部と、前記半導体素子搭載部から延在し、前記第１の板厚より薄い第２の板厚を有する架橋部と、前記架橋部から延在し、前記第２の板厚より厚い第３の板厚を有するリード部とを備えることにより、半導体素子から発生する熱がアウター端子に伝わって基板接合部の温度が上昇することの抑制が可能となる。また、曲げディプレス処理によりリードフレームを形成する場合にも、架橋部を設けることにより肉寄りの影響を受けず、チップ搭載有効エリアをロスせず利用できる。   According to the present invention, a semiconductor device comprising a lead frame and a semiconductor element mounted on the lead frame, wherein the lead frame has the first plate thickness mounted with the semiconductor element. A mounting portion; a bridge portion extending from the semiconductor element mounting portion and having a second plate thickness that is smaller than the first plate thickness; and a second portion extending from the bridge portion and thicker than the second plate thickness. By providing the lead portion having the plate thickness of 3, it is possible to prevent the heat generated from the semiconductor element from being transmitted to the outer terminal and the temperature of the substrate bonding portion from rising. Also, when a lead frame is formed by bending depressing treatment, it is possible to use the chip mounting effective area without losing the effect of fleshing by providing a bridging portion.

本発明の実施の形態１にかかる半導体装置の全体図である。1 is an overall view of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる半導体装置の詳細図である。1 is a detailed view of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態２にかかる半導体装置の上面および側面から見た詳細図である。It is the detailed view seen from the upper surface and side surface of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかる半導体装置の詳細図である。It is a detailed view of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態４にかかる半導体装置の詳細図である。FIG. 6 is a detailed view of a semiconductor device according to a fourth embodiment of the present invention.

＜Ａ．実施の形態１＞
＜Ａ−１．構成＞
図１は、本発明にかかる半導体装置１００の全体図である。図１に示すのは、半導体チップ２をリードフレーム４に搭載した状態の一例に過ぎず、半導体チップ２の個数や配置、その他の周辺部の構成要素についても図１に示すような場合に限られるものではない。 <A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is an overall view of a semiconductor device 100 according to the present invention. FIG. 1 shows only an example of a state in which the semiconductor chip 2 is mounted on the lead frame 4, and the number and arrangement of the semiconductor chips 2 and other peripheral components are also limited to those shown in FIG. It is not something that can be done.

図１に示すように、板状金属のリードフレーム４は、図示しない絶縁シートを介して放熱ブロック５（ヒートシンク）上に配置され、リードフレーム４のダイパット（チップ搭載部４ｃ、図２参照）上に半導体素子である半導体チップ２が搭載されている。半導体チップ２にはボンディングワイヤ３が接続され、このボンディングワイヤ３によってリードフレーム４のリード部４ａ（図２参照）と電気的に接続されている。さらに、放熱ブロック５、リードフレーム４、半導体チップ２を含めた領域が封止樹脂１で覆われ、リード部４ａが封止樹脂１から引き出されて上方に曲折されている。   As shown in FIG. 1, a plate-like metal lead frame 4 is disposed on a heat dissipation block 5 (heat sink) via an insulating sheet (not shown), and on a die pad (chip mounting portion 4c, see FIG. 2) of the lead frame 4. The semiconductor chip 2 which is a semiconductor element is mounted. A bonding wire 3 is connected to the semiconductor chip 2, and the bonding wire 3 is electrically connected to the lead portion 4 a (see FIG. 2) of the lead frame 4. Further, the region including the heat dissipation block 5, the lead frame 4, and the semiconductor chip 2 is covered with the sealing resin 1, and the lead portion 4a is drawn from the sealing resin 1 and bent upward.

図２は、図１に示したリードフレーム４のダイパット（チップ搭載部４ｃ）とその近傍を示すもので、リードフレーム４のリード部４ａと、チップ搭載部４ｃと、両者の接続部分である架橋部４ｂとを詳細に示した図である。   FIG. 2 shows the die pad (chip mounting portion 4c) of the lead frame 4 shown in FIG. 1 and the vicinity thereof. The lead portion 4a of the lead frame 4, the chip mounting portion 4c, and a bridge that is a connecting portion between them. It is the figure which showed the part 4b in detail.

リードフレーム４のチップ搭載部４ｃは、放熱する放熱ブロック５（ヒートシンク）の高さ調整のためリードフレーム４の第１の面である表面に対し表面後退処理を行い、図に示すように第１の板厚として所定の板厚ｔ１を有するように形成される。半導体チップ２は、例えば図２に示すようにチップ搭載部４ｃに搭載される。   The chip mounting portion 4c of the lead frame 4 performs a surface receding process on the surface, which is the first surface of the lead frame 4, in order to adjust the height of the heat dissipation block 5 (heat sink) that radiates heat. Is formed to have a predetermined thickness t1. The semiconductor chip 2 is mounted on the chip mounting portion 4c, for example, as shown in FIG.

リードフレーム４の架橋部４ｂは、チップ搭載部４ｃから延在し、図２に示すように、リードフレーム４の第１の面である表面およびリードフレーム４の第２の面である裏面それぞれから表面後退処理が行われることにより、チップ搭載部４ｃの板厚ｔ１（第１の板厚）よりも薄い板厚ｔ２（第２の板厚）を有するように形成される。   The bridging portion 4b of the lead frame 4 extends from the chip mounting portion 4c, and from each of the front surface that is the first surface of the lead frame 4 and the back surface that is the second surface of the lead frame 4, as shown in FIG. By performing the surface receding process, the chip mounting portion 4c is formed to have a plate thickness t2 (second plate thickness) smaller than the plate thickness t1 (first plate thickness).

リードフレーム４のリード部４ａは、架橋部４ｂから延在し、図２に示すように、リードフレーム４の第２の面である裏面から表面後退処理が行われることにより、架橋部４ｂの板厚ｔ２（第２の板厚）よりも厚い板厚ｔ３（第３の板厚）を有するように形成される。図１に示すように、チップ搭載部４ｃの下部には放熱ブロック５が配置されており、この放熱ブロック５（ヒートシンク）との絶縁距離を保つため、第２の面である裏面の表面後退処理の深さは０．１２ｍｍ、望ましくは０．２ｍｍ以上あると良い。   The lead portion 4a of the lead frame 4 extends from the bridging portion 4b, and as shown in FIG. 2, the surface of the lead frame 4 is subjected to a surface receding process from the back surface, which is the second surface, thereby the plate of the bridging portion 4b. It is formed to have a plate thickness t3 (third plate thickness) thicker than the thickness t2 (second plate thickness). As shown in FIG. 1, a heat radiating block 5 is disposed below the chip mounting portion 4c. In order to maintain an insulation distance from the heat radiating block 5 (heat sink), the back surface of the back surface is a second surface. The depth of is 0.12 mm, preferably 0.2 mm or more.

前述の表面後退処理としては、曲げディプレス処理の他、表面エッチング処理、切削処理（ハーフカット）等が考えられる。   As the above-described surface receding process, a surface etching process, a cutting process (half cut), etc. can be considered in addition to the bending depression process.

＜Ａ−２．動作＞
架橋部４ｂを図２の示すように形成することで、チップ搭載部４ｃとリード部４ａとを接続する熱伝導体としての架橋部４ｂの板厚ｔ２（第２の板厚）はチップ搭載部４ｃの板厚ｔ１（第１の板厚）およびリード部４ａの板厚ｔ３（第３の板厚）よりも薄く、そのため架橋部４ｂの断面積が小さく抑えられ、従来よりも熱伝導率が低くなる。よって、チップ搭載部４ｃに搭載された半導体チップ２において発生した熱が、チップ搭載部４ｃに伝わり、さらに架橋部４ｂを介してリード部４ａへと伝わることを抑制し、半導体装置１００と基板（図示せず）との接合部の温度上昇を抑制することが可能となる。 <A-2. Operation>
By forming the bridging portion 4b as shown in FIG. 2, the thickness t2 (second plate thickness) of the bridging portion 4b as a heat conductor connecting the chip mounting portion 4c and the lead portion 4a is the chip mounting portion. It is thinner than the plate thickness t1 (first plate thickness) of 4c and the plate thickness t3 (third plate thickness) of the lead portion 4a, so that the cross-sectional area of the bridging portion 4b is kept small, and the thermal conductivity is higher than in the past. Lower. Therefore, the heat generated in the semiconductor chip 2 mounted on the chip mounting portion 4c is transmitted to the chip mounting portion 4c and further to the lead portion 4a via the bridging portion 4b, and the semiconductor device 100 and the substrate ( It is possible to suppress the temperature rise at the joint with (not shown).

＜Ａ−３．効果＞
この発明にかかる実施の形態１によれば、リードフレーム４と、リードフレーム４上に搭載された半導体素子である半導体チップ２とを備える半導体装置であって、リードフレーム４は、半導体チップ２を搭載し、第１の板厚である板厚ｔ１を有する半導体素子搭載部であるチップ搭載部４ｃと、チップ搭載部４ｃから延在し、板厚ｔ１より薄い第２の板厚である板厚ｔ２を有する架橋部４ｂと、架橋部４ｂから延在し、板厚ｔ２より厚い第３の板厚である板厚ｔ３を有するリード部４ａとを備えることで、熱伝導体としての架橋部４ｂの、チップ搭載部４ｃとリード部４ａとを結ぶ方向と垂直な方向の断面積を小さくすることにより、半導体チップ２による発熱をリード部４ａへ熱伝導することを抑制し、半導体装置１００と基板（図示せず）との接合部の温度上昇を抑制することが可能となる。 <A-3. Effect>
According to the first embodiment of the present invention, a semiconductor device including a lead frame 4 and a semiconductor chip 2 which is a semiconductor element mounted on the lead frame 4, the lead frame 4 includes the semiconductor chip 2. A chip mounting portion 4c that is a semiconductor element mounting portion having a thickness t1 that is a first thickness, and a plate thickness that extends from the chip mounting portion 4c and that is a second thickness smaller than the thickness t1. By providing a bridging portion 4b having t2 and a lead portion 4a extending from the bridging portion 4b and having a plate thickness t3 that is a third plate thickness greater than the plate thickness t2, the bridging portion 4b as a heat conductor. By reducing the cross-sectional area in the direction perpendicular to the direction connecting the chip mounting portion 4c and the lead portion 4a, heat conduction from the semiconductor chip 2 to the lead portion 4a is suppressed, and the semiconductor device 100 and the substrate (Not shown ) And it is possible to suppress the temperature rise of the junction.

また、この発明にかかる実施の形態１によれば、半導体装置において、半導体素子搭載部であるチップ搭載部４ｃと架橋部４ｂとは、リードフレーム４の第１の面である表面から表面後退処理が行われており、リード部４ａと架橋部４ｂは、リードフレーム４の第２の面である裏面から表面後退処理が行われていることで、架橋部４ｂの板厚ｔ２である第２の板厚を、チップ搭載部４ｃの板厚ｔ１（第１の板厚）およびリード部４ａの板厚ｔ３（第３の板厚）よりも薄くすることが可能となり、半導体チップ２からリード部４ａへの熱伝導を抑制することができる。   Also, according to the first embodiment of the present invention, in the semiconductor device, the chip mounting portion 4c and the bridging portion 4b which are semiconductor element mounting portions are subjected to a surface retreat process from the surface which is the first surface of the lead frame 4. The lead portion 4a and the bridging portion 4b are subjected to the surface receding process from the back surface, which is the second surface of the lead frame 4, so that the second thickness which is the plate thickness t2 of the bridging portion 4b is obtained. The plate thickness can be made thinner than the plate thickness t1 (first plate thickness) of the chip mounting portion 4c and the plate thickness t3 (third plate thickness) of the lead portion 4a. Heat conduction to the can be suppressed.

＜Ｂ．実施の形態２＞
＜Ｂ−１．構成＞
図３は、図２に示した本発明にかかる半導体装置１００を上面および側面から見た図である。図２に示したチップ搭載部４ｃには半導体チップ２が搭載されているが、簡単のため図示を省略する。なお、図中に示した寸法は、具体的設計における一例であり、本発明がこの寸法に限定されるわけではない。 <B. Second Embodiment>
<B-1. Configuration>
FIG. 3 is a top view and a side view of the semiconductor device 100 according to the present invention shown in FIG. Although the semiconductor chip 2 is mounted on the chip mounting portion 4c shown in FIG. 2, the illustration is omitted for simplicity. In addition, the dimension shown in the figure is an example in a concrete design, and this invention is not necessarily limited to this dimension.

図３（ａ）は、架橋部４ｂに図に示すような切欠き１０１を形成する場合である。切欠き１０１の大きさ、範囲、位置等は適宜決定可能であるが、フレームの剛性を保つために幅方向の１／２程度が望ましい。   FIG. 3A shows a case where a notch 101 as shown in the figure is formed in the bridging portion 4b. The size, range, position, and the like of the notch 101 can be determined as appropriate, but about half of the width direction is desirable in order to maintain the rigidity of the frame.

図３（ｂ）は、架橋部４ｂに図に示すような穴１０２を形成する場合である。この場合も穴１０２の大きさ、範囲、位置等は適宜決定可能である。   FIG. 3B shows a case where a hole 102 as shown in the figure is formed in the bridging portion 4b. Also in this case, the size, range, position, etc. of the hole 102 can be determined as appropriate.

このように切欠き１０１、穴１０２を形成することで、架橋部４ｂを介してリード部４ａへ熱が伝わることをさらに抑制し、半導体装置１００と基板（図示せず）との接合部の温度上昇を抑制することができる。   By forming the notch 101 and the hole 102 in this way, it is possible to further suppress the heat from being transmitted to the lead portion 4a via the bridging portion 4b, and the temperature of the junction between the semiconductor device 100 and the substrate (not shown). The rise can be suppressed.

＜Ｂ−２．効果＞
この発明にかかる実施の形態２によれば、半導体装置において、架橋部４ｂに、切欠き１０１あるいは穴１０２が設けられたことで、半導体チップ２からリード部４ａへの伝熱が更に抑制され、半導体装置１００と基板（図示せず）との接合部の温度上昇を抑制することが可能となる。 <B-2. Effect>
According to the second embodiment of the present invention, in the semiconductor device, by providing the notch 101 or the hole 102 in the bridging portion 4b, heat transfer from the semiconductor chip 2 to the lead portion 4a is further suppressed, It is possible to suppress the temperature rise at the junction between the semiconductor device 100 and the substrate (not shown).

＜Ｃ．実施の形態３＞
＜Ｃ−１．構成＞
図４（ａ）は、リードフレーム４のリード部４ａとチップ搭載部４ｃと、両者の接続部分である架橋部４ｂとを詳細に示した図であり、図４（ｂ）は、架橋部４ｂとチップ搭載部４ｃとの間の端部１０３の形状をさらに詳細に示した図である。 <C. Embodiment 3>
<C-1. Configuration>
FIG. 4A is a diagram showing in detail the lead portion 4a and the chip mounting portion 4c of the lead frame 4, and the bridging portion 4b which is a connecting portion between them, and FIG. 4B is a bridging portion 4b. It is the figure which showed in more detail the shape of the edge part 103 between a chip mounting part 4c.

架橋部４ｂとチップ搭載部４ｃは、リードフレーム４の第１の面である表面から表面後退処理としての曲げディプレス処理が行われ、リード部４ａと架橋部４ｂは、リードフレーム４の第２の面である裏面から表面後退処理である曲げディプレス処理が行われることにより、図４（ｂ）において示すように、架橋部４ｂとチップ搭載部４ｃとの間の端部１０３がダレとなる。   The bridging portion 4b and the chip mounting portion 4c are subjected to a bending depression process as a surface receding process from the surface which is the first surface of the lead frame 4, and the lead portion 4a and the bridging portion 4b are connected to the second portion of the lead frame 4. As shown in FIG. 4B, the end portion 103 between the bridging portion 4b and the chip mounting portion 4c becomes sag as a result of the bending depressing process being the surface receding process being performed from the back surface, which is the surface of the substrate. .

具体的な工程としては、図４（ａ）に示されるような形状に対応する空間を有する上下プレス（金型）等によって圧縮し形成する。   As a specific process, it is formed by compression with an upper and lower press (mold) having a space corresponding to the shape as shown in FIG.

＜Ｃ−２．動作＞
曲げディプレス処理によって図４（ａ）に示すような構造を形成する場合、曲げた部分であるリード部４ａの端部１０４に、肉寄りの影響で半導体チップ２を搭載できないエリアが形成されてしまうが、本発明においては架橋部４ｂを設けたことによりリード部４ａの端部１０４は半導体チップ２の搭載位置より離れた位置に配置されるので、チップ搭載有効エリアは肉寄りの影響を受けることなく活用できる。 <C-2. Operation>
When the structure as shown in FIG. 4A is formed by the bending depression process, an area where the semiconductor chip 2 cannot be mounted is formed at the end portion 104 of the lead portion 4a which is a bent portion due to the influence of the flesh. However, in the present invention, since the end portion 104 of the lead portion 4a is disposed at a position away from the mounting position of the semiconductor chip 2 by providing the bridging portion 4b, the chip mounting effective area is affected by the flesh. Can be used without

また、他の表面後退処理（表面エッチング処理、切削処理等）によってバリ、エッジ等が形成される場合がある。この場合、封止樹脂１硬化時にそのバリ、エッジ等に応力が集中し、絶縁シート（図示せず）との密着性の阻害等の問題が生じるが、当該曲げディプレス処理によって、図４（ｂ）に示すようなダレが端部１０３に形成される場合には、そのような問題は解消される。   Further, burrs, edges, and the like may be formed by other surface receding processes (surface etching process, cutting process, etc.). In this case, when the sealing resin 1 is cured, stress concentrates on the burrs, edges, and the like, and problems such as inhibition of adhesion to the insulating sheet (not shown) occur. When the sagging as shown in b) is formed at the end portion 103, such a problem is solved.

＜Ｃ−３．効果＞
この発明にかかる実施の形態３によれば、半導体装置において、表面後退処理は、曲げディプレス処理であることで、絶縁シート（図示せず）との密着性を阻害するバリの発生を防ぎ、密着性を向上させることが可能となる。 <C-3. Effect>
According to the third embodiment of the present invention, in the semiconductor device, the surface receding process is a bending depression process, thereby preventing the occurrence of burrs that hinder the adhesion with the insulating sheet (not shown), It becomes possible to improve adhesiveness.

また、曲げディプレス処理をした場合には、曲げた部分に肉寄りの影響によりチップ搭載部４ｃには活用できない領域が存在するが、本発明においては曲げた部分と、半導体チップ２を搭載するチップ搭載部４ｃとの間に架橋部４ｂが介在しており、チップ搭載有効エリアと曲げた部分が隣接しないため、チップ搭載有効エリアのロスが生じるという問題は生じない。   Further, when the bending depression process is performed, there is a region that cannot be used for the chip mounting portion 4c due to the influence of flesh in the bent portion. In the present invention, the bent portion and the semiconductor chip 2 are mounted. Since the bridging portion 4b is interposed between the chip mounting portion 4c and the bent portion is not adjacent to the chip mounting effective area, there is no problem of loss of the chip mounting effective area.

＜Ｄ．実施の形態４＞
＜Ｄ−１．構成＞
図５は、本発明にかかる半導体装置１００の寸法の概略を示した図である。 <D. Embodiment 4>
<D-1. Configuration>
FIG. 5 is a diagram schematically showing the dimensions of the semiconductor device 100 according to the present invention.

例えば実施の形態１に示したような、リードフレーム４の表面（第１の面）と裏面（第２の面）において表面後退処理を行った架橋部４ｂを設けることにより、リードフレーム４の表面（第１の面）において、リード部４ａ上の所定位置から架橋部４ｂのリード部４ａ側の端部１０４までの距離をＧとし、リードフレーム４の裏面（第２の面）において、リード部４ａ上の前記所定位置から架橋部４ｂのチップ搭載部４ｃ側の端部１０３までの距離をＨとすると、Ｈ＞Ｇの関係が成り立つ。   For example, as shown in the first embodiment, the surface of the lead frame 4 is provided by providing the bridging portion 4b that has been subjected to the surface receding process on the front surface (first surface) and the back surface (second surface) of the lead frame 4. On the first surface, the distance from the predetermined position on the lead portion 4a to the end portion 104 on the lead portion 4a side of the bridging portion 4b is G, and the lead portion on the back surface (second surface) of the lead frame 4 When the distance from the predetermined position on 4a to the end portion 103 on the chip mounting portion 4c side of the bridging portion 4b is H, the relationship of H> G is established.

また図５に示すように、板厚ｔ３＞板厚ｔ１となるようにリード部４ａおよびチップ搭載部４ｃを形成することが可能である。   Further, as shown in FIG. 5, the lead portion 4a and the chip mounting portion 4c can be formed so that the plate thickness t3> the plate thickness t1.

＜Ｄ−２．動作＞
Ｈ＞Ｇが成り立つことにより、梱包時の積み重ねが垂直にできるため梱包ロスが少なくなる。 <D-2. Operation>
By satisfying H> G, stacking at the time of packing can be made vertical, so that packing loss is reduced.

また、板厚ｔ３＞板厚ｔ１となるようにリード部４ａおよびチップ搭載部４ｃを形成することにより、リードフレーム４を重ね合わせた場合にそれぞれのチップ搭載部４ｃ間に板厚ｔ３と板厚ｔ１との差分の隙間ができ、梱包輸送等を行う場合にそれぞれのチップ搭載部４ｃ間の干渉がなくなる。   Further, by forming the lead portion 4a and the chip mounting portion 4c so that the plate thickness t3> the plate thickness t1, when the lead frame 4 is overlapped, the plate thickness t3 and the plate thickness are between the chip mounting portions 4c. A gap with a difference from t1 is formed, and interference between the chip mounting portions 4c is eliminated when performing packaging transportation or the like.

なお、図５においては、架橋部４ｂの裏面とリード部４ａの裏面、架橋部４ｂの表面とチップ搭載部４ｃの表面、それぞれが面一となる場合を示しているが、架橋部４ｂの裏面がリード部４ａの裏面と面一でない場合、および架橋部４ｂの表面がチップ搭載部４ｃの表面と面一でない場合でも、リード部４ａの板厚ｔ３（第３の板厚）よりチップ搭載部４ｃの板厚ｔ１（第１の板厚）が薄ければ、梱包時において同様にチップ搭載部４ｃ間の干渉を防ぐことが可能である。   FIG. 5 shows the case where the back surface of the bridging portion 4b and the back surface of the lead portion 4a, the surface of the bridging portion 4b, and the surface of the chip mounting portion 4c are flush with each other. Even when the back surface of the lead portion 4a is not flush with the back surface of the lead portion 4a and when the surface of the bridging portion 4b is not flush with the surface of the chip mounting portion 4c, the chip mounting portion is determined from the plate thickness t3 (third plate thickness) of the lead portion 4a. If the plate thickness t1 (first plate thickness) of 4c is thin, it is possible to similarly prevent interference between the chip mounting portions 4c during packaging.

＜Ｄ−３．効果＞
この発明にかかる実施の形態４によれば、半導体装置において、リード部４ａの第３の板厚（板厚ｔ３）より半導体素子搭載部であるチップ搭載部４ｃの第１の板厚（板厚ｔ１）が薄いことで、梱包輸送時にはリード部４ａ同士のみが接触するように梱包することができるので、ダイパット（チップ搭載部４ｃ）同士の干渉がなくなり、品質安定性を向上させることが可能となる。 <D-3. Effect>
According to the fourth embodiment of the present invention, in the semiconductor device, the first plate thickness (plate thickness) of the chip mounting portion 4c, which is the semiconductor element mounting portion, from the third plate thickness (plate thickness t3) of the lead portion 4a. Since t1) is thin, it can be packed so that only the lead portions 4a are in contact with each other during package transportation, so there is no interference between die pads (chip mounting portions 4c), and quality stability can be improved. Become.

また、梱包時の積み重ねが垂直に出来るため、梱包ロスが少なくなる。   Moreover, since the stacking at the time of packing can be performed vertically, packing loss is reduced.

１ 封止樹脂、２ 半導体チップ、３ ボンディングワイヤ、４ リードフレーム、４ａ リード部、４ｂ 架橋部、４ｃ チップ搭載部、５ 放熱ブロック、１００ 半導体装置、１０１ 切欠き、１０２ 穴、１０３，１０４ 端部。   DESCRIPTION OF SYMBOLS 1 Sealing resin, 2 Semiconductor chip, 3 Bonding wire, 4 Lead frame, 4a Lead part, 4b Bridging part, 4c Chip mounting part, 5 Heat dissipation block, 100 Semiconductor device, 101 Notch, 102 Hole, 103,104 End .

Claims (5)

リードフレームと、
前記リードフレーム上に搭載された半導体素子と、
を備える半導体装置であって、
前記リードフレームは、
前記半導体素子を搭載し、第１の板厚を有する半導体素子搭載部と、
前記半導体素子搭載部から延在し、前記第１の板厚より薄い第２の板厚を有する架橋部と、
前記架橋部から延在し、前記第２の板厚より厚い第３の板厚を有するリード部とを備える、
半導体装置。 A lead frame;
A semiconductor element mounted on the lead frame;
A semiconductor device comprising:
The lead frame is
A semiconductor element mounting portion mounted with the semiconductor element and having a first plate thickness;
A bridging portion extending from the semiconductor element mounting portion and having a second plate thickness smaller than the first plate thickness;
A lead portion extending from the bridging portion and having a third plate thickness greater than the second plate thickness;
Semiconductor device. 前記半導体素子搭載部と前記架橋部は、前記リードフレームの第１の面から表面後退処理が行われており、
前記リード部と前記架橋部は、前記リードフレームの第２の面から表面後退処理が行われている、
請求項１に記載の半導体装置。 The semiconductor element mounting portion and the bridging portion are subjected to a surface receding process from the first surface of the lead frame,
The lead portion and the bridging portion are subjected to a surface receding process from the second surface of the lead frame.
The semiconductor device according to claim 1. 前記表面後退処理は、曲げディプレス処理である、
請求項２に記載の半導体装置。 The surface receding process is a bending depression process.
The semiconductor device according to claim 2. 前記架橋部に、切欠きあるいは穴が設けられた、
請求項１〜３のいずれかに記載の半導体装置。 The bridge portion was provided with a notch or a hole,
The semiconductor device according to claim 1. 前記リード部の前記第３の板厚より前記半導体素子搭載部の前記第１の板厚が薄い、
請求項１〜４のいずれかに記載の半導体装置。 The first plate thickness of the semiconductor element mounting portion is thinner than the third plate thickness of the lead portion;
The semiconductor device according to claim 1.
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