JP2018195648A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having high joint reliability in solder joint.SOLUTION: In a semiconductor device including a die pad 11 having one surface 11a and another surface 11b, leads 12 and a mold resin 16 which partially covers the die pad and the leads, the mod resin 16 is formed vertically asymmetrically with each other in a normal direction with respect to the one surface. When assuming that a direction from the one surface toward the other surface out of the normal direction is an upper direction and the opposite direction to the upper direction is a lower direction, the mold resin has a thickness larger in the lower direction from inner leads 121 than a thickness in the upper direction from the inner leads; and each of outer leads 122 is formed in the shape folded to a part in the lower direction. This achieves the long outer leads while inhibiting warpage of the semiconductor device to reduce force caused by the warpage or thermal stress even when the force is applied to the outer leads thereby to achieve high joint reliability when the outer leads are solder jointed to other components.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device having a heating element made of a semiconductor material and configured to radiate heat generated from the heating element from the back surface of the surface on which the heating element is mounted.

  Conventionally, as a semiconductor device including a lead frame including a die pad and a lead, a semiconductor chip mounted on the die pad and electrically connected to the lead via a wire, and a sealing member covering a part of the semiconductor chip For example, the thing of patent document 1 is known.

  A semiconductor device described in Patent Document 1 includes a semiconductor chip, a lead frame including a die pad on which the semiconductor chip is mounted, a lead, a wire that electrically connects the semiconductor chip and the lead, a semiconductor chip, and a lead frame. And a resin member for sealing the part. Specifically, the semiconductor device described in Patent Document 1 has a structure in which a resin member seals an inner lead and a die pad, a so-called full mold structure.

  In such a configuration, the inner lead covered with the resin member among the leads is arranged on the same plane as the die pad. The resin member is formed with a cut portion having a concave shape in a region overlapping with the inner lead in an outer region in a plan view. Out of the leads, the outer lead exposed from the resin member is bent so as to enter the cut portion, and has a J-shape facing the inner lead and the resin member in a sectional view.

  In other words, the die pad and the inner lead of the lead frame are arranged on the same plane, and the outer lead is bent so as to enter the cut portion of the resin member, thereby reducing the size and height of the semiconductor. It becomes a device.

JP 2000-133761 A

  By the way, in a semiconductor device including a lead frame, a semiconductor chip, and a resin member that covers a part thereof, it is important to efficiently dissipate heat generated when the semiconductor chip is driven to cool the semiconductor chip. Although the semiconductor device described in Patent Document 1 is reduced in size and height, it is difficult to increase heat dissipation because it is a full-molded device.

  On the other hand, as a structure for reducing the height of the semiconductor device, that is, reducing the thickness while improving the heat dissipation, the opposite side of the surface of the lead frame where the semiconductor chip is mounted is exposed from the resin member. A so-called half mold structure is known.

  For example, a semiconductor device having a half mold structure is mounted on a wiring substrate by solder bonding between the wiring substrate and an outer lead, and the surface opposite to the surface on which the semiconductor chip is mounted (hereinafter referred to as “rear surface”) has a thermal conductivity. It is used by being connected to a heat radiating member made of a high material. Specifically, in the semiconductor device having a half mold structure, the outer lead extends in the direction of the side where the semiconductor chip is mounted, and is bonded to the wiring substrate via solder, and the back surface and the heat dissipation substrate are bonded to each other by a bonding material. ing. In other words, in the above example, the half-molded semiconductor device is sandwiched between the wiring board and the heat dissipation member. As described above, the semiconductor device having the half mold structure has a structure capable of dissipating heat generated by driving the semiconductor chip from the back surface, and thus has a higher cooling efficiency of the semiconductor chip than the full mold structure.

  Therefore, it is conceivable that the semiconductor device described in Patent Document 1 has a half mold structure to improve heat dissipation, but the inner lead and the die pad need to be arranged on the same plane. In the half mold structure, the inner lead is a resin member. There is a risk of peeling. Therefore, when the semiconductor device described in Patent Document 1 adopts the half mold structure, the reliability with respect to peeling is significantly reduced.

  Here, the semiconductor device having a half mold structure has a structure in which the die pad protrudes from the lead by extruding the lead frame. Also, in this extrusion process, it is common to reduce the extrusion amount of the die pad so that the hanging pin connecting the die pad and the lead is not cut or damaged, so the semiconductor device of the half mold structure is thin. There is a tendency to become.

  In recent years, further reduction in thickness of semiconductor devices having a half mold structure has been studied in view of needs such as higher integration. As a result of intensive studies of the thin-molded semiconductor device by the present inventors, it has been found that the reliability of solder joints in the outer leads cannot be ensured with a structure that is simply made thin.

  Specifically, a thin semiconductor device having a half mold structure is likely to warp due to heat generated by driving a semiconductor chip, and the outer leads are shortened as the thickness is reduced. Easy to be transmitted to the joint. As a result, it has been found that the warpage or thermal stress of the semiconductor device caused by the heat generated by driving the semiconductor chip is applied to the solder joint, and the solder joint reliability can be lowered by cracking the solder.

  The present invention has been made in view of the above points, and can reduce the thermal stress applied to the outer lead while having a backside heat radiation type structure that is thinner than the conventional one, and has high solder joint reliability. An object is to provide a semiconductor device.

  In order to achieve the above object, a semiconductor device according to claim 1 includes a die pad (11) having one surface (11a) and the other surface (11b) in a front / back relationship, and a lead (12). (10), a semiconductor chip (14) mounted on one surface, a wire (15) for electrically connecting a part of the lead and the semiconductor chip, one surface of the die pad, one of the semiconductor chip, the wire and the lead A mold resin (16) covering the portion. The die pad is arranged on a plane different from the plane formed by the inner lead (121) which is a portion covered with the mold resin in the lead, and the direction from one surface to the other surface in the normal direction to the one surface is set. The thickness in the normal direction of the mold lower part (162), which is the lower part of the mold resin than the inner lead, is the upper direction, and the direction from the other surface to the one surface is the lower direction. Also, the thickness is larger than the thickness in the normal direction of the upper part (161) of the mold, which is the upper part, and the outer lead is bent to the lower part of the mold.

  As a result, the mold resin has an asymmetrical body in which the thickness of the lower part of the mold, which is the lower part of the inner lead with the inner lead as the reference position, is thicker than the thickness of the upper part of the mold, which is the upper part of the inner lead. It becomes a semiconductor device. The outer leads are arranged to be bent to the mold lower side thicker than the mold upper part, and the length of the outer leads in the vertical direction can be ensured. As a result, the semiconductor device is prevented from warping due to the effect of heat generated when the semiconductor chip is driven while being thinned, and the thermal stress is difficult to be transmitted to the opposite side of the mold resin in the outer lead. The semiconductor device is highly stable when mounted on the member.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a top layout view illustrating a semiconductor device according to a first embodiment; It is sectional drawing between II-II shown with the broken line in FIG. (A) is sectional drawing which shows the conventional semiconductor device mounted on the board | substrate, (b) is the effect | action of the force by the curvature or the thermal stress of the said semiconductor device in area | region R1 shown with the broken line in (a). It is an expanded sectional view shown about the mode of occurrence of a crack of solder by this. It is sectional drawing which shows the state with which the semiconductor device of 1st Embodiment was mounted on the board | substrate. 4 is an enlarged view of a region R2 indicated by a broken line in FIG. 4, and the action of the warp of the semiconductor device according to the first embodiment mounted on the substrate and the action of force due to thermal stress and the occurrence of solder cracks due to this are suppressed. It is an expanded sectional view shown about a mode. It is a figure which shows the simulation result about the stress which acts on the junction interface of the semiconductor chip and die pad in the conventional semiconductor device and the semiconductor device of 1st Embodiment. It is sectional drawing shown about the semiconductor device of 2nd Embodiment. It is a figure shown about the solder joint of the outer lead and board | substrate in the semiconductor device of other embodiment. It is sectional drawing shown about the semiconductor device of other embodiment. It is sectional drawing shown about the semiconductor device of other embodiment. It is sectional drawing shown about the semiconductor device of other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
The semiconductor device according to the first embodiment will be described with reference to FIGS. The semiconductor device of this embodiment is mounted on a vehicle such as an automobile, and is applied as a device for driving various electronic devices for the vehicle.

  FIG. 1 shows an upper surface layout of the semiconductor device of this embodiment viewed from the other surface 11b side of a die pad 11 to be described later shown in FIG. 2, and an outline of the mold resin 16 is indicated by a two-dot chain line. Further, in FIG. 1, a part of the semiconductor chip 14 or the wire 15 that is hidden by the die pad 11 or the inner lead 121 when viewed from the other surface 11 b side is indicated by a broken line. In FIG. 2, for convenience of description of the configuration of the mold resin 16, a plane formed by the surface of the inner lead 121 described later and an extended line of a plane formed by a part of the surface of the mold resin 16 are indicated by alternate long and short dash lines. .

  As shown in FIG. 1 or FIG. 2, the semiconductor device of this embodiment includes a lead frame 10 having a die pad 11 and leads 12, a semiconductor chip 14 mounted on one surface 11a of the die pad 11, wires 15, And a mold resin 16 covering a part of these.

  As shown in FIG. 1, the semiconductor device according to the present embodiment has a QFP having a shape in which a part of the lead 12 protrudes and is exposed from four sides of the mold resin 16 which is substantially rectangular when viewed from the other surface 11b side of the die pad 11. (Abbreviation for Quad Flat Package). Note that the semiconductor device of the present embodiment is not limited to the QFP, and may be other package shapes such as SOP (abbreviation of Small Outline Package).

  The lead frame 10 is made of a metal material such as Cu or Fe, for example. As shown in FIG. 2, the lead frame 10 includes a die pad 11 having one surface 11 a and another surface 11 b and leads 12 arranged on a different plane from the die pad 11. Have. The lead frame 10 is formed, for example, by forming an area to be the die pad 11 and the lead 12 by press punching a single metal plate and then extruding the area to be the die pad 11 by extrusion processing. The lead frame 10 may be subjected to noble metal plating such as Ag or Au as necessary from the viewpoint of improving wire bonding.

  For example, as shown in FIG. 1, the die pad 11 has one surface 11 a and another surface 11 b that are in a front-back relationship, and has a rectangular plate shape. The die pad 11 is disposed on a different plane from the leads 12 as a result of being extruded from a single metal plate, for example, by the extrusion process described above. The die pad 11 is connected to the metal plate on which the leads 12 are formed via the suspension leads 17 shown in FIG. 1 at the time of extrusion processing. However, as a result of being punched after the molding resin 16 is formed, the leads 12 It is divided.

  As shown in FIG. 2, the die pad 11 is a semiconductor having, for example, a MOSFET (abbreviation of Metal-Oxide-Semiconductor Field-Effect Transistor) or IGBT (abbreviation of Insulated Gate Bipolar Transistor) via a bonding material 13 on one surface 11a. A chip 14 is mounted.

  The bonding material 13 is an arbitrary bonding material such as solder or a die bonding material, and thermally connects the semiconductor chip 14 and the die pad 11.

  As shown in FIG. 2, the lead 12 is partially covered with the mold resin 16, and is constituted by an inner lead 121 covered with the mold resin 16 and an outer lead 122 that is a remaining part exposed from the mold resin 16. Has been.

  The inner lead 121 is electrically connected to the semiconductor chip 14 via the wire 15 by wire bonding of a wire 15 made of a metal material such as Al, for example. The inner lead 121 is arranged on a different plane from the die pad 11 as a result of the above-described extrusion processing of the lead frame 10.

  As shown in FIG. 2, the outer lead 122 is extended to extend in one direction while being bent in one direction in the normal direction Y <b> 1 with respect to the one surface 11 a of the die pad 11. Specifically, out of the normal direction Y1, the direction from the one surface 11a to the other surface 11b of the die pad 11 is the upward direction, the opposite direction of the upward direction is the downward direction, and the outer lead 122 is bent downward. It is a shape. As a result, the outer lead 122 protrudes from the mold resin 16, is bent downward, and has a shape extending downward.

  One end 122a of the outer lead 122 opposite to the mold resin 16 is used to be mounted on a wiring board or the like by solder bonding or the like. As shown in FIG. 2, the outer lead 122 is preferably extended to at least the bottom surface 16a, with the surface of the mold resin 16 facing the one surface 11a of the die pad 11 with the semiconductor chip 14 therebetween as the bottom surface 16a. This is because when one end 122a of the outer lead 122 is joined to another member by soldering, the reliability of the joined portion can be improved. Details of this will be described later.

  In the present embodiment, the mold resin 16 is a sealing member that covers a portion of the die pad 11 different from the other surface 11b, a part of the lead 12, the bonding material 13, the semiconductor chip 14, and the wire 15, as shown in FIG. For example, it is made of a resin material such as an epoxy resin.

  As shown in FIG. 2, the mold resin 16 is an asymmetric body in the normal direction Y1 when the surface of the inner lead 121 is used as a reference position. Specifically, a portion of the mold resin 16 in the upward direction from the inner lead 121 is a mold upper portion 161, and a portion of the mold resin 16 in the downward direction from the inner lead 121 is a mold lower portion 162. At this time, the thickness of the mold lower part 162 in the normal direction Y1 is made thicker than the thickness of the mold upper part 161 in the normal direction Y1.

  In other words, unlike the conventional semiconductor device in which the mold resin is a symmetric body in the normal direction Y1 when the inner lead is the reference position, in the semiconductor device of this embodiment, the mold resin 16 is an asymmetric body in the normal direction Y1. It is said that.

  This is to reduce the warpage of the entire mold resin 16 due to heat generation when the semiconductor chip 14 is driven and to secure the length of the outer lead 122. This will be described in detail later.

  In the semiconductor device of this embodiment, the die pad 11 and the semiconductor chip 14 mounted on the die pad 11 are arranged on the mold upper part 161 side, and the other surface 11b of the die pad 11 is exposed from the mold resin 16. As a result, a heat radiating type semiconductor device is formed in which heat generated from the semiconductor chip 14 is radiated from the other surface 11b of the die pad 11, that is, from the back surface.

  The above is the basic configuration of the semiconductor device of this embodiment. Next, a method for manufacturing the semiconductor device of this embodiment will be described.

  One metal plate made of Cu or the like is subjected to press punching to form a region to be the die pad 11 and the lead 12, and then the region to be the die pad 11 is extruded by extrusion processing, thereby producing the lead frame 10. A lead frame 10 in which the die pad 11 is already arranged on a different plane from the lead 12 may be prepared and used. Further, noble metal plating or the like may be applied to the surface of the lead frame 10 as necessary.

  Next, the semiconductor chip 14 manufactured by an arbitrary manufacturing method is prepared, and the semiconductor chip 14 is mounted on the one surface 11a of the die pad 11 via the bonding material 13 made of an arbitrary die bonding material, for example. Then, the lead 12 and the semiconductor chip 14 are electrically connected via a wire 15 made of Al or the like by wire bonding.

  Subsequently, a mold composed of an upper mold and a lower mold (not shown) is prepared, the lead frame 10 on which the semiconductor chip 14 is mounted and wire-bonded is set in the lower mold, and the upper mold and the lower mold are molded. Match. Then, a resin material such as an epoxy resin that becomes the mold resin 16 is poured into a mold, and the resin material is heated and cured.

  In this case, for example, the upper mold cavity is recessed deeper than the lower mold cavity in which the lead frame 10 is set, and this mold has a resin thickness opposite to the mounting side of the semiconductor chip 14. The specification is larger than the resin thickness on the mounting side of the semiconductor chip 14.

  After forming the mold resin 16, the workpiece is taken out of the mold, and unnecessary portions are cut and removed by press punching, whereby the semiconductor device of this embodiment can be manufactured.

  Next, the effect of suppressing solder cracks after mounting the semiconductor device of this embodiment on another member by soldering will be described with reference to FIGS.

  First, a case where a conventional semiconductor device is mounted on another member by soldering will be described with reference to FIG.

  As shown in FIG. 3A, a conventional semiconductor device includes a lead frame 110 including a die pad 111 having one surface 111a and another surface 111b and a lead 112, a semiconductor chip 114, a wire 115, and a part of them. And a molding resin 116 to be covered.

  In such a configuration, the die pad 111 is disposed on a different plane from the inner leads 1121 covered with the mold resin 116 of the leads 112. The semiconductor chip 114 is mounted on the one surface 111a of the die pad 111 via the bonding material 113, and is electrically connected to the inner lead 1121 that is a portion of the lead 112 covered with the mold resin 116 via the wire 115. Yes. Outer leads 1122, which are portions of the leads 112 exposed from the mold resin 116, are bent to the opposite side of the die pad 111.

  As shown in FIG. 3A, the mold resin 116 is symmetric in the normal direction Y2 when the inner lead 1121 is used as a reference in the normal direction Y2 with respect to the one surface 111a of the die pad 111. Specifically, a direction from one surface 111a to the other surface 111b in the normal direction Y2 is defined as an upward direction, and a direction opposite to the upward direction is defined as a downward direction. At this time, the portion of the mold resin 116 above the inner lead 1121 has the same thickness in the normal direction Y2 as the portion of the mold resin 116 below the inner lead 1121.

  In FIG. 3A, a thinned conventional semiconductor device having the above configuration is mounted on the surface 20a of the substrate 20, and one end 1122a of the outer lead 1122 opposite to the mold resin 116 is formed on the surface 20a. The state where it was soldered to the prepared pad 21 is shown.

  Here, “thinning” means that the thickness of the mold resin constituting the semiconductor device is in the range of 1 mm to 2 mm. In addition, the conventional semiconductor device has a configuration in which the thickness of the molding resin as a component is larger than 2 mm, and the semiconductor device of this embodiment is thinner than the conventional semiconductor device as a whole.

  The substrate 20 is made of, for example, an insulating material such as glass epoxy resin, and is formed with a pad 21 made of a metal material such as Al.

  Here, as a result of the study by the present inventors, when the thinned semiconductor device having such a conventional semiconductor device structure is mounted on another member by soldering, as shown in FIG. It has been found that solder crack defects occur.

  Specifically, as shown in FIG. 3A, the distance in the normal direction Y2 between the upper portion of the surface of the outer lead 1122 and one end 1122a of the outer lead 1122 is defined as the height H1 of the outer lead 1122. To do.

  At this time, the height H1 of the outer lead 1122 decreases as the thickness of the mold resin 116 in the normal direction Y2 decreases, that is, as the semiconductor device decreases. Further, as the semiconductor device is made thinner, the influence of the warp of the semiconductor device due to heat generation of the semiconductor chip and the force due to the thermal stress caused by the difference in the linear expansion coefficient between the mold resin 116 and the lead 112 on the outer lead 1122 increases.

  More specifically, as indicated by the white arrow in FIG. 3B, heat generated between the mold resin 116 and the lead 112 due to environmental changes such as warpage of the semiconductor device due to heat generation of the semiconductor chip 114 and a cooling cycle. A force F 1 resulting from stress or the like acts on the outer lead 1122. At this time, with the thinning of the semiconductor device, the height H1 of the outer lead 1122 is smaller than that in the semiconductor device having a structure that is not thinned. In other words, the length of the outer lead 1122 is shorter than that of the conventional semiconductor device.

  When a conventional semiconductor device simply thinned is joined to the pad 21 provided on the substrate 20 via the solder 30, a force F1 acts on the outer lead 1122, as shown in FIG. It will be. However, as shown in FIG. 3 (b), when the length of the outer lead 1122 is shortened, the action of relaxing the force F1 is reduced, so that the solder crack between the solder 30 and the pad 21 due to the influence of the force F1. 301 can occur.

  Such a problem is expected to be a problem particularly when applied to a field where the requirement for reliability is severe such as in-vehicle use.

  Thus, as a result of intensive studies, the present inventors have invented a semiconductor device that can reduce the influence on the outer lead 122 due to thermal stress caused by warpage or environmental change due to heat generation of the semiconductor chip 14 while being thinned. It was. As an example, a case where the semiconductor device of this embodiment is mounted on another member by soldering will be described with reference to FIGS.

  When the semiconductor device of this embodiment is mounted on the substrate 20 having the pad 21 on the surface 20a, the outer leads 122 are caused by warpage of the semiconductor device due to heat generation of the semiconductor chip 14 or environmental changes as shown in FIG. The force F2 due to the thermal stress or the like acting will act. At this time, the force F2 acting on the outer lead 122 is smaller than the force F1 acting on the outer lead 1122 although the conventional semiconductor device is simply made thinner.

  Specifically, the distance in the normal direction Y1 between the upper portion of the surface of the outer lead 122 and the one end 122a of the outer lead 122 is defined as the height H2 of the outer lead 122. In the semiconductor device of the present embodiment, as described above, the outer lead 122 is bent and extended to the mold lower portion 162 side that is thicker in the normal direction Y1 than the mold upper portion 161.

  Therefore, even if the thickness of the mold resin in the normal direction Y1 is the same, the height H2 of the outer lead 122 is larger than the height H1 of the outer lead 1122 in a conventional thinned semiconductor device. . In other words, the length of the outer lead 122 is longer than the length of the outer lead 1122. In other words, the outer lead 122 is configured to have a greater effect than the outer lead 1122 in reducing the force caused by the warp of the semiconductor device.

  Further, in the semiconductor device of this embodiment, since the thickness of the portion of the mold resin 16 in the lower direction than the semiconductor chip is thicker than that of the conventional semiconductor device, the warpage of the entire semiconductor device is larger than that of the conventional semiconductor device. It is set as the structure which becomes small.

  Furthermore, in the semiconductor device of this embodiment, since the mold lower part 162 is thicker than the mold upper part 161, when the mold lower part 162 is mounted on another member such as the substrate 20, the semiconductor device of this embodiment is mounted at the time of mounting. It plays the role of receiving the load applied to. Therefore, the outer lead 122 is less likely to be plastically deformed when mounted on another member, and an effect that the area of the outer lead 122 used for solder bonding can be stably secured is also expected.

  As described above, the force F2 acting on the outer lead 122 is smaller than the force F1 by setting the mold resin 16 so that the entire semiconductor device is hardly warped while H2> H1. As a result, as shown in FIG. 5, a semiconductor device capable of suppressing the occurrence of solder cracks between the solder 30 and the pad 21 is obtained.

  Next, an effect of stress reduction in a portion where the semiconductor chip 14 and the die pad 11 are joined (hereinafter simply referred to as “joint portion”) in the semiconductor device of the present embodiment will be described with reference to FIG.

  FIG. 6 shows the result of calculation of the stress amplitude applied to the joint, by comparing the results obtained by simply thinning the conventional semiconductor device and the semiconductor device of the present embodiment. .

  Note that “conventional” on the horizontal axis in FIG. 6 refers to a thinned conventional semiconductor device, and “first embodiment” refers to the semiconductor device of the present embodiment. In the “stress amplitude at the joint” on the vertical axis in FIG. 6, the stress amplitude obtained from the simulation result of the conventional semiconductor device is 100 (reference). Moreover, in simulation, it implemented by 2D analysis and performed the stress analysis in a cross-sectional state as shown in FIG. Then, the conventional semiconductor device simply thinned and the semiconductor device of this embodiment have an outer dimension of the mold resin of 20 mm (width) × 1.4 mmt (height) and an outer dimension of the die pad of 13 mm (width). X0.15 mmt (height). Further, the outer dimension of the semiconductor chip was set to 9 mm (width), and the area of the bonding portion was the same as the outer dimension of the semiconductor chip. And the stress amplitude concerning the junction part of said each semiconductor device was computed on the conditions of -65 degreeC.

  Further, the simulation of FIG. 6 was performed by using commonly used simulation software for stress calculation (for example, ANSYS AIM manufactured by Ansys Japan). It shows that the smaller the stress amplitude obtained by this simulation, the smaller the stress applied to the joint and the higher the reliability of the joint. From the experience, it is known from experience that the magnitude of the magnitude of the stress amplitude obtained by this simulation is almost the same as the reliability of the junction in an actual semiconductor device.

  As shown in FIG. 6, when the stress amplitude applied to the junction in the conventional semiconductor device simply thinned is 100, the stress amplitude applied to the junction in the semiconductor device of this embodiment is 88. In other words, in the semiconductor device of this embodiment, the stress amplitude applied to the joint is reduced by 12% compared to the conventional semiconductor device that is simply made thinner, and the joint reliability at the joint is higher than that of the conventional device. It becomes composition.

  According to the present embodiment, the semiconductor device can be reduced in thickness while suppressing warpage of the entire semiconductor device due to heat generation of the semiconductor chip, and can be mitigated even if force due to warpage or thermal stress acts on the outer lead. . For this reason, when mounted on another member by soldering, it is possible to suppress the occurrence of cracks in the solder, resulting in a semiconductor device with higher reliability of solder bonding to the other member than a conventional semiconductor device. Further, the stress applied to the joint between the die pad and the semiconductor chip can be reduced as compared with the conventional semiconductor device.

(Second Embodiment)
A semiconductor device according to the second embodiment will be described with reference to FIG. The package unit 100 shown in FIG. 7 is a part corresponding to the semiconductor device of the first embodiment, which is configured by the lead frame 10, the bonding material 13, the semiconductor chip 14, the wire 15, and the mold resin 16.

  In the semiconductor device of this embodiment, as shown in FIG. 7, a package unit 100 is mounted on a substrate 20 including a pad 21, and heat dissipation for dissipating heat generated from the semiconductor chip 14 on the other surface 11 b of the die pad 11. A gel 40 is arranged. The semiconductor device of this embodiment is different from the first embodiment in that it is configured to be connected to the heat dissipation member 50 via the heat dissipation gel 40. In the present embodiment, this difference will be mainly described.

  The heat dissipating gel 40 is used to increase the efficiency of dissipating heat generated from the semiconductor chip 14, and is made of, for example, silicon gel. The heat dissipating gel 40 is preferably made of a material having a thermal conductivity of 3 W / m · K or more from the viewpoint of improving heat dissipation efficiency. The heat dissipation gel 40 may be formed so as to be in contact with a part of the other surface 11b from the viewpoint of improving the efficiency of heat dissipation, but is preferably formed so as to cover the entire other surface 11b.

  The heat radiating gel 40 is formed by applying a material that becomes the heat radiating gel 40 on the other surface 11b of the die pad 11 of the package unit 100 mounted on the substrate 20 with, for example, a dispenser, and then applying the heat radiating member 50 onto the applied material. It is formed by placing.

  The heat dissipating member 50 is a member that is thermally connected to the semiconductor chip 14 via the heat dissipating gel 40 and is used for improving the heat dissipating efficiency, and is made of a metal material having high thermal conductivity such as Al.

  As shown in FIG. 7, the heat dissipating member 50 has a rectangular plate shape, for example, in cross-sectional view. However, it is only necessary to improve heat dissipating efficiency. The surface opposite to the gel 40 may have a concavo-convex shape, a groove, or the like. The heat dissipation member 50 may be a housing that covers the package unit 100 or other members such as the package unit 100 and the substrate 20. As described above, the heat radiating member 50 has an arbitrary shape as necessary. However, from the viewpoint of improving the efficiency of heat dissipation, it is preferable that the area and volume are increased, that is, the heat capacity is large.

  According to this embodiment, the heat generated from the semiconductor chip 14 diffuses from the other surface 11b of the die pad 11 to the heat radiating member 50 having a large heat capacity through the heat radiating gel 40, and the heat radiation efficiency of the rear heat radiation type semiconductor device is high. Become.

  Similarly to the first embodiment, the mold lower portion 162 of the package unit 100 is thicker than the mold upper portion 161 and the length of the outer lead 122 is increased. Therefore, the semiconductor device according to the present embodiment is a semiconductor device with high bonding reliability in the solder bonding of the outer leads 122 while the package unit 100 is thinned.

(Other embodiments)
The semiconductor device described in each of the above embodiments is an example of the semiconductor device of the present invention, and is not limited to each of the above embodiments, but within the scope described in the claims. Can be changed as appropriate.

  (1) For example, in the semiconductor device of each of the above embodiments, as shown in FIG. 8, the length of the outer lead 122 used for joining to the one end 122 a side, that is, the pad 21 on the substrate 20 is increased. The structure may be different. As a result, the area of the portion where the outer lead 122 is joined to the pad 21 via the solder 30 is increased, and a crack is generated in the solder 30 even if a force due to warpage or thermal stress of the semiconductor device acts on the one end 122a. It becomes a joining structure which can suppress this.

  (2) The semiconductor device of each of the above embodiments is an example in which the surface of the mold resin 16 opposite to the bottom surface 16a is the top surface and the top surface and the other surface 11b of the die pad 11 are arranged on the same plane. explained. However, in the case where the other surface 11b of the die pad 11 is exposed from the mold resin 16, the other surface 11b only needs to be exposed from the mold resin 16, and the upper surface is disposed above the other surface 11b. It may be a structure.

  For example, as shown in FIG. 9, a structure in which a recess 16 c reaching the other surface 11 b is formed on the upper surface 16 b of the mold resin 16 in a cross-sectional view so that a part or all of the other surface 11 b is exposed from the mold resin 16. It may be a semiconductor device. In addition, when arrange | positioning the thermal radiation gel 40 on the other surface 11b, the thermal radiation gel 40 may be provided so that it may be settled in the recessed part 16c, and may be provided so that it may protrude from the upper surface 16b upward.

  (3) In the semiconductor device of each of the embodiments described above, the example in which the die pad 11 is arranged above the inner lead 121 has been described. However, since the backside heat dissipation type structure may be used, the die pad 11 may be arranged below the inner lead 121.

  In this case, as shown in FIG. 10, while the die pad 11 is disposed below the inner lead 121, the recess 16c formed on the upper surface 16b of the mold resin 16 is formed, and the other surface 11b is the mold resin in the recess 16c. 16 is exposed from the structure. Even in the case of such a structure, the semiconductor device can be thinned, radiated, and has high bonding reliability.

  (4) The semiconductor device according to each of the above embodiments has been described with respect to the example in which the other surface 11b of the die pad 11 is exposed from the mold resin 16 and has a so-called exposed package structure. However, the semiconductor device of the present invention is not limited to the structure of the exposed package, and may have a so-called full mold structure in which the other surface 11b of the die pad 11 is covered with the mold resin 16 as shown in FIG. The semiconductor device having a full mold structure is a backside heat radiation type semiconductor device while ensuring insulation between the die pad 11 and members other than the semiconductor device. At this time, the heat radiating gel 40 may be disposed on the other surface 11 b of the die pad 11, or may be thermally connected to other members such as the heat radiating member 50 via the heat radiating gel 40.

  (5) The semiconductor device of each of the above embodiments may be configured such that the thickness of the lead frame 10, particularly the thickness of the outer lead 122, is thinner than the thickness of the outer lead 1122 in the conventional semiconductor device. As a result, the thinned outer lead 122 is bent, so that the stress applied to the solder 30 joined to the outer lead 122 is relieved, and a semiconductor device having high joining reliability in solder joining is obtained.

  (6) The semiconductor device of each of the above embodiments may be configured such that the mold resin 16 contains a filler such as alumina or silica in the resin. When the mold resin 16 includes a filler, the linear expansion coefficient of the entire mold resin 16 is the same as or close to the linear expansion coefficient of the substrate 20 or other member on which the semiconductor device of each of the above embodiments is mounted. It is preferable that As a result, the difference between the thermal expansion and contraction of the mold resin 16 in the cold cycle and the thermal expansion and contraction of the substrate 20 and other members on which the semiconductor device is mounted via the solder 30 is reduced, and the stress applied to the solder 30 is reduced. Thus, a semiconductor device with high bonding reliability in solder bonding is obtained.

11 Die Pad 12 Lead 121 Inner Lead 122 Outer Lead 13 Bonding Material 14 Semiconductor Chip 16 Mold Resin 30 Solder 40 Heat Dissipation Gel 50 Heat Dissipation Member

Claims (6)

A lead frame (10) comprising a die pad (11) having one surface (11a) and the other surface (11b) in a front-back relationship, and a lead (12);
A semiconductor chip (14) mounted on the one surface;
A wire (15) for electrically connecting a part of the lead and the semiconductor chip;
A mold resin (16) that covers the one surface of the die pad, the semiconductor chip, the wire, and a part of the lead;
The die pad is arranged on a plane different from the plane formed by the inner lead (121) which is a portion covered with the mold resin in the lead,
Of the normal direction to the one surface, the direction from the one surface to the other surface is the upward direction, the direction from the other surface to the one surface is the downward direction, the mold resin in the lower direction than the inner lead The thickness in the normal direction of the mold lower portion (162) which is a portion is made thicker than the thickness in the normal direction of the mold upper portion (161) which is the portion in the upper direction than the inner lead in the mold resin. And
The semiconductor device, wherein the outer lead is bent to the mold lower side.   2. The semiconductor device according to claim 1, wherein a surface of the surface of the mold resin that faces the one surface across the semiconductor chip is a bottom surface (16 a), and the outer lead extends at least to the bottom surface.   The semiconductor device according to claim 1, wherein a part or all of the other surface is exposed from the mold resin.   The semiconductor device according to claim 3, wherein a heat radiating gel (40) for diffusing heat generated from the semiconductor chip is disposed on the other surface. A substrate (20) having a surface (20a);
A heat dissipating member (50),
The outer lead is connected to the surface via solder (30),
The semiconductor device according to claim 4, wherein the heat dissipation gel is connected to the heat dissipation member and thermally connects the semiconductor chip and the heat dissipation member.   The semiconductor device according to claim 1, wherein a thickness of the mold resin in the normal direction is in a range of 1 mm to 2 mm.

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