JP2018018952A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2018018952A
JP2018018952A JP2016148056A JP2016148056A JP2018018952A JP 2018018952 A JP2018018952 A JP 2018018952A JP 2016148056 A JP2016148056 A JP 2016148056A JP 2016148056 A JP2016148056 A JP 2016148056A JP 2018018952 A JP2018018952 A JP 2018018952A
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semiconductor device
thick
chip
power chip
thin
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祥吾 柴田
Shogo Shibata
祥吾 柴田
中川　信也
Shinya Nakagawa
信也 中川
公輔 山口
Kosuke Yamaguchi
公輔 山口
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2016148056A priority Critical patent/JP2018018952A/en
Priority to DE102017212641.8A priority patent/DE102017212641A1/en
Priority to CN201710631475.4A priority patent/CN107665875A/en
Publication of JP2018018952A publication Critical patent/JP2018018952A/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing thermal interferences, improving a heat radiation property, and suppressing increase in product cost.SOLUTION: A semiconductor device 1 comprises: power chips 8 and 9; an IC chip 10 that drives the power chips 8 and 9; and a lead frame 2 that has thin parts 3 and 3a and a thick part 4 thicker than the thin parts 3 and 3a. The power chips 8 and 9 are mounted on the thick part 4. The IC chip 10 is mounted on the thin part 3a.SELECTED DRAWING: Figure 2

Description

本発明は、インバータ等の電力変換装置を構成する電力用半導体装置に関し、特に部分的に異なる厚みを有するリードフレームの構成に関するものである。   The present invention relates to a power semiconductor device that constitutes a power conversion device such as an inverter, and more particularly to a configuration of a lead frame having partially different thicknesses.

電力用半導体装置であるトランスファーモールド構造パッケージのＤＩＰＩＰＭ（Dual Inline Package Intelligent Power Module）には、高い放熱性と絶縁性が要求される。放熱性を向上させるためには、接合材を介して接合されたチップ直下のリードフレームの厚みを増すことにより、熱伝導性が低い絶縁シートに熱が入力される前段階で熱広がりを促進させることが有効である。そのため、従来は放熱性が求められる品種では、リードフレーム全体の厚みを均一に厚くした設計が行われてきた。   DIPIPM (Dual Inline Package Intelligent Power Module), which is a transfer mold structure package, which is a power semiconductor device, requires high heat dissipation and insulation. In order to improve heat dissipation, by increasing the thickness of the lead frame directly under the chip bonded via the bonding material, the heat spread is promoted before heat is input to the insulating sheet having low thermal conductivity. It is effective. For this reason, conventionally, a variety of products that require heat dissipation have been designed with a uniform thickness of the entire lead frame.

また、例えば特許文献１では、パワーチップのみが搭載されるモジュールにおいて、部分的に異なる厚みを有するリードフレームを備えた構成が開示されており、チップ搭載部は全て厚肉部となっている。   Further, for example, Patent Document 1 discloses a configuration in which a module on which only a power chip is mounted is provided with a lead frame having a partially different thickness, and the chip mounting portions are all thick portions.

特開２０１５−９５４８６号公報Japanese Patent Laying-Open No. 2015-95486

しかしながら、リードフレーム全体の厚みを均一に厚くした場合には材料コストが増加する。さらに、リードフレームの打ち抜き制約条件によるパターンレイアウトの拡大に起因して、パッケージサイズが増大する。以上のことから、製品コストが増加するという問題があった。   However, the material cost increases when the thickness of the entire lead frame is increased uniformly. Furthermore, the package size increases due to the expansion of the pattern layout due to the lead frame punching constraint. From the above, there is a problem that the product cost increases.

また、特許文献１に記載の技術を、パワーチップおよび、パワーチップを駆動するＩＣ（Integrated Circuit）チップが搭載されるモジュールに採用した場合、パワーチップだけでなく温度制限の低いＩＣチップについてもチップ搭載部としての厚肉部に搭載される。この場合、材料コストの増加を抑制するために厚肉部が形成される領域をできるだけ小さくする必要があることから、厚肉部におけるＩＣチップが搭載された箇所とパワーチップが搭載された箇所との距離が近くなり、パワーチップからＩＣチップへの熱干渉が大きくなるという問題があった。   Further, when the technique described in Patent Document 1 is applied to a power chip and a module on which an IC (Integrated Circuit) chip for driving the power chip is mounted, not only the power chip but also an IC chip with a low temperature limit is used. It is mounted on the thick part as the mounting part. In this case, since it is necessary to make the region where the thick portion is formed as small as possible in order to suppress the increase in material cost, the location where the IC chip is mounted and the location where the power chip is mounted in the thick portion There is a problem in that the thermal interference from the power chip to the IC chip increases.

そこで、本発明は、熱干渉を低減し、かつ、放熱性を向上させるとともに、製品コストの増加を抑制できる半導体装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor device that can reduce thermal interference, improve heat dissipation, and suppress an increase in product cost.

本発明に係る半導体装置は、パワーチップと、前記パワーチップを駆動するＩＣチップと、薄肉部と、前記薄肉部の厚みよりも厚い厚肉部とを有するリードフレームとを備え、前記パワーチップは前記厚肉部に搭載され、前記ＩＣチップは前記薄肉部に搭載されたものである。   A semiconductor device according to the present invention includes a power chip, an IC chip that drives the power chip, a thin portion, and a lead frame that is thicker than a thickness of the thin portion, The IC chip is mounted on the thin part, and the IC chip is mounted on the thin part.

本発明によれば、半導体装置は、パワーチップと、パワーチップを駆動するＩＣチップと、薄肉部と、薄肉部の厚みよりも厚い厚肉部とを有するリードフレームとを備え、パワーチップは厚肉部に搭載され、ＩＣチップは薄肉部に搭載された。   According to the present invention, a semiconductor device includes a power chip, an IC chip that drives the power chip, a thin portion, and a lead frame that has a thick portion thicker than the thin portion, and the power chip is thick. It was mounted on the meat part, and the IC chip was mounted on the thin part.

したがって、主な発熱源であるパワーチップに対して、放熱体としてのリードフレームにおけるパワーチップ直下の部分の厚みが増すことにより熱広がりを促進させることができる。これにより、半導体装置の放熱性を向上させることができる。   Therefore, the heat spread can be promoted by increasing the thickness of the portion immediately below the power chip in the lead frame as the heat radiating element with respect to the power chip as the main heat source. Thereby, the heat dissipation of the semiconductor device can be improved.

また、温度制限の低いＩＣチップは薄肉部に搭載されるため、リードフレームにおけるＩＣチップが搭載された箇所とパワーチップが搭載された箇所との距離を離すことができる。これにより、パワーチップからＩＣチップへの熱干渉を低減できる。   Further, since the IC chip having a low temperature limit is mounted on the thin portion, the distance between the position where the IC chip is mounted on the lead frame and the position where the power chip is mounted can be separated. Thereby, thermal interference from the power chip to the IC chip can be reduced.

さらに、リードフレームにおけるパワーチップの搭載箇所のみに厚肉部が設けられるため、厚肉部が形成される領域を小さくすることができる。これにより、材料コストおよびパッケージサイズの増加を抑制できるため、製品コストの増加を抑制できる。   Furthermore, since the thick portion is provided only at the power chip mounting location in the lead frame, the region where the thick portion is formed can be reduced. Thereby, since the increase in material cost and package size can be suppressed, the increase in product cost can be suppressed.

実施の形態１に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment. 実施の形態１に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment. 厚肉部での熱広がりを説明するための図である。It is a figure for demonstrating the heat spread in a thick part. 厚肉部の形成位置を説明するための図である。It is a figure for demonstrating the formation position of a thick part. 実施の形態２に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. 実施の形態３に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment. 実施の形態４に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment. 実施の形態５に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

＜実施の形態１＞
本発明の実施の形態１について、図面を用いて以下に説明する。図１は、実施の形態１に係る半導体装置１の平面図である。図２は、半導体装置１の断面図であり、より具体的には、図１のII-II線断面図である。ここで、図１はタイバーカット工程前を示す図面である。なお、図１の紙面に向かって左右方向をＸ軸方向、上下方向をＹ軸方向として説明する。 <Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor device 1 according to the first embodiment. 2 is a cross-sectional view of the semiconductor device 1, and more specifically, a cross-sectional view taken along the line II-II of FIG. Here, FIG. 1 is a drawing showing a tie bar cutting step. In the following description, the left-right direction is the X-axis direction and the up-down direction is the Y-axis direction toward the paper surface of FIG.

図１と図２に示すように、半導体装置１は、例えばパワーモジュールであり、パワーチップ８，９と、ＩＣチップ１０と、リードフレーム２と、モールド樹脂１５と、絶縁層６と、ヒートシンク７とを備えている。リードフレーム２は、モールド樹脂１５により封止されるインナーリード２ａと、インナーリード２ａと繋がるアウターリード２ｂと、アウターリード２ｂと繋がる外枠部２ｃとを備えている。インナーリード２ａは、薄肉部３，３ａと、薄肉部３，３ａの厚みよりも厚い厚肉部４とを複数ずつ備えている。また、各薄肉部３の一部と各厚肉部４はそれぞれ繋がっている。各薄肉部３ａの一部と各厚肉部４はそれぞれ繋がっている。なお、アウターリード２ｂおよび外枠部２ｃは、薄肉部３，３ａと同じ厚みを有している。   As shown in FIGS. 1 and 2, the semiconductor device 1 is, for example, a power module, and includes power chips 8 and 9, an IC chip 10, a lead frame 2, a mold resin 15, an insulating layer 6, and a heat sink 7. And. The lead frame 2 includes an inner lead 2a sealed with a mold resin 15, an outer lead 2b connected to the inner lead 2a, and an outer frame portion 2c connected to the outer lead 2b. The inner lead 2a includes a plurality of thin portions 3 and 3a and a plurality of thick portions 4 that are thicker than the thin portions 3 and 3a. Moreover, a part of each thin part 3 and each thick part 4 are connected, respectively. A part of each thin part 3a and each thick part 4 are connected. The outer lead 2b and the outer frame portion 2c have the same thickness as the thin portions 3 and 3a.

パワーチップ８，９は、例えばＳｉＣを材料として形成されたＳｉＣチップであり、接合材１６（図３参照）を介して厚肉部４に搭載されている。なお、パワーチップ８，９はＳｉＣチップに限定されることなく、例えばＳｉを材料として形成されたＳｉチップであってもよい。ＩＣチップ１０は、パワーチップ８，９を駆動するための電子部品であり、薄肉部３ａに搭載されている。パワーチップ８はワイヤ１１を介して薄肉部３と電気的に接続されるとともに、ワイヤ１２を介してパワーチップ９と電気的に接続されている。パワーチップ９は、ワイヤ１３を介してＩＣチップ１０と電気的に接続されている。ＩＣチップ１０は、ワイヤ１４を介して薄肉部３ａと電気的に接続されている。   The power chips 8 and 9 are SiC chips formed of, for example, SiC, and are mounted on the thick portion 4 via the bonding material 16 (see FIG. 3). The power chips 8 and 9 are not limited to SiC chips, and may be Si chips formed using Si as a material, for example. The IC chip 10 is an electronic component for driving the power chips 8 and 9, and is mounted on the thin portion 3a. The power chip 8 is electrically connected to the thin portion 3 via the wire 11 and is also electrically connected to the power chip 9 via the wire 12. The power chip 9 is electrically connected to the IC chip 10 via the wire 13. The IC chip 10 is electrically connected to the thin portion 3a via the wire 14.

リードフレーム２の一部であるインナーリード２ａ、パワーチップ８，９、ＩＣチップ１０、絶縁層６、およびヒートシンク７の下面を除く部分は、モールド樹脂１５により封止されている。モールド樹脂１５としては、例えばエポキシ樹脂が用いられる。アウターリード２ｂおよび外枠部２ｃは、モールド樹脂１５から露出しており、アウターリード２ｂは、モールド樹脂１５から第１の方向に突出する端子５，５ａを構成している。外枠部２ｃは、タイバーカット工程にてアウターリード２ｂから切断され除去される。ここで、第１の方向とはＹ軸方向である。   Portions other than the inner leads 2 a, the power chips 8 and 9, the IC chip 10, the insulating layer 6, and the lower surface of the heat sink 7 that are a part of the lead frame 2 are sealed with a mold resin 15. As the mold resin 15, for example, an epoxy resin is used. The outer lead 2b and the outer frame portion 2c are exposed from the mold resin 15, and the outer lead 2b constitutes terminals 5 and 5a that protrude from the mold resin 15 in the first direction. The outer frame portion 2c is cut and removed from the outer lead 2b in a tie bar cutting process. Here, the first direction is the Y-axis direction.

絶縁層６は、厚肉部４の下面に配置されている。ヒートシンク７は、例えば熱伝導性の高い銅などの金属を材料として形成され、絶縁層６の下面に配置されている。   The insulating layer 6 is disposed on the lower surface of the thick part 4. The heat sink 7 is formed of a metal such as copper having high thermal conductivity, for example, and is disposed on the lower surface of the insulating layer 6.

次に、図３を用いて、厚肉部４での熱広がりについて説明する。ここでは、パワーチップ８について説明するが、パワーチップ９の場合もこれと同様である。図３は、厚肉部４での熱広がりを説明するための図である。   Next, the heat spread in the thick part 4 will be described with reference to FIG. Although the power chip 8 will be described here, the same applies to the power chip 9. FIG. 3 is a diagram for explaining the heat spread in the thick portion 4.

図３に示すように、パワーチップ８は厚肉部４に搭載されているため、主な発熱源であるパワーチップ８に対して、放熱体としてのリードフレーム２におけるパワーチップ８直下の部分の厚みが増すことにより熱広がりを促進させることができる。これにより、放熱性の向上と熱抵抗の低減が可能となる。なお、図３における点線Ｃは熱広がりを示している。   As shown in FIG. 3, since the power chip 8 is mounted on the thick part 4, the power chip 8 which is a main heat source has a portion directly below the power chip 8 in the lead frame 2 as a radiator. Heat spread can be promoted by increasing the thickness. As a result, it is possible to improve heat dissipation and reduce thermal resistance. Note that a dotted line C in FIG. 3 indicates heat spread.

また、チップ端−搭載フレーム端距離、すなわち、パワーチップ８の端と、当該パワーチップ８の当該端側に対応する厚肉部４の端との距離をａとし、フレーム厚み、すなわち、厚肉部４の厚みをｔとすると、厚肉部４の厚みは、パワーチップ８の４辺のうち少なくとも１辺でｔ≧ａを満たすように設定されている。これにより、厚肉部４の端まで熱が広がることで、更なる放熱性の向上が可能となる。ここで、当該パワーチップ８の当該端側に対応する厚肉部４の端とは、パワーチップ８および厚肉部４において、図３の紙面に向かって同じ側の端のことである。   Further, the distance between the chip end and the mounting frame end, that is, the distance between the end of the power chip 8 and the end of the thick portion 4 corresponding to the end of the power chip 8 is a, and the frame thickness, When the thickness of the portion 4 is t, the thickness of the thick portion 4 is set so that t ≧ a is satisfied on at least one side of the four sides of the power chip 8. Thereby, since heat spreads to the end of the thick part 4, further improvement in heat dissipation becomes possible. Here, the end of the thick part 4 corresponding to the end side of the power chip 8 is an end on the same side of the power chip 8 and the thick part 4 toward the paper surface of FIG. 3.

次に、図４を用いて、厚肉部４が形成される位置について説明する。図４は、厚肉部４の形成位置を説明するための図である。   Next, the position where the thick part 4 is formed will be described with reference to FIG. FIG. 4 is a view for explaining the formation position of the thick portion 4.

図４に示すように、各厚肉部４は、コイル材を使用した順送型の打ち抜き加工により形成されることを考慮して、第１の方向に直交する第２の方向に沿って一直線上に設けられている。ここで、第１の方向とはＹ軸方向であり、第２の方向とはＸ軸方向である。   As shown in FIG. 4, each thick portion 4 is straight along a second direction orthogonal to the first direction in consideration of being formed by a progressive punching process using a coil material. It is provided on the line. Here, the first direction is the Y-axis direction, and the second direction is the X-axis direction.

以下、詳細に説明する。平板状のコイル材がＸ軸方向に沿って順送りされて順番に打ち抜き加工が行われることで、部分的に異なる厚みを有するリードフレーム２、すなわち、複数の薄肉部３，３ａと複数の厚肉部４とを有するインナーリード２ａと、アウターリード２ｂと、外枠部２ｃとを有するリードフレーム２が製造される。各薄肉部３，３ａと、各薄肉部３，３ａに繋がる各厚肉部４は、Ｘ軸方向に間隔をあけて形成される。より具体的には、各厚肉部４は、Ｘ軸方向に沿って一直線上に形成された２つの点線で囲まれた領域に、Ｘ軸方向に互いに間隔をあけて設けられている。また、各薄肉部３は、２つの点線で囲まれた領域の外側の領域、換言すると２つの点線で囲まれた領域に対して−Ｙ方向に隣接する領域に、Ｘ軸方向に互いに間隔をあけて設けられている。各薄肉部３ａは、２つの点線で囲まれた領域の外側の領域、換言すると２つの点線で囲まれた領域に対して＋Ｙ方向に隣接する領域に、Ｘ軸方向に互いに間隔をあけて設けられている。また、アウターリード２ｂは、２つの点線で囲まれた領域の外側の領域、換言すると２つの点線で囲まれた領域に対してＹ軸方向に隣接する領域に、Ｘ軸方向に互いに間隔をあけて設けられている。ここで、＋Ｙ方向とは図４の紙面に向かって上方向、−Ｙ方向とは図４の紙面に向かって下方向である。   Details will be described below. A lead frame 2 having partially different thicknesses, that is, a plurality of thin portions 3 and 3a and a plurality of thick walls, are obtained by sequentially feeding a flat coil material along the X-axis direction and performing punching processing in order. The lead frame 2 having the inner lead 2a having the portion 4, the outer lead 2b, and the outer frame portion 2c is manufactured. Each thin part 3 and 3a and each thick part 4 connected to each thin part 3 and 3a are formed at intervals in the X-axis direction. More specifically, each thick portion 4 is provided in the region surrounded by two dotted lines formed in a straight line along the X-axis direction and spaced from each other in the X-axis direction. In addition, each thin portion 3 is spaced from each other in the X-axis direction in a region outside the region surrounded by two dotted lines, in other words, in a region adjacent to the −Y direction with respect to the region surrounded by two dotted lines. Opened. Each thin portion 3a is provided in a region outside the region surrounded by two dotted lines, in other words, in a region adjacent to the region surrounded by two dotted lines in the + Y direction and spaced from each other in the X-axis direction. It has been. The outer leads 2b are spaced from each other in the X-axis direction in a region outside the region surrounded by two dotted lines, in other words, in a region adjacent to the Y-axis direction with respect to the region surrounded by two dotted lines. Is provided. Here, the + Y direction is an upward direction toward the paper surface of FIG. 4, and the −Y direction is a downward direction toward the paper surface of FIG.

以上のように、実施の形態１に係る半導体装置１は、パワーチップ８，９と、パワーチップ８，９を駆動するＩＣチップ１０と、薄肉部３，３ａと、薄肉部３，３ａの厚みよりも厚い厚肉部４とを有するリードフレーム２とを備え、パワーチップ８，９は厚肉部４に搭載され、ＩＣチップ１０は薄肉部３ａに搭載された。   As described above, the semiconductor device 1 according to the first embodiment includes the power chips 8, 9, the IC chip 10 that drives the power chips 8, 9, the thin portions 3, 3a, and the thicknesses of the thin portions 3, 3a. The power chip 8 and 9 is mounted on the thick portion 4 and the IC chip 10 is mounted on the thin portion 3a.

したがって、主な発熱源であるパワーチップ８，９に対して、放熱体としてのリードフレーム２におけるパワーチップ８，９直下の部分の厚みが増すことにより熱広がりを促進させることができる。これにより、半導体装置１の放熱性を向上させることができる。   Therefore, the heat spread can be promoted by increasing the thickness of the portion immediately below the power chips 8 and 9 in the lead frame 2 as a heat radiating body with respect to the power chips 8 and 9 which are main heat sources. Thereby, the heat dissipation of the semiconductor device 1 can be improved.

また、温度制限の低いＩＣチップ１０は薄肉部３ａに搭載されるため、リードフレーム２におけるＩＣチップ１０が搭載された箇所とパワーチップ８，９が搭載された箇所との距離を離すことができる。これにより、パワーチップ８，９からＩＣチップ１０への熱干渉を低減できる。   In addition, since the IC chip 10 having a low temperature limit is mounted on the thin portion 3a, the distance between the position where the IC chip 10 is mounted on the lead frame 2 and the position where the power chips 8, 9 are mounted can be separated. . Thereby, thermal interference from the power chips 8 and 9 to the IC chip 10 can be reduced.

さらに、リードフレーム２におけるパワーチップ８，９の搭載箇所のみに厚肉部４が設けられるため、厚肉部４が形成される領域を小さくすることができる。これにより、材料コストおよびパッケージサイズの増加を抑制できるため、製品コストの増加を抑制できる。   Furthermore, since the thick part 4 is provided only in the place where the power chips 8 and 9 are mounted in the lead frame 2, the region where the thick part 4 is formed can be reduced. Thereby, since the increase in material cost and package size can be suppressed, the increase in product cost can be suppressed.

パワーチップ８，９の端と、当該パワーチップ８，９の当該端側に対応する厚肉部４の端との距離をａとし、厚肉部４の厚みをｔとすると、パワーチップ８，９の４辺のうち少なくとも１辺でｔ≧ａを満たす。したがって、厚肉部４の端まで熱が広がることで、更なる放熱性の向上が可能となる。   When the distance between the end of the power chip 8, 9 and the end of the thick part 4 corresponding to the end of the power chip 8, 9 is a and the thickness of the thick part 4 is t, the power chip 8, At least one of the four sides of 9 satisfies t ≧ a. Therefore, the heat spreads to the end of the thick portion 4, so that the heat dissipation can be further improved.

厚肉部４は複数であり、半導体装置１は、リードフレーム２の一部、パワーチップ８，９およびＩＣチップ１０を封止するモールド樹脂１５をさらに備え、リードフレーム２は、モールド樹脂１５からＹ軸方向に突出する端子５，５ａをさらに有し、各厚肉部４は、Ｙ軸方向に直交するＸ軸方向に沿って一直線上に設けられた。したがって、リードフレーム２の製造工程において、コイル材を使用した順送型の打ち抜き加工を採用することができるため、製造効率の向上を図ることができる。また、絶縁層６は、図４の点線で囲まれた領域で示される矩形状に形成されるため、絶縁層６の形状が簡単になり、絶縁層６の面積縮小が可能となる。   The semiconductor device 1 further includes a mold resin 15 that seals a part of the lead frame 2, the power chips 8 and 9, and the IC chip 10, and the lead frame 2 is formed from the mold resin 15. It further has terminals 5 and 5a projecting in the Y-axis direction, and each thick portion 4 is provided on a straight line along the X-axis direction orthogonal to the Y-axis direction. Accordingly, in the manufacturing process of the lead frame 2, a progressive die-cutting process using a coil material can be employed, and thus the manufacturing efficiency can be improved. Further, since the insulating layer 6 is formed in a rectangular shape indicated by a region surrounded by a dotted line in FIG. 4, the shape of the insulating layer 6 is simplified, and the area of the insulating layer 6 can be reduced.

パワーチップ８，９はＳｉＣを材料として形成されたため熱抵抗が増加するものの、厚肉部４を設けたことにより放熱性が向上するため、熱抵抗の増加分を吸収することができる。   Since the power chips 8 and 9 are made of SiC as a material, the thermal resistance is increased. However, since the heat dissipation is improved by providing the thick portion 4, the increased thermal resistance can be absorbed.

なお、厚肉部４にめっきが施されていてもよい。この場合、パワーチップ８，９直下の厚肉部４と接合材１６（図３参照）との界面の接触熱抵抗を低減させることができる。これにより、熱抵抗の悪化を抑制することが可能となる。   Note that the thick portion 4 may be plated. In this case, the contact thermal resistance at the interface between the thick portion 4 immediately below the power chips 8 and 9 and the bonding material 16 (see FIG. 3) can be reduced. Thereby, it becomes possible to suppress deterioration of thermal resistance.

＜実施の形態２＞
次に、実施の形態２に係る半導体装置１Ａについて説明する。図５は、実施の形態２に係る半導体装置１Ａの断面図である。なお、実施の形態２において、実施の形態１で説明したものと同一の構成要素については同一符号を付して説明は省略する。また、図５以降では、モールド樹脂１５の図示を省略している。 <Embodiment 2>
Next, a semiconductor device 1A according to the second embodiment will be described. FIG. 5 is a cross-sectional view of the semiconductor device 1A according to the second embodiment. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 5 and subsequent figures, illustration of the mold resin 15 is omitted.

図５に示すように、実施の形態２では、厚肉部４を下方に沈めた構成を採用している。より具体的には、薄肉部３における厚肉部４との接続部分を下方に折り曲げた状態で固定することで、厚肉部４の上面は、薄肉部３，３ａの上面の高さ位置よりも低い高さ位置に設けられている。   As shown in FIG. 5, in Embodiment 2, the structure which sunk the thick part 4 below is employ | adopted. More specifically, by fixing the connecting portion of the thin portion 3 with the thick portion 4 while being bent downward, the upper surface of the thick portion 4 is higher than the height position of the upper surfaces of the thin portions 3 and 3a. Is also provided at a low height position.

さらに、厚肉部４の沈め寸法と厚肉部４の厚みとの和、すなわち、薄肉部３，３ａの上面の高さ位置と厚肉部４の上面の高さ位置との差と、厚肉部４の厚みとの和をＡとし、絶縁層６の厚みとヒートシンク７の厚みとの和をＢとすると、厚肉部４の沈め寸法および厚肉部４の厚みは、Ａ＞Ｂを満たすように設定されている。   Furthermore, the sum of the sinking dimension of the thick portion 4 and the thickness of the thick portion 4, that is, the difference between the height position of the upper surface of the thin portions 3 and 3a and the height position of the upper surface of the thick portion 4, and the thickness Assuming that the sum of the thickness of the thick part 4 is A and the sum of the thickness of the insulating layer 6 and the thickness of the heat sink 7 is B, the sinking dimension of the thick part 4 and the thickness of the thick part 4 satisfy A> B. It is set to meet.

以上のように、実施の形態２に係る半導体装置１Ａでは、厚肉部４の上面は、薄肉部３，３ａの上面の高さ位置よりも低い高さ位置に設けられているため、外形の絶縁高さを容易に確保することができる。ここで、外形の絶縁高さとは、ヒートシンク７の裏面から端子５，５ａの下面までの高さである。また、ＩＣチップ１０の搭載部としての薄肉部３ａと、厚肉部４との距離を容易に確保することができることから、パワーチップ８，９から温度制限の低いＩＣチップ１０への熱干渉を抑制することが容易である。   As described above, in the semiconductor device 1A according to the second embodiment, the upper surface of the thick portion 4 is provided at a height position lower than the height position of the upper surfaces of the thin portions 3 and 3a. The insulation height can be easily secured. Here, the insulation height of the outer shape is the height from the back surface of the heat sink 7 to the lower surfaces of the terminals 5 and 5a. Further, since the distance between the thin portion 3a as the mounting portion of the IC chip 10 and the thick portion 4 can be easily secured, thermal interference from the power chips 8 and 9 to the IC chip 10 having a low temperature limit is prevented. It is easy to suppress.

薄肉部３，３ａの上面の高さ位置と厚肉部４の上面の高さ位置との差と、厚肉部４の厚みとの和をＡとし、絶縁層６の厚みとヒートシンク７の厚みとの和をＢとすると、Ａ＞Ｂを満たす。したがって、ヒートシンク７の材料コストを抑えつつパワーチップ８，９直下の厚肉部４の厚みを確保することができるため、半導体装置１の絶縁性の向上および熱抵抗の低減が可能となる。   The sum of the difference between the height position of the upper surface of the thin portions 3 and 3a and the height position of the upper surface of the thick portion 4 and the thickness of the thick portion 4 is A, and the thickness of the insulating layer 6 and the thickness of the heat sink 7 If the sum of B is B, A> B is satisfied. Therefore, since the thickness of the thick portion 4 immediately below the power chips 8 and 9 can be ensured while suppressing the material cost of the heat sink 7, the insulation of the semiconductor device 1 can be improved and the thermal resistance can be reduced.

＜実施の形態３＞
次に、実施の形態３に係る半導体装置１Ｂについて説明する。図６は、実施の形態３に係る半導体装置１Ｂの断面図である。なお、実施の形態３において、実施の形態１，２で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 3>
Next, a semiconductor device 1B according to the third embodiment will be described. FIG. 6 is a cross-sectional view of the semiconductor device 1B according to the third embodiment. In the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted.

図６に示すように、実施の形態３では、厚肉部４と薄肉部３，３ａとは別部材により形成され、厚肉部４は、薄肉部３，３ａよりも高い熱伝導特性を有する部材により形成されている。より具体的には、厚肉部４は、薄肉部３の下面に配置される第１部材４ａと、第１部材４ａの下面に配置される第２部材４ｂとを備えている。ここで、第１部材４ａは例えば銀、第２部材４ｂは例えば純銅により形成されている。または、第１部材４ａは例えば純銅、第２部材４ｂは例えば銀により形成されていてもよい。打ち抜き加工前に、コイル材における厚肉部４となる部分を含む領域の下面に第１部材４ａが接合され、第１部材４ａの下面に第２部材４ｂが接合される。そして、順送型の打ち抜き加工が行われることで、薄肉部３と厚肉部４が形成される。なお、厚肉部４となる部分を含む領域とは、Ｘ軸方向に隣接する厚肉部４同士の間の部分を含む領域である。   As shown in FIG. 6, in Embodiment 3, the thick portion 4 and the thin portions 3 and 3a are formed by separate members, and the thick portion 4 has higher heat conduction characteristics than the thin portions 3 and 3a. It is formed by a member. More specifically, the thick portion 4 includes a first member 4a disposed on the lower surface of the thin portion 3 and a second member 4b disposed on the lower surface of the first member 4a. Here, the first member 4a is made of, for example, silver, and the second member 4b is made of, for example, pure copper. Alternatively, the first member 4a may be formed of pure copper, for example, and the second member 4b may be formed of silver, for example. Before the punching process, the first member 4a is joined to the lower surface of the region including the portion that becomes the thick portion 4 in the coil material, and the second member 4b is joined to the lower surface of the first member 4a. And the thin part 3 and the thick part 4 are formed by punching a progressive die. In addition, the area | region including the part used as the thick part 4 is an area | region including the part between the thick parts 4 adjacent to a X-axis direction.

第１部材４ａおよび第２部材４ｂは、薄肉部３，３ａよりも高い熱伝導特性を有する部材である。なお、厚肉部４は必ずしも２種類の部材により形成される必要はなく、薄肉部３，３ａよりも高い熱伝導特性を有する１種類の部材により形成されてもよいし、３種類以上の部材により形成されてもよい。   The first member 4a and the second member 4b are members having higher heat conduction characteristics than the thin portions 3 and 3a. In addition, the thick part 4 does not necessarily need to be formed by two types of members, and may be formed by one type of member having higher heat conduction characteristics than the thin portions 3 and 3a, or three or more types of members. May be formed.

以上のように、実施の形態３に係る半導体装置１Ｂでは、厚肉部４と薄肉部３，３ａとは別部材により形成され、厚肉部４は、薄肉部３，３ａよりも高い熱伝導特性を有する部材により形成されたため、更なる放熱性の向上が可能となる。   As described above, in the semiconductor device 1B according to the third embodiment, the thick portion 4 and the thin portions 3 and 3a are formed by separate members, and the thick portion 4 has higher heat conduction than the thin portions 3 and 3a. Since it is formed of a member having characteristics, it is possible to further improve heat dissipation.

＜実施の形態４＞
次に、実施の形態４に係る半導体装置１Ｃについて説明する。図７は、実施の形態４に係る半導体装置１Ｃの断面図である。なお、実施の形態４において、実施の形態１〜３で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 4>
Next, a semiconductor device 1C according to the fourth embodiment will be described. FIG. 7 is a cross-sectional view of a semiconductor device 1C according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and description thereof is omitted.

図７に示すように、実施の形態４では、厚肉部４は２種類の異なる厚みを有している。より具体的には、例えばパワーチップ８の一端部側に対応する領域において、厚肉部４はその他の領域よりも厚みが薄く形成されている。なお、厚肉部４は２種類の異なる厚みに限定されることなく、３種類以上の異なる厚みを有していてもよい。   As shown in FIG. 7, in the fourth embodiment, the thick portion 4 has two different thicknesses. More specifically, for example, in the region corresponding to the one end portion side of the power chip 8, the thick portion 4 is formed thinner than the other regions. The thick part 4 is not limited to two different thicknesses, and may have three or more different thicknesses.

実施の形態４に係る半導体装置１Ｃでは、厚肉部４は少なくとも２種類の異なる厚みを有するため、厚肉部４における各部位毎に必要な熱抵抗値に調整することができる。厚肉部４において異なる厚みを持たせることで、熱抵抗値の調整を容易に行うことができるため、製品コストの上昇を低減することが可能となる。   In the semiconductor device 1 </ b> C according to the fourth embodiment, the thick part 4 has at least two different thicknesses, so that it can be adjusted to a necessary thermal resistance value for each part in the thick part 4. By giving the thick part 4 different thicknesses, it is possible to easily adjust the thermal resistance value, and thus it is possible to reduce an increase in product cost.

＜実施の形態５＞
次に、実施の形態５に係る半導体装置１Ｄについて説明する。図８は、実施の形態５に係る半導体装置１Ｄの断面図である。なお、実施の形態５において、実施の形態１〜４で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 5>
Next, a semiconductor device 1D according to the fifth embodiment will be described. FIG. 8 is a cross-sectional view of a semiconductor device 1D according to the fifth embodiment. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted.

図８に示すように、実施の形態５では、厚肉部４は、ワイヤ１１を介してパワーチップ８と接続されるリードフレーム２のワイヤボンド箇所にさらに設けられている。これにより、通電時にワイヤ１１から発せられる熱についても、厚肉部４を介して絶縁層６側へ放熱することが可能となる。   As shown in FIG. 8, in the fifth embodiment, the thick portion 4 is further provided at a wire bond portion of the lead frame 2 connected to the power chip 8 via the wire 11. Thereby, it is possible to radiate heat generated from the wire 11 during energization to the insulating layer 6 side through the thick portion 4.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１，１Ａ，１Ｂ，１Ｃ，１Ｄ 半導体装置、２ リードフレーム、３，３ａ 薄肉部、４ 厚肉部、５，５ａ 端子、６ 絶縁層、７ ヒートシンク、８，９ パワーチップ、１０ ＩＣチップ、１１ ワイヤ、１５ モールド樹脂。   1, 1A, 1B, 1C, 1D Semiconductor device, 2 Lead frame, 3, 3a Thin portion, 4 Thick portion, 5, 5a Terminal, 6 Insulating layer, 7 Heat sink, 8, 9 Power chip, 10 IC chip, 11 Wire, 15 Mold resin.

Claims (10)

パワーチップと、
前記パワーチップを駆動するＩＣチップと、
薄肉部と、前記薄肉部の厚みよりも厚い厚肉部とを有するリードフレームと、
を備え、
前記パワーチップは前記厚肉部に搭載され、前記ＩＣチップは前記薄肉部に搭載された、半導体装置。 A power chip,
An IC chip for driving the power chip;
A lead frame having a thin portion and a thick portion thicker than the thickness of the thin portion;
With
The power chip is mounted on the thick part, and the IC chip is mounted on the thin part. 前記パワーチップの端と、当該パワーチップの当該端側に対応する前記厚肉部の端との距離をａとし、前記厚肉部の厚みをｔとすると、
前記パワーチップの４辺のうち少なくとも１辺でｔ≧ａを満たす、請求項１記載の半導体装置。 When the distance between the end of the power chip and the end of the thick part corresponding to the end side of the power chip is a, and the thickness of the thick part is t,
The semiconductor device according to claim 1, wherein t ≧ a is satisfied on at least one side of the four sides of the power chip. 前記厚肉部の上面は、前記薄肉部の上面の高さ位置よりも低い高さ位置に設けられた、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein an upper surface of the thick portion is provided at a height position lower than a height position of the upper surface of the thin portion. 前記厚肉部は複数であり、
前記半導体装置は、前記リードフレームの一部、前記パワーチップおよび前記ＩＣチップを封止するモールド樹脂をさらに備え、
前記リードフレームは、前記モールド樹脂から第１の方向に突出する端子をさらに有し、
各前記厚肉部は、前記第１の方向に直交する第２の方向に沿って一直線上に設けられた、請求項１記載の半導体装置。 The thick part is plural,
The semiconductor device further includes a mold resin that seals a part of the lead frame, the power chip, and the IC chip,
The lead frame further includes a terminal protruding from the mold resin in a first direction,
2. The semiconductor device according to claim 1, wherein each of the thick portions is provided on a straight line along a second direction orthogonal to the first direction. 前記厚肉部と前記薄肉部とは別部材により形成され、
前記厚肉部は、前記薄肉部よりも高い熱伝導特性を有する部材により形成された、請求項１記載の半導体装置。 The thick part and the thin part are formed by separate members,
The semiconductor device according to claim 1, wherein the thick portion is formed of a member having higher heat conduction characteristics than the thin portion. 前記厚肉部にめっきが施された、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the thick portion is plated. 前記厚肉部は少なくとも２種類の異なる厚みを有する、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the thick portion has at least two different thicknesses. 前記厚肉部の下面に配置された絶縁層と、前記絶縁層の下面に配置されたヒートシンクとをさらに備え、
前記薄肉部の上面の高さ位置と前記厚肉部の上面の高さ位置との差と、前記厚肉部の厚みとの和をＡとし、前記絶縁層の厚みと前記ヒートシンクの厚みとの和をＢとすると、
Ａ＞Ｂを満たす、請求項３記載の半導体装置。 An insulating layer disposed on the lower surface of the thick portion; and a heat sink disposed on the lower surface of the insulating layer,
The sum of the difference between the height position of the upper surface of the thin portion and the height position of the upper surface of the thick portion and the thickness of the thick portion is A, and the thickness of the insulating layer and the thickness of the heat sink If the sum is B,
The semiconductor device according to claim 3, wherein A> B is satisfied. 前記厚肉部は、ワイヤを介して前記パワーチップと接続される前記リードフレームのワイヤボンド箇所にさらに設けられた、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the thick portion is further provided at a wire bond portion of the lead frame connected to the power chip through a wire. 前記パワーチップはＳｉＣを材料として形成された、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the power chip is formed using SiC as a material.
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