JP2004146706A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004146706A
JP2004146706A JP2002312002A JP2002312002A JP2004146706A JP 2004146706 A JP2004146706 A JP 2004146706A JP 2002312002 A JP2002312002 A JP 2002312002A JP 2002312002 A JP2002312002 A JP 2002312002A JP 2004146706 A JP2004146706 A JP 2004146706A
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Japan
Prior art keywords
semiconductor element
semiconductor device
sealing resin
lead
semiconductor
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JP2002312002A
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Japanese (ja)
Inventor
Hiroshi Abe
安部　洋
Shinji Watanabe
渡辺　信二
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Sony Corp
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Sony Corp
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Priority to JP2002312002A priority Critical patent/JP2004146706A/en
Publication of JP2004146706A publication Critical patent/JP2004146706A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which occurrence of warping is suppressed. <P>SOLUTION: This semiconductor device comprises a semiconductor element 2; a lead 3, having a first top part 4 and a second top part 5, in which a thickness of the first top part is thicker than that of the semiconductor element; a bonding wire 6 connecting the semiconductor element to the second top part; and a sealing resin 7 sealing the semiconductor element and the bonding wire. In this device, a recessed part 8 is provided in an upper part of the semiconductor element of the sealing resin. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関する。詳しくは、アウターリードの突出が無い表面実装型パッケージの半導体装置に係るものである。
【０００２】
【従来の技術】
近年、電子機器の小型化、高機能化の要求に対応するために半導体装置の小型化・薄型化が継続的に強く求められており、実装面積が小さい表面実装型のパッケージが種々開発されている。
【０００３】
以下、図面を用いて従来の表面実装型パッケージの半導体装置について説明する。
図５は従来の半導体装置を説明するための模式的な断面図であり、ここで示す表面実装型パッケージの半導体装置１０１は、半導体素子１０２の対向する２辺の側方に近接して多数のリード１０３が配設されており、各リードの上面側は段差を有し、上面上段部１０４と上面下段部１０５から成っている。ここで、リードの上面上段部の厚さは半導体素子の厚さより大きく、ボンディングワイヤ１０６によってリードの上面下段部は半導体素子表面の電極パッド（図示せず）とボンディングされており、ボンディングワイヤのループの頂点はリードの上面上段部よりも低く形成されている。
また、半導体素子とボンディングワイヤを封止する封止樹脂１０７は、その表面がリードの上面上段部と同一平面をなし、その裏面が半導体素子の裏面及びリードの下面と同一平面をなす様に形成されている。即ち、リードの上面上段部、半導体素子の裏面及びリードの下面が露出する様に形成されている（例えば、特許文献１参照。）。
【０００４】
【特許文献１】
特開２００１−１７７００５号公報（第２−３頁、第１図）
【０００５】
【発明が解決しようとする課題】
上記の様に構成された従来の半導体装置では、各リードの上下面とも封止樹脂から露出しているために、多段化による３Ｄモジュール化が容易であるものの、半導体素子と比較して封止樹脂の膨張係数が大きいために、図５中符号Ａで示す部分において温度変化に伴い半導体素子と封止樹脂の膨張係数の差により生じる応力によって半導体装置の反りが発生してしまうという不都合がある。
【０００６】
即ち、例えば、熱硬化性の封止樹脂を成形する高温、例えば１７５℃から常温へ冷却した場合に温度変化に伴い収縮が生じ、半導体素子と封止樹脂の膨張係数の差によって図６で示す様に半導体装置の反りが発生してしまい基板への半田付けの作業性が悪いという不都合や、半導体装置を駆動する際に生じる熱によって半導体装置の反りの発生及び緩和という状態を繰り返すために基板に半田付けを行った際の半田付け部の温度サイクルに対する劣化が早いという不都合がある。
【０００７】
なお、リードと封止樹脂の膨張係数の差によって図５中符号Ｂで示す部分においても応力が発生し得るが、半導体素子と封止樹脂の膨張係数の差に基づいて発生する応力と比較すると、その影響は極めて少ないと考え得る。
【０００８】
本発明は、以上の点に鑑みて創案されたものであって、反りの発生を抑制することができる半導体装置を提供することを目的とするものである。
【０００９】
【課題を解決するための手段】
上記の目的を達成するために、本発明に係る半導体装置は、半導体素子と、該半導体素子の側方に近接して配設されると共に、その上面は第１の上面部と該第１の上面部よりその高さが小さな第２の上面部を有し、前記第１の上面部の厚さが前記半導体素子の厚さよりも大きなリードと、前記半導体素子と前記第２の上面部とを接続するボンディングワイヤと、前記半導体素子の裏面、前記第１の上面部及び前記リードの下面が露出する様に半導体素子及びボンディングワイヤを封止する封止樹脂とを備える半導体装置において、前記封止樹脂の前記半導体素子の上方部に凹部を設けた。
【００１０】
ここで、封止樹脂は、半導体素子の上方部に凹部を設けることによって半導体素子と封止樹脂の膨張係数の差により生じる応力を緩和することができる。
【００１１】
【発明の実施の形態】
以下、本発明の実施の形態を図面を参照しながら説明し、本発明の理解に供する。
【００１２】
図１は本発明を適用した半導体装置の一例を説明するための模式的な断面図及び斜視図であり、ここで示す半導体装置１は、上記した従来の半導体装置と同様に、半導体素子２の対向する２辺の側方に近接して多数の銅製のリード３が配設されており、各リードの上面側は段差を有し、上面上段部４と上面下段部５から成っている。ここで、リードの上面上段部の厚さは半導体素子の厚さより大きく、ボンディングワイヤ６によってリードの上面下段部は半導体素子表面の電極パッド（図示せず）とボンディングされており、ボンディングワイヤのループの頂点はリードの上面上段部よりも低く形成されている。
また、膨張係数が銅と同程度である封止樹脂７は、半導体素子の裏面、上面上段部及びリードの下面が露出する様に半導体素子とボンディングワイヤを封止すると共に、半導体素子の上方部に凹部８が形成され、ボンディングワイヤの上方部に凸部９が形成されている。
【００１３】
ここで、封止樹脂に形成された凹部は半導体素子と封止樹脂の膨張係数の差により生じる応力を緩和するために形成されたものであり、応力の緩和を図ることができるのであれば必ずしも図１に表す様に図１中符号ａで示す半導体装置の第１の側面から第１の側面に対向する図１中符号ｂで示す第２の側面まで一様に形成された凹部形状である必要は無く、例えば図２（ａ）に示す様に、半導体素子の上方部のみに凹部を形成したり、図２（ｂ）に示す様に、半導体素子の上方部のうち一部分のみに凹部を形成したりする等、いかなる形状であっても構わない。
【００１４】
同様に、凹部は半導体素子と封止樹脂の膨張係数の差により生じる応力を緩和することができれば充分であって、必ずしも凹部が形成された個所の厚さがリードの厚さよりも小さくなる様に形成される必要は無く、例えば図３に示す様に、半導体素子の上方部に凹部が形成されることなくボンディングワイヤの上方部に凹部が形成され、半導体素子の上方部に相対的に凹部が形成されたとしても構わない。
【００１５】
また、半導体素子の上方部に凹部が形成されることによって半導体素子と封止樹脂との膨張係数の差により生じる応力を緩和することができるために、半導体素子の上方部に凹部が形成された場合には必ずしもボンディングワイヤの上方部に凸部が形成される必要は無いが、ボンディングワイヤが封止樹脂表面から露出してしまう危険性を下げると共に、半導体装置の機械的強度の向上を図るべくボンディングワイヤの上方部には凸部が形成された方が好ましい。なお、図１中符号ｃで示す凸部の高さは、図４で示す様に半導体装置を積層して基板に搭載する場合を考慮すると、積層接続部１０の高さよりも大きくならない様に形成される必要がある。
【００１６】
また、上記した様に、半導体素子の周辺部におけるリードと封止樹脂の膨張係数の差により生じる応力は半導体素子と封止樹脂の膨張係数の差により生じる応力と比較すると小さく、半導体装置の反りに及ぼす影響は極めて小さいために封止樹脂に形成された凹部により半導体素子と封止樹脂の膨張係数の差に基づいて生じる応力を緩和することによって半導体装置の反りを抑制することが可能であるために、必ずしもリードの素材である銅と膨張係数が同程度である封止樹脂で封止を行う必要は無いが、リードと封止樹脂の膨張係数の差により生じる応力をも緩和することによって、より一層半導体装置の反りを抑制すべく銅と膨張係数が同程度の封止樹脂で封止を行う方が好ましい。
【００１７】
更に、リードの上面側に段差が形成されているのは、上面下段部をボンディングし上面上段部を封止樹脂から露出させるためであり、リードの上面側が段差を有し上面上段部を封止樹脂から露出させることができるのであれば、リードの上面側に形成された段差の段数は必ずしも２段である必要は無い。
【００１８】
本発明を適用した半導体装置では、半導体素子の上方部の封止樹脂量が少なくなり、封止樹脂の収縮応力が小さくなることによって、半導体素子と封止樹脂の膨張係数の差により生じる応力を緩和することができ、半導体装置の反りの発生を抑制することが可能であると共に、半田付け作業性の向上及び半田付け部の温度サイクルに対する信頼性の向上を図ることができる。
即ち、１０ｍｍ×２０ｍｍ×０．２ｍｍの寸法である半導体装置を、封止樹脂を成形する１７５℃の温度から常温（２５℃）に冷却した場合に、従来の半導体装置、即ち、半導体素子の上方部に凹部が形成されていない場合には図６中符号ｄで示す実装基板からの半導体装置の取付高さが４１８．９μｍであるのに対して、本発明を適用した半導体装置、即ち、半導体素子の上方部に凹部が形成された場合には実装基板からの半導体装置の取付高さが３４０．０μｍと小さく、半導体素子の上方部に凹部が形成されたことによって半導体装置の反りの発生が抑制されている。
【００１９】
また、ボンディングワイヤの上方部に凸部が形成されたことによって、ボンディングワイヤの露出による歩留りの低下や断線不良を抑制することができると共に、半導体装置の機械的強度の向上を図ることが可能である。
【００２０】
更に、リードの上下面が共に封止樹脂から露出しているために、図４で示す様に、積層接続部を介して積層することができ、厚みがかさばることなく半導体装置を積層することが可能である。
【００２１】
【発明の効果】
以上述べてきた如く、本発明の半導体装置によれば、反りの発生を抑制することができる。
【図面の簡単な説明】
【図１】本発明を適用した半導体装置の一例を説明するための模式的な断面図及び斜視図である。
【図２】凹部形状の変形例を説明するための模式的な斜視図である。
【図３】本発明を適用した半導体装置の他の一例を説明するための模式的な断面図及び斜視図である。
【図４】半導体装置を積層して基板に搭載した状態を説明するための模式的な断面図である。
【図５】従来の半導体装置を説明するための模式的な断面図である。
【図６】半導体装置の反りの発生を説明するための模式的な断面図である。
【符号の説明】
１　　半導体装置
２　　半導体素子
３　　リード
４　　上面上段部
５　　上面下段部
６　　ボンディングワイヤ
７　　封止樹脂
８　　凹部
９　　凸部
１０　　積層接続部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device of a surface mount type package having no protruding outer leads.
[0002]
[Prior art]
In recent years, there has been a continuing strong demand for smaller and thinner semiconductor devices in order to respond to demands for smaller and more sophisticated electronic devices, and various surface mount packages having a small mounting area have been developed. I have.
[0003]
Hereinafter, a conventional semiconductor device of a surface mount type package will be described with reference to the drawings.
FIG. 5 is a schematic cross-sectional view for explaining a conventional semiconductor device. A semiconductor device 101 of a surface mount type package shown here has a large number of semiconductor devices 102 that are close to two sides of a semiconductor element 102 facing each other. The leads 103 are provided, and the upper surface side of each lead has a step, and is composed of an upper surface upper portion 104 and an upper surface lower portion 105. Here, the thickness of the upper part of the upper surface of the lead is larger than the thickness of the semiconductor element, and the lower part of the upper surface of the lead is bonded to an electrode pad (not shown) on the surface of the semiconductor element by the bonding wire 106. Are formed lower than the upper step of the upper surface of the lead.
The sealing resin 107 for sealing the semiconductor element and the bonding wire is formed such that its surface is flush with the upper step of the upper surface of the lead and its back surface is flush with the back surface of the semiconductor element and the lower surface of the lead. Have been. That is, the upper surface of the lead, the lower surface of the semiconductor element, and the lower surface of the lead are formed so as to be exposed (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-177005 A (page 2-3, FIG. 1)
[0005]
[Problems to be solved by the invention]
In the conventional semiconductor device configured as described above, since both the upper and lower surfaces of each lead are exposed from the sealing resin, it is easy to form a 3D module by increasing the number of stages. Since the expansion coefficient of the resin is large, there is an inconvenience that the semiconductor device is warped due to a stress caused by a difference in expansion coefficient between the semiconductor element and the sealing resin due to a temperature change in a portion indicated by reference numeral A in FIG. .
[0006]
That is, for example, when the thermosetting sealing resin is cooled from a high temperature, for example, 175 ° C., to room temperature, shrinkage occurs with a temperature change, and the difference between the expansion coefficients of the semiconductor element and the sealing resin is shown in FIG. As described above, the semiconductor device may be warped and the workability of soldering to the substrate may be poor, or the semiconductor device may be repeatedly warped and relaxed due to heat generated when the semiconductor device is driven. However, there is an inconvenience that the temperature cycle of the soldered portion deteriorates quickly when soldering is performed.
[0007]
Although a stress may be generated in a portion indicated by reference numeral B in FIG. 5 due to a difference in expansion coefficient between the lead and the sealing resin, compared with a stress generated based on a difference in expansion coefficient between the semiconductor element and the sealing resin. The effect can be considered to be extremely small.
[0008]
The present invention has been made in view of the above points, and has as its object to provide a semiconductor device capable of suppressing the occurrence of warpage.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is provided with a semiconductor element and a semiconductor element disposed close to a side of the semiconductor element. A lead having a second upper surface portion whose height is smaller than the upper surface portion, wherein the thickness of the first upper surface portion is larger than the thickness of the semiconductor element; and the semiconductor element and the second upper surface portion A semiconductor device comprising: a bonding wire to be connected; and a sealing resin that seals the semiconductor element and the bonding wire such that a back surface of the semiconductor element, the first upper surface, and a lower surface of the lead are exposed. A concave portion was provided in an upper portion of the resin semiconductor element.
[0010]
Here, the sealing resin can reduce stress caused by a difference in expansion coefficient between the semiconductor element and the sealing resin by providing a concave portion above the semiconductor element.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings to provide an understanding of the present invention.
[0012]
FIG. 1 is a schematic cross-sectional view and a perspective view illustrating an example of a semiconductor device to which the present invention is applied. The semiconductor device 1 shown here has a semiconductor element 2 similar to the above-described conventional semiconductor device. A large number of copper leads 3 are arranged close to the sides of the two opposing sides, and the upper surface side of each lead has a step, and is composed of an upper surface upper step portion 4 and an upper surface lower step portion 5. Here, the thickness of the upper portion of the upper surface of the lead is larger than the thickness of the semiconductor element, and the lower portion of the upper surface of the lead is bonded to an electrode pad (not shown) on the surface of the semiconductor device by a bonding wire 6. Are formed lower than the upper step of the upper surface of the lead.
In addition, the sealing resin 7 having an expansion coefficient substantially equal to that of copper seals the semiconductor element and the bonding wire so that the back surface of the semiconductor element, the upper step, and the lower surface of the lead are exposed. A concave portion 8 is formed on the upper side of the bonding wire, and a convex portion 9 is formed above the bonding wire.
[0013]
Here, the concave portion formed in the sealing resin is formed to alleviate the stress caused by the difference in the expansion coefficient between the semiconductor element and the sealing resin, and is not necessarily provided that the stress can be alleviated. As shown in FIG. 1, the semiconductor device has a concave shape uniformly formed from a first side surface of the semiconductor device indicated by reference numeral a in FIG. 1 to a second side surface indicated by reference numeral b in FIG. 1 opposed to the first side surface. There is no necessity. For example, as shown in FIG. 2A, a concave portion is formed only in an upper portion of the semiconductor element, or as shown in FIG. 2B, a concave portion is formed only in a part of the upper portion of the semiconductor element. It may be of any shape, such as formed.
[0014]
Similarly, the recess is sufficient if it can relieve the stress caused by the difference in the expansion coefficient between the semiconductor element and the sealing resin, so that the thickness of the portion where the recess is formed is always smaller than the thickness of the lead. It is not necessary to form the recess, for example, as shown in FIG. 3, a recess is formed above the bonding wire without forming a recess above the semiconductor element, and a recess is formed relatively above the semiconductor element. It may be formed.
[0015]
In addition, since the stress generated due to the difference in expansion coefficient between the semiconductor element and the sealing resin can be reduced by forming the concave portion above the semiconductor element, the concave portion is formed above the semiconductor element. In this case, it is not always necessary to form a convex portion above the bonding wire, but in order to reduce the risk of the bonding wire being exposed from the sealing resin surface and to improve the mechanical strength of the semiconductor device. It is preferable that a convex portion is formed above the bonding wire. Note that the height of the protruding portion indicated by reference numeral c in FIG. 1 is formed so as not to be larger than the height of the stacked connection portion 10 in consideration of the case where semiconductor devices are stacked and mounted on a substrate as shown in FIG. Need to be done.
[0016]
Further, as described above, the stress caused by the difference in the expansion coefficient between the lead and the sealing resin in the peripheral portion of the semiconductor element is smaller than the stress caused by the difference in the expansion coefficient between the semiconductor element and the sealing resin. Since the influence on the semiconductor device is extremely small, it is possible to suppress the warpage of the semiconductor device by relaxing the stress generated based on the difference in the expansion coefficient between the semiconductor element and the sealing resin by the concave portion formed in the sealing resin. Therefore, it is not always necessary to perform sealing with a sealing resin having an expansion coefficient substantially equal to that of copper, which is a material of the lead, but by relaxing a stress caused by a difference in expansion coefficient between the lead and the sealing resin, In order to further suppress the warpage of the semiconductor device, it is preferable to perform sealing with a sealing resin having an expansion coefficient similar to that of copper.
[0017]
Further, the step is formed on the upper surface side of the lead in order to bond the lower step on the upper surface and expose the upper step on the upper surface from the sealing resin, and the upper surface side of the lead has a step and seals the upper step on the upper surface. As long as it can be exposed from the resin, the number of steps formed on the upper surface side of the lead does not necessarily need to be two.
[0018]
In the semiconductor device to which the present invention is applied, the amount of the sealing resin in the upper part of the semiconductor element is reduced, and the contraction stress of the sealing resin is reduced, so that the stress generated due to the difference in expansion coefficient between the semiconductor element and the sealing resin is reduced. As a result, the warpage of the semiconductor device can be suppressed, and the workability of the soldering operation and the reliability of the soldered portion against the temperature cycle can be improved.
That is, when a semiconductor device having a size of 10 mm × 20 mm × 0.2 mm is cooled from a temperature of 175 ° C. for molding a sealing resin to a normal temperature (25 ° C.), a conventional semiconductor device, that is, above a semiconductor element, is cooled. In the case where no concave portion is formed in the portion, the mounting height of the semiconductor device from the mounting substrate indicated by reference numeral d in FIG. 6 is 418.9 μm, whereas the semiconductor device to which the present invention is applied, ie, the semiconductor When the recess is formed above the element, the mounting height of the semiconductor device from the mounting board is as small as 340.0 μm, and the formation of the recess above the semiconductor element causes the warpage of the semiconductor device. Is suppressed.
[0019]
In addition, since the convex portion is formed above the bonding wire, it is possible to suppress a decrease in yield and a disconnection failure due to the exposure of the bonding wire, and it is possible to improve the mechanical strength of the semiconductor device. is there.
[0020]
Further, since both the upper and lower surfaces of the leads are exposed from the sealing resin, as shown in FIG. 4, the leads can be laminated via the laminated connecting portion, and the semiconductor device can be laminated without increasing the thickness. It is possible.
[0021]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, occurrence of warpage can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view and a perspective view illustrating an example of a semiconductor device to which the present invention is applied.
FIG. 2 is a schematic perspective view for explaining a modified example of a concave shape.
FIG. 3 is a schematic cross-sectional view and a perspective view illustrating another example of a semiconductor device to which the present invention is applied.
FIG. 4 is a schematic cross-sectional view illustrating a state in which semiconductor devices are stacked and mounted on a substrate.
FIG. 5 is a schematic cross-sectional view illustrating a conventional semiconductor device.
FIG. 6 is a schematic cross-sectional view for explaining the occurrence of warpage of the semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 Lead 4 Upper surface upper part 5 Upper surface lower part 6 Bonding wire 7 Sealing resin 8 Concave part 9 Convex part 10 Stack connection part

Claims (3)

半導体素子と、
該半導体素子の側方に近接して配設されると共に、その上面は第１の上面部と該第１の上面部よりその高さが小さな第２の上面部を有し、前記第１の上面部の厚さが前記半導体素子の厚さよりも大きなリードと、
前記半導体素子と前記第２の上面部とを接続するボンディングワイヤと、
前記半導体素子の裏面、前記第１の上面部及び前記リードの下面が露出する様に半導体素子及びボンディングワイヤを封止する封止樹脂とを備える半導体装置において、
前記封止樹脂の前記半導体素子の上方部には凹部が設けられている
ことを特徴とする半導体装置。A semiconductor element;
The semiconductor device is disposed adjacent to the side of the semiconductor element, and has an upper surface having a first upper surface portion and a second upper surface portion having a height smaller than that of the first upper surface portion. A lead having a thickness of the upper surface portion larger than the thickness of the semiconductor element;
A bonding wire connecting the semiconductor element and the second upper surface,
A semiconductor device comprising: a sealing resin that seals the semiconductor element and the bonding wire such that the back surface of the semiconductor element, the first upper surface, and the lower surface of the lead are exposed;
A semiconductor device, wherein a recess is provided in an upper portion of the sealing resin above the semiconductor element. 前記リードを形成する材料と前記封止樹脂を形成する材料の膨張係数が略同一である
ことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein a material forming the lead and a material forming the sealing resin have substantially the same expansion coefficient. 積層接続部を介して積層した
ことを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the semiconductor device is stacked via a stacked connection portion.
JP2002312002A 2002-10-28 2002-10-28 Semiconductor device Pending JP2004146706A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008060562A (en) * 2006-08-04 2008-03-13 Dainippon Printing Co Ltd Resin sealed semiconductor device, manufacturing method for the same, base material for semiconductor device, and layered resin sealed semiconductor device
KR100850147B1 (en) * 2005-12-12 2008-08-04 미쓰비시덴키 가부시키가이샤 Semiconductor device and mold for resin-molding semiconductor device
JP2010177388A (en) * 2009-01-29 2010-08-12 Panasonic Corp Semiconductor device, and method of manufacturing the same
JP2018032852A (en) * 2016-08-22 2018-03-01 ローム株式会社 Semiconductor device, and mounting structure for the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100850147B1 (en) * 2005-12-12 2008-08-04 미쓰비시덴키 가부시키가이샤 Semiconductor device and mold for resin-molding semiconductor device
US7808085B2 (en) 2005-12-12 2010-10-05 Mitsubishi Electric Corporation Semiconductor device and mold for resin-molding semiconductor device
JP2008060562A (en) * 2006-08-04 2008-03-13 Dainippon Printing Co Ltd Resin sealed semiconductor device, manufacturing method for the same, base material for semiconductor device, and layered resin sealed semiconductor device
JP2010177388A (en) * 2009-01-29 2010-08-12 Panasonic Corp Semiconductor device, and method of manufacturing the same
JP2018032852A (en) * 2016-08-22 2018-03-01 ローム株式会社 Semiconductor device, and mounting structure for the same

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