JP2011233610A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having reduced thickness and preventing an occurrence of warpage accompanied by the reduction.SOLUTION: A semiconductor device 10 comprises a semiconductor chip 11, a wiring board 12, and an encapsulation resin 15. The wiring board has a first solder resist on a semiconductor chip-mounting surface on which the semiconductor chip is mounted. The encapsulation resin seals the semiconductor chip mounted on the semiconductor chip-mounting surface. The region on the semiconductor chip-mounting surface on which the semiconductor chip is mounted is a non-coated region in which the first solder resist is not provided.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a package structure using a wiring board having solder resists on the front and back surfaces thereof.

  As a package structure of a semiconductor device, a BGA (ball grid array) type suitable for miniaturization and thinning is widely used. In this structure, a semiconductor chip and a sealing resin for sealing the semiconductor chip are mounted on one surface side of the wiring board, and external connection terminals are mounted on the other surface side. The surface of one surface and the other surface of the wiring board used in such a semiconductor device is covered with a solder resist except for electrical connection portions such as connection pads and land portions.

  Wiring boards have been thinned to meet the demand for smaller and thinner semiconductor devices. For this reason, the rigidity of the wiring board is lowered, and warping has occurred due to the difference in the configuration (coverage of the load or solder resist, etc.) between the one surface side and the other surface side. Such warpage of the wiring board deteriorates the external mountability of the semiconductor device and reduces the product yield.

  Conventionally, as a method for preventing or suppressing warping of a wiring board, a method of keeping the coating area ratio and the thickness ratio of a solder resist provided on one side and the other side of the wiring board within a certain range ( There is a first method) (see, for example, Patent Document 1).

  In addition, there is a method (second method) in which the thickness of the solder resist provided on the one surface side and the other surface side of the wiring board is made the same, and the covering surface region is made the same (also Patent Document 1). reference).

  Furthermore, there is a method of adjusting the thickness of the solder resist provided on the front and back surfaces of the wiring board (see, for example, Patent Document 2).

JP-A-9-172104 JP 2007-242673 A

  None of the first and second methods described in Patent Document 1 considers the presence of a semiconductor chip or a sealing resin mounted on a wiring board. That is, the method described in Patent Document 1 is intended to suppress warping of a single wiring board. For this reason, these methods have a problem that warpage of the wiring substrate in a state where the semiconductor chip or the sealing resin is mounted, that is, warpage of the entire semiconductor device cannot be sufficiently suppressed.

  Moreover, since the 1st method described in patent document 1 makes the thickness ratio of a soldering resist the range of 3: 1-1.5: 1, the thickness of the soldering resist on the one side is appropriate thickness. If it is set to (as thin as possible), it is necessary to make the solder resist on the other surface side 2/3 to 1/3 of the thickness (thin), and the surface on which irregularities are formed by metal wiring etc. However, it is difficult or impossible to form a solder resist uniformly. On the other hand, if the solder resist on the other side is set to an appropriate thickness, the thickness of the solder resist on the one side must be 1.5 to 3 times the thickness, thereby inhibiting thinning, In addition, the amount of solder resist having a large linear expansion coefficient increases, so that there is a problem that the amount of change in thermal warpage temporarily increases during heating and cooling operations.

  In the first method described in Patent Document 1, the solder resist coating area ratio provided on both surfaces of the wiring board is such that the bonding portion is exposed on one surface side and the land portion is exposed on the other surface side. Therefore, it is assumed that the ratio is 1: 1.3 to 1: 1.7. In Patent Document 1, there is no description about intentionally keeping the covering area ratio within the above range.

  Further, in the second method described in Patent Document 1, the surface of the wiring board is exposed more than necessary on at least one surface in order to make the coated areas of the one side of the wiring board and the solder resist on the other side correspond to each other. It will be. As a result, there is a problem in that the exposure amount of the metal wiring and the metal plating portion around the land portion increases, and the possibility of metal peeling or scratches increases.

  On the other hand, the method described in Patent Document 2 considers the influence of electronic components mounted on a wiring board. However, this method is applied to a relatively large and highly rigid wiring board on which a plurality of electronic components are mounted, and can be applied to a wiring board used for a BGA package or the like that is becoming smaller and thinner. is not. Even if applicable, the first method described in Patent Document 1 is that the thickness of the solder resist provided on one surface of the wiring board is thicker than the solder resist provided on the other surface. In common, there are problems such as obstructing thinning.

  The inventor, due to recent downsizing and thinning of the semiconductor device, the warp that occurs in the semiconductor device is caused by the difference in the amount of expansion and contraction that occurs in the solder resist provided on one side and the other side of the wiring board, It has been found that this is due to the difference in expansion and contraction between the semiconductor chip and the sealing resin and the entire wiring board. Such warpage cannot be prevented or suppressed by the methods described in Patent Documents 1 and 2.

  In view of the above, there is a demand for the reduction in size and thickness of semiconductor devices and the prevention or suppression of warping that accompanies them.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor chip, a wiring board in which a first solder resist is provided on a semiconductor chip mounting surface on which the semiconductor chip is mounted, and mounted on the semiconductor chip mounting surface. A sealing resin for sealing the semiconductor chip, and a region of the semiconductor chip mounting surface on which the semiconductor chip is mounted is an uncovered region in which the first solder resist is not provided Features.

  According to the present invention, the area of the wiring board on which the semiconductor chip is mounted is defined as an uncovered area where the first solder resist is not provided. Thereby, the height of the semiconductor chip mounted on the wiring board can be reduced by the thickness of the first solder resist, and the thickness can be reduced. Moreover, since the coating area of the first solder resist is reduced, the force that causes the warp is reduced, and the warp can be suppressed. Thus, according to the present invention, it is possible to suppress the thinning of the semiconductor device and the warpage caused thereby.

It is sectional drawing which shows schematic structure of the semiconductor device which concerns on the 1st Embodiment of this invention. It is an enlarged view in the broken line A of FIG. It is a top view which shows the 1st surface of the wiring board used for the semiconductor device of FIG. FIG. 3 is a plan view showing a second surface of a wiring board used in the semiconductor device of FIG. 1. It is sectional drawing which shows the model used for simulation. It is a graph which shows a simulation result.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 10 according to a first embodiment of the present invention. FIG. 2 is an enlarged view within a broken line A in FIG. Here, a semiconductor device having a BGA (ball grid array) type package structure is illustrated as a semiconductor device, but the present invention can also be applied to other semiconductor devices such as an LGA (land grid array) type and MCP (multichip package). It is.

  The illustrated semiconductor device 10 includes a semiconductor chip 11, a wiring substrate 12, an insulating adhesive 13, a bonding wire 14, a sealing resin (resin) 15, and an external connection terminal 16.

  The semiconductor chip 11 has a thin plate shape having a pair of front and back surfaces of a substantially rectangular shape. One surface of the front and back surfaces (the upper surface in FIGS. 1 and 2, here, the front surface) is a circuit formation surface 112 on which at least one semiconductor element (not shown) and a plurality of electrode pads 111 are formed. is there.

  The wiring substrate 12 is a thin plate-like, for example, glass epoxy substrate having a pair of front and back surfaces (first surface and second surface) that are substantially rectangular. One of the front and rear surfaces (here, the first surface) is a semiconductor chip mounting surface on which the semiconductor chip 11 is mounted, and the other (here, the second surface) is mounted with the external connection terminal 16. The external connection terminal mounting surface. The planar shape of the wiring board 12 is larger than the surface shape of the semiconductor chip 11.

  The wiring substrate 12 includes a substrate core part 121, connection wiring layers 122 and 123 formed on the front and back surfaces thereof, and first and second solders covering at least a part of each of the connection wiring layers 122 and 123. It has resists (insulating films) 124 and 125. Here, the wiring substrate 12 having the connection wiring layers 122 and 123 on the front and back surfaces of the substrate core part 121 is illustrated, but a multilayer wiring substrate in which three or more connection wiring layers and insulating layers are alternately stacked. It may be.

  The connection wiring layers 122 and 123 are metal plating portions made of, for example, Au or Cu, and are patterned into a predetermined shape, for example, a pad shape or a wiring shape. Further, in the connection wiring layer 123 formed on the back surface side (lower side in FIGS. 1 and 2) of the substrate core part 121, a plurality of land parts 126 are arranged and formed by, for example, metal plating. A part of the connection wiring layer 122 formed on the surface side of the substrate core part 121 (upper side in FIGS. 1 and 2) constitutes a connection pad part 127 for connecting and fixing the bonding wire 14. These connection pad portions 127 and the land portions 126 correspond one to one. That is, the connection wiring layers 122 and 123 are connected to each other by a plurality of through vias 128 formed through the substrate core portion 121 so as to electrically connect each land portion 126 and the corresponding connection pad portion 127. Has been.

  The first and second solder resists 124 and 125 are provided to ensure insulation, improve the peeling strength of the metal plating portion, and prevent scratches and dirt. The first solder resist 124 formed on the first surface side of the wiring board 12 (upper side in FIGS. 1 and 2) includes a semiconductor chip mounting area for mounting the semiconductor chip 11 and an area for exposing the connection pad portion 127. It is formed in the area except. The second solder resist 125 formed on the second surface side (lower side in FIGS. 1 and 2) of the wiring board 12 is formed in a region other than the region where the land portion 126 is formed. The first and second solder resists 124 and 125 may be formed to the same thickness using the same material.

  The insulative adhesive 13 is, for example, a solid sheet-shaped DAF (die attach film). The insulating adhesive 13 is provided in a semiconductor chip mounting area defined on the first surface side of the wiring board 12. This semiconductor chip mounting area is an uncovered area where the first solder resist is not provided as described above. The insulating adhesive 13 is cured by heating or the like, and the semiconductor chip 11 is bonded and fixed to the wiring board 12. The semiconductor chip 11 is in a so-called face-up state in which the circuit forming surface 112 faces in the direction opposite to the wiring substrate 12 and the surface opposite to the circuit forming surface 112, that is, the back surface 113 faces the wiring substrate 12. It is mounted on the semiconductor chip mounting area of the wiring board 12.

  The bonding wire 14 is made of a conductive metal, such as Au, and electrically connects the electrode pad 111 of the semiconductor chip 11 and the connection pad portion 127 of the wiring board 12. As described above, since the connection pad portion 127 has a one-to-one correspondence with the land portion 126, each electrode pad 111 is electrically connected to the corresponding land portion 126 by the connection by the bonding wire 14.

  The sealing resin 15 is made of, for example, an epoxy resin and seals the semiconductor chip 11 together with the bonding wires 14. The sealing resin 15 is formed so that the outer thickness of the semiconductor device is uniform up to the outer peripheral end of the wiring substrate 12. In other words, the sealing resin 15 has an outer peripheral surface coinciding with the edge of the wiring board 12 and is formed so that the height in the thickness direction of the wiring board 12 is uniform (uniform).

  The external connection terminal 16 is, for example, a solder ball. The external connection terminals 16 are respectively provided on the land portions 126 and correspond to the electrode pads 111 of the semiconductor chip 11 on a one-to-one basis.

  Next, the first and second solder resists 124 and 125 provided on the wiring board 12 will be further described with reference to FIGS.

  FIG. 3 is a plan view of the first surface (semiconductor chip mounting surface) of the wiring board 12 used in the semiconductor device 10. As shown in the figure, the solder resist 124 provided on the first surface of the wiring board 12 is in a region excluding the semiconductor chip mounting region 201 for mounting the semiconductor chip 11 and the connection pad peripheral region 202 for exposing the connection pad portion 127. Is formed. The solder resist 124 is formed by, for example, forming a photosensitive solder resist film on the entire first surface side of the wiring substrate 12 and performing exposure and development to thereby form the semiconductor chip mounting region 201 and the connection pad peripheral region. This can be done by removing the 202 solder resist film.

  The shape and size of the semiconductor chip mounting area 201 are preferably the same as the back surface of the semiconductor chip 11. However, in consideration of manufacturing accuracy, work accuracy, work ease, and the like, the size of the semiconductor chip mounting region 201 is slightly larger than the size of the back surface of the semiconductor chip 11 (shown by a broken line in FIG. 3). May be. The degree can be the same as the maximum error (for example, +0.1 mm) due to the alignment and mounting accuracy of the equipment used for the chip mounting operation. In any case, it is only necessary that the semiconductor chip 11 can be mounted in the semiconductor chip mounting area 201 without overlapping the inner peripheral edge of the solder resist 124 that defines the semiconductor chip mounting area 201.

  Since the connection pad peripheral region 202 is a known structure (for example, FIG. 6 of Patent Document 1), the description thereof is omitted.

  When DAF is used as the insulating adhesive 13, it is desirable that the shape and size of the DAF are also the same as the back surface of the semiconductor chip 11. However, in consideration of manufacturing accuracy, work accuracy, and the like, the size of the DAF may be slightly smaller than the size of the back surface of the semiconductor chip 11. The degree can be the same as the maximum error (for example, 0.1 mm) due to the alignment accuracy of the equipment used for the work. Further, the thickness (the amount of adhesive or resin) of the DAF is deformed or flows during heat curing after mounting the semiconductor chip 11 to absorb surface irregularities due to the connection wiring layer 122 exposed to the semiconductor chip mounting region 201. In addition, the gap between the semiconductor chip 11 and the solder resist 124 around the semiconductor chip 11 is set so as to be filled. At least, an adjustment is made so that excess adhesive does not overflow the gap between the semiconductor chip 11 and the solder resist 124 and cover the electrode pad 111 and the connection pad portion 127.

  With the above configuration, the semiconductor chip 11 (and the insulating adhesive 13) can be mounted on the semiconductor chip mounting region 201 without overlapping the solder resist 124. In this configuration, the solder resist 124 does not exist immediately below the semiconductor chip 11. Therefore, the thickness (height) of the semiconductor device 10 can be made thinner than the semiconductor device having a known structure by an amount corresponding to the thickness of the solder resist 124.

  Further, since the solder resist 124 exists around the semiconductor chip mounting region 201, when sealing with the sealing resin 15, the sealing resin 15 and the wiring substrate 12 are connected in the same manner as a known structure. Sufficient adhesion can be secured between them, and no problem arises with respect to moisture resistance.

  The insulating adhesive 13 is not limited to DAF, and for example, a die bonding paste that is a liquid adhesive having viscosity and fluidity even at a low temperature can be used. Compared with DAF, the liquid adhesive easily penetrates into gaps due to irregularities on the surface of the wiring board 12 and between the semiconductor chip 11 and the peripheral solder resist 124, and the amount can be easily adjusted and is inexpensive.

  FIG. 4 is a plan view showing a coating region of the solder resist 125 provided on the second surface of the wiring board 12. However, the land portions 126 in FIG. 4 do not have a one-to-one correspondence with the connection pad portions 127 in FIG.

  As shown in FIG. 4, the solder resist 125 covers almost the entire surface other than the land portion 126 on the second surface of the wiring board 12. This structure is the same as the known structure, and the effect of preventing the metal wiring from peeling or scratching by the solder resist 125 is not different from the known structure.

  Next, warpage occurring in the semiconductor device 10 will be described.

  In general, the linear expansion coefficient α of the solder resist is larger than that of other members such as the substrate core portion 121 and the sealing resin 15 of the wiring substrate 12, and the expansion and contraction during heating and cooling is larger than that of other members. For this reason, if the solder resist is in close contact with other members, there is a risk of warping. The wiring board 12 is also warped because the first and second solder resists 124 and 125 are provided on both the first and second surfaces. However, due to the recent thinning of the wiring board 12, the influence of the entire expansion and contraction on the sealing resin 15 is greater than the warp generated in the wiring board 12 character. That is, the covering area ratio and the thickness ratio of the first solder resist 124 and the second solder resist 125 on the wiring board 12 do not significantly affect the warp of the semiconductor device 10, and the expansion and contraction of the wiring board 12 as a whole is caused by the semiconductor. The device 10 has been warped. That is, as the total amount of the first and second solder resists 124 and 125 increases, the semiconductor device 10 is more likely to be warped during heating and cooling, and the total amount of the first and second solder resists 124 and 125 is reduced. This contributes to a reduction in warpage of the semiconductor device 10.

  In this embodiment, as is apparent from FIGS. 3 and 4, the total amount of the solder resists 124 and 125 is reduced by making the semiconductor chip mounting region 201 an uncovered region that is not covered with the solder resist 124. By limiting the semiconductor chip mounting area 201, which is an uncovered area, to an area immediately below the semiconductor chip 11 (or a slightly larger area), various inconveniences due to the absence of the solder resist 124 in that area. Prevent occurrence.

  Hereinafter, suppression of warpage of the semiconductor device 10 will be described based on simulation. The warp generated in the semiconductor device 10 includes not only the first and second solder resists 124 and 125 but also the arrangement and structure of other components, physical properties such as glass transition temperature and Young's modulus of each member, and heating conditions. It depends on. The simulation was performed in consideration of these points.

  First, the semiconductor device 10 was modeled as shown in FIG. The semiconductor device 10 is different from the semiconductor device 10 in that the bonding wire 14 is not present, the first solder resist 124 is also provided in the connection pad peripheral region 202 on the first surface side of the wiring substrate 12, and the wiring substrate 12. The land portion 126 does not exist on the second surface side, and the solder resist 125 is provided on the entire surface. Further, the insulating adhesive 13 is DAF.

  An example of the dimensions of main parts is shown in Table 1. The dimensions of these portions are based on a thin package for PoP (package on package) stacking.

  In addition, Table 2 shows an example of main physical property values of the material of each part. In Table 2, the linear expansion coefficient α1 is a typical value at a temperature lower than the glass transition temperature Tg, and α2 is a typical value at a temperature higher than Tg. Note that physical property values not listed in the table, for example, Young's modulus of the substrate core 121, and the like were also used in the simulation.

  As shown in Table 2, the solder resist has a linear expansion coefficient of about 60 to 130 ppm, a glass transition temperature of about 100 ° C., and has a larger linear expansion coefficient than that of the sealing resin (resin) and the substrate core part. The transition temperature is low. Since a material with a larger coefficient of thermal expansion at a specific temperature causes a larger expansion and contraction due to heating, the solder resist has a larger expansion and contraction due to heat than the resin or the substrate core, and if the solder resist is adjacent to another member, the difference in contraction Warpage occurs due to. Therefore, if the total amount (thickness and covering area) of the solder resist having a large linear expansion coefficient is reduced, it is considered that the amount of warpage caused by heat can be suppressed. However, the purpose of covering the solder resist is to ensure insulation, improve the peeling strength of the metal plating part that forms the land and connection wiring, and prevent scratches and dirt, so reduce the total amount of solder resist It is necessary to take care not to cause any problems. In the present embodiment, the occurrence of problems due to the reduction of the total amount of solder resist is prevented by limiting the uncovered area of the solder resist to the area immediately below the semiconductor chip (semiconductor chip mounting area).

  For the above model, the amount of warpage generated in the semiconductor device was simulated by a stress analysis tool using a finite element method. The temperature condition was lowered from 175 ° C. to 25 ° C. assuming a cooling temperature change after the mold baking operation. The amount of warpage was defined as the amount of change in the center surface up and down with respect to the straight line connecting the left and right ends on the upper surface of the semiconductor device (upward direction in the figure). In this simulation, the warpage amount in the initial state was ignored, and the warpage amount was obtained using the warpage amount at 175 ° C. as a reference (= 0).

  Table 3 shows the result of simulation by changing the covering state of the first solder resist 124 on the wiring board 12 in the model.

  The ratio of the amount of solder resist in Table 3 was the ratio of the amount of first solder resist 124 to the amount of second solder resist 125. The basic structure is obtained by forming first and second solder resists 124 and 125 having the same thickness on the entire surface (No. 2).

  As shown in Table 3, in the basic structure (No. 2), the warp amount is 72 μm plus warp (the center is convex). As can be understood from Table 1, the thickness d2 of the wiring board 12 (from the first solder resist 124 to the second solder resist 125) is 0.14 mm, and the total thickness d1 = 0 of the semiconductor device 10 This is because the shrinkage during cooling is concentrated on the lower side of the semiconductor device 10 because it is only 37% of .38 mm and is biased to the lower side of the semiconductor device 10.

  FIG. 6 is a graph showing the simulation results of Table 3.

  As understood from the graph of FIG. 6, the warp tends to increase if the amount of the first solder resist 124 on the wiring board 12 is large, and decreases if the amount of the first solder resist 124 is small. The warpage amount of the structure (No. 4) according to the present embodiment is 9 μm, which is greatly reduced compared to the warpage amount 72 μm of the basic structure (No. 2).

  In addition, No. on the graph. Looking at the left and right of the point 4, if 50% or more of the semiconductor chip mounting area 201 is an uncovered area that is not covered with a solder resist, it is equivalent to the case where the entire semiconductor chip mounting area 201 is an uncovered area. A warp reduction effect is obtained. Further, even if the uncovered area is slightly wider than the semiconductor chip mounting area 201, the warp reduction effect is also expected.

  In the graph, the amount of warpage does not decrease uniformly (linearly) as the amount of solder resist decreases. For example, no. 3 or No. The point 5 is greatly deviated from the assumed linear function line. This is presumably because the structure of the simulation model is that the semiconductor chip and DAF are arranged in the center. That is, the semiconductor chip, DAF, and the sealing resin are not uniformly arranged from the central portion to the peripheral portion, the semiconductor chip and the DAF are biased toward the central portion, and the sealing resin is thin in the central portion. This is thought to be because it is thick.

  From the above simulation results, it can be seen that the warpage of the semiconductor device 10 can be reduced by reducing the amount of the first solder resist 124 of the wiring board 12.

  As described above, according to the present embodiment, it is possible to achieve both reduction in thickness of a semiconductor device and reduction in warpage caused by heating and cooling during manufacturing. As the warpage is reduced, it is possible to improve yield, improve product reliability, and improve external mountability.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made. That is, the present invention can be applied to any semiconductor device having a structure in which a solder resist is provided on both front and back surfaces and a semiconductor chip mounted on one surface of the wiring substrate and sealed with a sealing resin. It is. As such semiconductor devices, there are semiconductor devices of LGA (Land Grid Array) type and MCP (Multi-chip Package) type.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Wiring board 13 Insulating adhesive 14 Bonding wire 15 Sealing resin 16 External connection terminal 111 Electrode pad 112 Circuit formation surface 113 Back surface 121 Substrate core part 122,123 Connection wiring layer 124 1st solder resist 125 Second solder resist 126 Land portion 127 Connection pad portion 128 Through-via 201 Semiconductor chip mounting region 202 Connection pad peripheral region

Claims (9)

A semiconductor chip;
A wiring board provided with a first solder resist on a semiconductor chip mounting surface on which the semiconductor chip is mounted;
A sealing resin for sealing the semiconductor chip mounted on the semiconductor chip mounting surface;
With
2. A semiconductor device according to claim 1, wherein an area of the semiconductor chip mounting surface where the semiconductor chip is mounted is an uncovered area where the first solder resist is not provided.   2. The semiconductor device according to claim 1, wherein the size of the uncovered region is the same as or slightly larger than a surface of the semiconductor chip facing the wiring substrate.   The semiconductor device according to claim 2, wherein a surface of the semiconductor chip that faces the wiring substrate is a surface opposite to a circuit formation surface.   The semiconductor device according to claim 3, wherein the semiconductor chip is bonded to the semiconductor chip mounting surface using an insulating adhesive.   5. The semiconductor device according to claim 4, wherein the semiconductor chip is bonded to the semiconductor chip mounting surface using the insulating adhesive without overlapping the first solder resist.   6. The semiconductor device according to claim 1, wherein the first solder resist is provided in a region of the semiconductor chip mounting surface excluding a region where the semiconductor chip is mounted and a region where the connection pad portion is exposed. The semiconductor device according to claim 1.   The second solder resist is provided in a region excluding a region where a connection land portion is formed on a surface opposite to the semiconductor chip mounting surface of the wiring board. Semiconductor device.   The semiconductor device according to claim 7, wherein the second solder resist is provided so as to have the same thickness by using the same material as the first solder resist.   2. The sealing resin according to claim 1, wherein the sealing resin has an outer peripheral surface coinciding with an edge of the wiring board and has a uniform height in a thickness direction of the wiring board. The semiconductor device according to claim 8.

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