JP2010531501A5 - - Google Patents

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Publication number
JP2010531501A5
JP2010531501A5 JP2010513903A JP2010513903A JP2010531501A5 JP 2010531501 A5 JP2010531501 A5 JP 2010531501A5 JP 2010513903 A JP2010513903 A JP 2010513903A JP 2010513903 A JP2010513903 A JP 2010513903A JP 2010531501 A5 JP2010531501 A5 JP 2010531501A5
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JP
Japan
Prior art keywords
memory module
data
mode
data access
access command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2010513903A
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English (en)
Japanese (ja)
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JP4824126B2 (ja
JP2010531501A (ja
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Publication date
Priority claimed from US11/769,001 external-priority patent/US7822936B2/en
Application filed filed Critical
Publication of JP2010531501A publication Critical patent/JP2010531501A/ja
Publication of JP2010531501A5 publication Critical patent/JP2010531501A5/ja
Application granted granted Critical
Publication of JP4824126B2 publication Critical patent/JP4824126B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010513903A 2007-06-27 2008-06-25 コマンド・データ・レプリケーションをサポートする高容量メモリ・サブシステム用メモリ・チップ Expired - Fee Related JP4824126B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/769,001 2007-06-27
US11/769,001 US7822936B2 (en) 2007-06-27 2007-06-27 Memory chip for high capacity memory subsystem supporting replication of command data
PCT/EP2008/058082 WO2009000857A1 (en) 2007-06-27 2008-06-25 Memory chip for high capacity memory subsystem supporting replication of command data

Publications (3)

Publication Number Publication Date
JP2010531501A JP2010531501A (ja) 2010-09-24
JP2010531501A5 true JP2010531501A5 (enExample) 2011-09-01
JP4824126B2 JP4824126B2 (ja) 2011-11-30

Family

ID=39791330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010513903A Expired - Fee Related JP4824126B2 (ja) 2007-06-27 2008-06-25 コマンド・データ・レプリケーションをサポートする高容量メモリ・サブシステム用メモリ・チップ

Country Status (8)

Country Link
US (1) US7822936B2 (enExample)
EP (1) EP2160687B1 (enExample)
JP (1) JP4824126B2 (enExample)
KR (1) KR101107349B1 (enExample)
CN (1) CN101681322B (enExample)
AT (1) ATE479947T1 (enExample)
DE (1) DE602008002436D1 (enExample)
WO (1) WO2009000857A1 (enExample)

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US9123409B2 (en) 2009-06-11 2015-09-01 Micron Technology, Inc. Memory device for a hierarchical memory architecture
US9117496B2 (en) 2012-01-30 2015-08-25 Rambus Inc. Memory device comprising programmable command-and-address and/or data interfaces
US8788748B2 (en) 2012-03-22 2014-07-22 International Business Machines Corporation Implementing memory interface with configurable bandwidth
CN103150006A (zh) * 2013-03-25 2013-06-12 西安华芯半导体有限公司 Dram存储器的省电方法
US9324389B2 (en) * 2013-05-29 2016-04-26 Sandisk Technologies Inc. High performance system topology for NAND memory systems
US9728526B2 (en) 2013-05-29 2017-08-08 Sandisk Technologies Llc Packaging of high performance system topology for NAND memory systems
WO2014193592A2 (en) * 2013-05-29 2014-12-04 Sandisk Technologies Inc. High performance system topology for nand memory systems
US9703702B2 (en) * 2013-12-23 2017-07-11 Sandisk Technologies Llc Addressing auto address assignment and auto-routing in NAND memory network
CN104268121B (zh) * 2014-09-23 2017-08-11 浪潮(北京)电子信息产业有限公司 超大规模芯片中访问寄存器的方法及系统
TWI588658B (zh) 2015-10-20 2017-06-21 旺宏電子股份有限公司 I/o匯流排共用記憶體系統
US9841922B2 (en) * 2016-02-03 2017-12-12 SK Hynix Inc. Memory system includes a memory controller

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US5893927A (en) * 1996-09-13 1999-04-13 International Business Machines Corporation Memory device having programmable device width, method of programming, and method of setting device width for memory device
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
JP2002063791A (ja) * 2000-08-21 2002-02-28 Mitsubishi Electric Corp 半導体記憶装置およびメモリシステム
US6493250B2 (en) * 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
DE10318603B4 (de) * 2003-04-24 2005-03-10 Infineon Technologies Ag Eingangsempfängerschaltung
US20040243769A1 (en) * 2003-05-30 2004-12-02 Frame David W. Tree based memory structure
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
JP4741226B2 (ja) * 2003-12-25 2011-08-03 株式会社日立製作所 半導体メモリモジュール、およびメモリシステム
US7216196B2 (en) * 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7188219B2 (en) * 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
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