WO2016202114A1 - 一种数据传输方法、装置及存储介质 - Google Patents

一种数据传输方法、装置及存储介质 Download PDF

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Publication number
WO2016202114A1
WO2016202114A1 PCT/CN2016/081038 CN2016081038W WO2016202114A1 WO 2016202114 A1 WO2016202114 A1 WO 2016202114A1 CN 2016081038 W CN2016081038 W CN 2016081038W WO 2016202114 A1 WO2016202114 A1 WO 2016202114A1
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Prior art keywords
packet
address
module
data
indication information
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PCT/CN2016/081038
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English (en)
French (fr)
Inventor
戴仁林
娄本刚
王平
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深圳市中兴微电子技术有限公司
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Publication of WO2016202114A1 publication Critical patent/WO2016202114A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Definitions

  • the present invention relates to the field of data transmission, and in particular, to a data transmission method, apparatus, and storage medium based on a Peripheral Component Interconnect Express (PCIe) protocol bus.
  • PCIe Peripheral Component Interconnect Express
  • the PCIe protocol bus is a third-generation high-performance interface bus. It is a packet-based serial connection protocol that provides high-speed, high-bandwidth, high-performance, high-scalability, hot-swappable, point-to-point Point, dual simplex, serial differential signal links to interconnect devices. Moreover, it has been widely used in the interconnection of peripheral devices in the field of computers and electronic communications.
  • PCIe protocol bus in the field of communication, there have been many different types, such as: Advanced Extensible Interface (AXI) based on PCIe protocol bus; Host Adaptation Interface (HAL); Patented PCIE-based CPU (CPU) Device and Method for Accessing Local Bus (Patent No.: CN201310528347.9) A method for implementing CPU access registers by PCIe; Patent "Method, Device and System for Transmitting Messages on PCIE Bus" (Patent No.: CN201110032172.3) A method for transmitting protocol packets from a PCIe initiating device to a destination device by means of identification (ID) routing; etc., but these prior art techniques are based on a specific application such as a single Implement CPU access registers or transport protocol messages.
  • AXI Advanced Extensible Interface
  • HAL Host Adaptation Interface
  • Patented PCIE-based CPU (CPU) Device and Method for Accessing Local Bus Patent No.: CN201310528
  • embodiments of the present invention are directed to a data transmission method, apparatus, and storage medium, which can simultaneously implement a CPU read/write access register and a data message based on a PCIe bus in a direct memory access (DMA) mode. Two-way transmission.
  • An embodiment of the present invention provides a data transmission method, based on an enhanced peripheral interconnecting a PCIe protocol bus, where the method is applied to a controller, where the controller includes a first working module, a second working module, and a third working. a module and a fourth working module, the method comprising:
  • the data packet is allocated to the first work module, and the first work module parses the data packet to obtain a read operation command, and sends the read operation command to the target device. Receiving read data returned by the target device, and sending the read data to the peer device;
  • the data packet is allocated to the second work module, and when the second work module parses the data packet to obtain a write operation command, the write operation command in the data packet is Sending to the target device, receiving a write operation completion signal returned by the target device;
  • the second working module parses the data packet to obtain a direct storage access DMA read operation command, starts the third working module, and sends the DMA read operation command to the third working module, the third work
  • the module obtains the sending packet in the peer device according to the DMA read operation command, and sends the sent packet to the target device.
  • the fourth working module When the second working module parses the data packet to obtain a DMA write operation command, the fourth working module is started, and the DMA write operation command is sent to the fourth working module, and the fourth working module is configured according to the The DMA write operation command sends the received message sent by the target device to the peer device.
  • the first working module parses the data packet to obtain a read operation command, sends the read operation command to the target device, receives read data returned by the target device, and sends the read data to the pair.
  • End devices including:
  • the first working module parses the data packet to obtain a CPU read operation command, and then converts the CPU read operation command into one or more general-purpose register read operation access commands; wherein the CPU read operation command includes a read enable, Read the initial address, the number of read data, the general register read Operation access commands include read enable and read address;
  • the first working module buffers the one or more general register read operation access commands into the first asynchronous first in first out buffer FIFO;
  • the first asynchronous FIFO in the first working module converts the timing of the one or more general register read operation access commands into a timing conforming to the target device, and reads the one or more general-purpose registers after the conversion
  • An access command is sent to the target device through a configuration channel;
  • a general register read operation access command is used by the target device to perform a read operation to obtain read data;
  • the second asynchronous FIFO in the first working module receives the read data through a configuration channel, and converts the read data into a TLP packet structure form and timing that meets a PCIe protocol requirement; and sends the converted read data to Peer device.
  • the second asynchronous FIFO of the first working module generates the invalid read data by itself when the read data sent by the target device is not received within the first preset time.
  • the write operation command in the data packet is sent to the target device, and the write operation completion signal returned by the target device is received, including:
  • the second working module parses the data packet to obtain a CPU write operation command, and then converts the CPU write operation command into one or more general-purpose register write operation access commands; wherein the CPU write operation command includes a write enable, Writing data, writing an initial address, and writing a number of data, the general-purpose register write operation access command includes a write enable, a write address, and a single write data corresponding to the write address;
  • the second working module buffers the one or more general register write operation access commands into the third asynchronous FIFO;
  • the third asynchronous FIFO in the second working module converts the timing of the one or more general-purpose register write operation access commands to meet the timing of the target device, and writes the one or more general-purpose registers after the conversion
  • the access command is sent to the target device through the configuration channel;
  • the general register write operation access command is used by the target device to write a single write data corresponding to the write address at a write address;
  • the second working module receives a write operation completion signal sent by the target device through a configuration channel.
  • the second working module when the second working module does not receive the write operation completion signal sent by the target device in the second preset time, the second working module generates the write operation completion signal by itself.
  • the DMA read operation command includes an initial address and an address space size of the packet sending indication information
  • the third working module obtains the sending packet in the peer device according to the DMA read operation command.
  • Sending the sent packet to the target device includes:
  • the third working module sends the address of the packet sending indication information to the peer device according to the DMA read operation command; wherein the address of the packet sending indication information is the packet sending indication information.
  • the initial address +i-1,i is an integer greater than or equal to 1;
  • the third working module receives the packet sending indication information content in the address of the packet sending indication information sent by the peer device, where the packet sending indication information content includes the packet sending effective indication information and the packet The size and address of the initial buffer of the message;
  • the third working module sends the packet size and the initial buffer address of the packet to the peer device when the packet sending valid indication information is valid;
  • the third working module receives the sending message corresponding to the packet size and the initial buffer address of the packet sent by the peer device;
  • the third working module buffers the sent message into the fourth asynchronous FIFO, and after being converted by the timing conversion and the data bit width, converted into a packet of the general packet structure form, and sent to the target device through the DMA channel;
  • the third working module sends a message sending completion command to the peer device, where the message sending completion command is used by the peer device to send valid indication information of the packet corresponding to the sending packet. Change to invalid;
  • the above steps are sequentially performed until the address of the packet transmission indication information exceeds the address range defined by the initial address and the address space size of the packet transmission indication information.
  • the DMA write operation command includes an initial address and an address space size of the packet receiving indication information
  • the fourth working module sends the received packet sent by the target device to the pair according to the DMA write operation command.
  • End devices including:
  • the fourth working module sends the address of the packet receiving indication information to the peer device according to the DMA write operation command; wherein the address of the packet receiving indication information is the packet receiving indication information.
  • the initial address +j-1,j is an integer greater than or equal to 1;
  • the fourth working module receives the packet receiving indication information content in the address of the packet receiving indication information sent by the peer device, where the packet receiving indication information content includes the packet receiving effective indication information, and the receiving report The initial cache address of the text;
  • the fifth asynchronous FIFO of the fourth working module converts the received message in the form of a general packet structure sent by the target device into a buffer, a timing conversion, and a data bit width conversion, and then converts into a TLP packet structure form and timing conforming to the PCIe protocol requirement.
  • the fourth working module sends the initial buffer address of the received message and the message data packet outputted from the fifth asynchronous FIFO to the peer device; the receiving The initial buffer address of the packet is used by the peer device to buffer the packet data packet from the initial buffer address of the received packet;
  • the fourth working module peer device sends a message receiving completion command, where the message receiving completion command is used by the peer device to change the packet receiving valid indication information corresponding to the initial buffer address of the packet data packet to invalid;
  • the above steps are sequentially performed in sequence until the address of the message receiving indication information exceeds the address range defined by the initial address and the address space size of the message receiving indication information.
  • Embodiments of the present invention also provide a data transmission apparatus, which is based on an enhanced peripheral interconnect PCIe a protocol bus, the device includes: a receiving module, an allocating module, a first working module, a second working module, a third working module, and a fourth working module, wherein
  • a receiving module configured to receive a data packet sent by the peer device, where the data packet carries a work type flag bit
  • An allocating module configured to allocate the data packet to the first working module when the working type flag received by the receiving module is indicated as a read operation
  • the first working module is configured to, when parsing the data packet allocated by the allocating module, obtain the read operation command, send the read operation command to the target device, receive the read data returned by the target device, and read the read data Data is sent to the peer device;
  • the allocating module is further configured to allocate the data packet to the second working module when the working type flag bit received by the receiving module is represented as a write operation;
  • the second working module is configured to, when parsing the data packet allocated by the allocating module, obtain a write operation command, send a write operation command in the data packet to the target device, and receive a write operation returned by the target device Complete signal
  • the second working module is further configured to: when the data packet is parsed to obtain a direct storage access DMA read operation command, start the third working module, and send the DMA read operation command to the third working module ;
  • the third working module is configured to obtain, according to the DMA read operation command sent by the second working module, a sending message in the peer device, and send the sending message to a target device;
  • the second working module is further configured to: when parsing the data packet to obtain a DMA write operation command, start the fourth working module, and send the DMA write operation command to the fourth working module;
  • the fourth working module is configured to send the received packet sent by the target device to the peer device according to the DMA write operation command sent by the second working module.
  • the first working module includes: a first processing module, a first asynchronous first in first out buffer FIFO module and a second asynchronous FIFO module;
  • the first processing module is configured to parse the data packet to obtain a CPU read operation command, and then convert the CPU read operation command into one or more general register read operation access commands; wherein the CPU read operation command includes reading Enabling, reading an initial address, reading a number of data, the general register read operation access command includes a read enable, a read address;
  • the first processing module is further configured to cache the one or more general register read operation access commands into the first asynchronous first in first out buffer FIFO module;
  • the first asynchronous FIFO module is configured to convert a timing of one or more general register read operation access commands buffered by the first processing module to a timing conforming to a target device, and to convert the one or more after conversion a general register read operation access command is sent to the target device through a configuration channel; a general register read operation access command is used by the target device to perform a read operation to obtain read data;
  • the second asynchronous FIFO module is configured to receive the read data through a configuration channel, and convert the read data into a TLP packet structure form and timing that meets a PCIe protocol requirement; and send the converted read data to the peer end device.
  • the first asynchronous FIFO module is further configured to generate invalid read data by itself when the read data sent by the target device is not received within the first preset time.
  • the second working module includes: a second processing module, and a third asynchronous FIFO module;
  • the second processing module is configured to parse the data packet to obtain a CPU write operation command, and then convert the CPU write operation command into one or more general-purpose register write operation access commands; wherein the CPU write operation command includes writing
  • the general register write operation access command includes a write enable, a write address, and a single write data corresponding to the write address; enabling, writing data, writing an initial address, and writing a number of data;
  • the second processing module is further configured to buffer the one or more general-purpose register write operation access commands into the third asynchronous FIFO module;
  • the third asynchronous FIFO module is configured to convert a timing of the one or more general-purpose register write operation access commands buffered by the second processing module to a timing conforming to a target device, and to convert the one or a plurality of general-purpose register write operation access commands are sent to the target device through a configuration channel; a general-purpose register write operation access command is used by the target device to write a single write data corresponding to the write address at a write address;
  • the second processing module is further configured to receive a write operation completion signal sent by the target device by using a configuration channel.
  • the second processing module is further configured to generate the write operation completion signal when the write operation completion signal sent by the target device is not received within the second preset time.
  • the DMA read operation command includes an initial address and an address space size of the packet sending indication information
  • the third working module includes a third processing module and a fourth asynchronous FIFO module.
  • the third processing module is configured to, according to the DMA read operation command, send an address of the packet sending indication information to the peer device according to the DMA read operation command, where the address of the packet sending indication information is a packet sending indication
  • the initial address of the information +i-1, i is an integer greater than or equal to 1; the address of the message transmission indication information does not exceed the address range defined by the initial address and the address space size of the message transmission indication information.
  • the third processing module is further configured to receive the packet sending indication information content in the address of the packet sending indication information that is sent by the peer device, where the packet sending indication information content includes the packet sending effective indication information, The message size and the address of the initial buffer of the message;
  • the third processing module is further configured to send the packet size and the initial buffer address of the packet to the peer device when the valid sending information of the packet is valid;
  • the third processing module is further configured to receive the packet size and the report sent by the peer device Sending a message corresponding to the initial buffer address, and buffering the sent message into the fourth asynchronous FIFO module.
  • the fourth asynchronous FIFO module is configured to convert the sent message buffered by the third processing module into a general packet structure form message after being subjected to timing conversion and data bit width conversion, and sent to the target device through the DMA channel;
  • the third processing module is further configured to: after the fourth asynchronous FIFO module sends the sent packet to the target device, send a message sending completion command to the peer device, where the message sending completion command is used for the The peer device changes the valid indication information for sending the packet corresponding to the sent packet to invalid.
  • the DMA write operation command includes an initial address and an address space size of the packet receiving indication information
  • the fourth working module includes: a fourth processing module and a fifth asynchronous FIFO module, where
  • the fourth processing module is configured to send the address of the packet receiving indication information to the peer device according to the DMA write operation command, where the address of the packet receiving indication information is a packet.
  • Receiving the initial address of the indication information +j-1, j is an integer greater than or equal to 1; the address of the packet receiving indication information does not exceed the address range defined by the initial address and the address space size of the packet receiving indication information;
  • the fourth processing module is further configured to receive the packet receiving indication information content in the address of the packet receiving indication information sent by the peer device, where the packet receiving indication information content includes a packet receiving valid indication Information, the initial cache address of the received message;
  • the fifth asynchronous FIFO module is configured to perform buffering, timing conversion, and data bit width conversion on the received packet in the form of a general packet structure sent by the target device, and then convert the packet into a TLP packet structure form and timing report conforming to the PCIe protocol requirement.
  • Text packet
  • the fourth processing module is further configured to: when the message receiving valid indication information is valid, the initial buffer address of the received message and the message output by the fifth asynchronous FIFO module
  • the data packet is sent to the peer device; the initial buffer address of the received packet is used by the peer device to buffer the packet data packet from the initial buffer address of the received packet;
  • the fourth processing module is further configured to send a message receiving completion command to the peer device, where the message receiving completion command is used by the peer device to receive the packet corresponding to the initial buffer address of the packet data packet.
  • the valid indication changed to invalid.
  • the embodiment of the present invention further provides a computer storage medium storing a computer program configured to execute the above data transmission method of the embodiment of the present invention.
  • two or more working modules in the controller can work at the same time, so that a CPU read and write access register operation can be realized simultaneously based on a PCIe bus link.
  • the data message is transmitted bidirectionally in DMA mode, which also greatly simplifies the PCIe bus device or system, and has the characteristics of flexible application and diversity; in addition, one controller can simultaneously support one or more target devices, and has very Good scalability.
  • FIG. 1 is a schematic flowchart of a data transmission method based on a PCIe protocol bus according to Embodiment 1 of the present invention
  • FIG. 2 is a block diagram of a system architecture based on a PCIe protocol bus according to Embodiment 2 of the present invention
  • FIG. 3 is a schematic flowchart of a first data transmission method according to Embodiment 2 of the present invention.
  • FIG. 4 is a schematic flowchart of a second data transmission method according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic flowchart diagram of a third data transmission method according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic flowchart diagram of a fourth data transmission method according to Embodiment 2 of the present invention.
  • FIG. 7 is a structural block diagram of a data transmission apparatus based on a PCIe protocol bus according to Embodiment 3 of the present invention.
  • FIG. 8 is a structural block diagram of a first working module according to Embodiment 3 of the present invention.
  • FIG. 9 is a structural block diagram of a second working module according to Embodiment 3 of the present invention.
  • FIG. 10 is a structural block diagram of a third working module according to Embodiment 3 of the present invention.
  • FIG. 11 is a structural block diagram of a fourth working module according to Embodiment 3 of the present invention.
  • An embodiment of the present invention provides a data transmission method, where the method is applied to a controller based on a PCIe protocol bus, where the controller includes a first working module, a second working module, a third working module, and a fourth working module.
  • the processing procedure of the method in this embodiment includes the following steps:
  • Step 101 Receive a data packet sent by the peer device, where the data packet carries a work type flag bit.
  • the method in this embodiment is a data transmission method between the peer device and the target device.
  • the main transmission types are CPU read, CPU write, DMA read, and DMA write; the data packet sent by the peer device to the controller carries the work type.
  • the flag bit is used to make the controller distinguish the type of work, and then apply different modules for data processing.
  • Step 102 When the work type flag is indicated as a read operation, assign the data packet to the first working module.
  • Step 103 The first working module parses the data packet to obtain a read operation command, sends the read operation command to a target device, receives read data returned by the target device, and sends the read data to the peer end. device.
  • the first working module is configured to process the read operation data packet sent by the peer device, and the read operation data packet carries a read operation command, and the read operation command indicates the address that requires the target device to perform the read operation, and the controller will After the read operation command is forwarded to the target device, the target device will be based on the target device.
  • the read operation command reads the data at the corresponding address to obtain the read data, and then forwards the read data to the controller, and the controller forwards the read data to the peer device, which completes a read operation.
  • Step 104 When the work type flag is indicated as a write operation, assign the data packet to the second work module.
  • Step 105 When the second working module parses the data packet to obtain a write operation command, the write operation command in the data packet is sent to the target device, and the write operation completion signal returned by the target device is received.
  • the second working module is configured to process the write operation data packet sent by the peer device, and the write operation data packet carries a write operation command, and the write operation command indicates the address and the write data that require the target device to perform the write operation.
  • the target device After the second working module forwards the write operation command to the target device, the target device writes the write data to the corresponding address according to the write operation command, and then sends a write operation completion signal to the second working module, and the second working module determines to receive the After the write operation completion signal, it is determined whether the next write operation command can be sent to the target device.
  • data transmission between two devices is performed according to an adapted data format, and format conversion can be performed to convert the data into an adapted format.
  • Step 106 When the second working module parses the data packet to obtain a DMA read operation command, start the third working module, and send the DMA read operation command to the third working module.
  • Step 107 The third working module obtains a sending message in the peer device according to the DMA read operation command, and sends the sent message to the target device.
  • the data packet is allocated to the second work module, and when the second work module parses the data packet to obtain a DMA read operation command, the third work module is started. Sending the DMA read operation command to the third working module.
  • the third working module obtains a sending message that the peer device sends to the target device according to the information exchange between the DMA read operation command and the peer device, and then the third working module sends the obtained sending message to the target. device.
  • Step 108 When the second working module parses the data packet to obtain a DMA write operation command, the fourth working module is started, and the DMA write operation command is sent to the fourth working module.
  • Step 109 The fourth working module sends the received packet sent by the target device to the peer device according to the DMA write operation command.
  • the data packet is allocated to the second work module, and when the second work module parses the data packet to obtain a DMA read operation command, the fourth work module is started. And sending the DMA read operation command to the fourth working module.
  • the fourth working module obtains a cache address allocated by the peer device to the received message according to the information exchange between the DMA write operation command and the peer device, and then the received packet sent by the target device is obtained by the third working module.
  • the device forwards the packet to the peer device, so that the peer device caches the received packet in the cache address allocated to the received packet.
  • the steps 102-103 and the steps 104-105 are not divided into sequential steps, and the steps 105, 106-107 and 108-109 are also not in the order, and the controller only selects the working module according to the content of the data packet.
  • the above steps are not divided into sequential steps, and the steps 105, 106-107 and 108-109 are also not in the order, and the controller only selects the working module according to the content of the data packet.
  • two or more working modules in the controller can work at the same time, so that based on a PCIe bus link, the method in this embodiment can simultaneously perform CPU read and write access register operations and data messages to DMA.
  • the two-way transmission which also greatly simplifies a PCIe bus device or system, and has the characteristics of flexible application diversity; and in the method of the embodiment, one of the controllers can simultaneously support one or more of the target devices. Has very good scalability.
  • An embodiment of the present invention provides a data transmission method based on a PCIe protocol bus.
  • the method is based on the PCIe link system architecture shown in FIG. 2.
  • the PCIe link system includes a peer device 201. , protocol layer device 202, controller 203, target device 204; wherein
  • the peer device 201 can generate a CPU read operation command and a CPU write operation command; a cache space having a message receiving indication information and a message sending indication information; and a cache space for buffering the received message and the sent message;
  • the link system operates as a PCIe root device, a switching device, or an endpoint device; and the protocol layer device 202 performs high-speed, multi-bandwidth point-to-point communication of information through a PCIe link (ie, a high-speed serial bus SerDes).
  • the protocol layer device 202 is designed to implement the functions and requirements of the PCIe protocol layer such that the device operates as a PCIe endpoint device throughout the PCIe link system. It has a high speed serial (SerDes) interface and a transaction layer packet (TLP) interface, wherein the SerDes interface is interconnected and data interacted with the peer device 201, and the TLP interface is interconnected with the controller 203 and data. Interaction.
  • SerDes serial
  • TLP transaction layer packet
  • the controller 203 includes a first working module, a second working module, a third working module, and a fourth working module.
  • the controller 203 executes the CPU read by the peer device 201 through the protocol layer device 202 through the first working module.
  • the operating command is executed by the second working module to execute the CPU write operation command sent by the peer device 201 through the protocol layer device 202; the second working module and the third working module cooperate to execute the peer device 201 through the protocol layer device.
  • the DMA write operation command sent by the 202 cooperates with the DMA read operation command sent by the peer device 201 through the protocol layer device 202 through the second working module and the fourth working module.
  • the controller 203 is provided with a configuration channel interface and a DMA channel interface.
  • the channel interface is configured to send and receive CPU read and write commands
  • the DMA channel interface is used to send and receive DMA read and write commands.
  • Target device 204 includes, but is not limited to, at least one of a configuration channel interface and a DMA channel interface that conforms to controller 203.
  • the controller 203 can Data communication with one or more of the target devices 204.
  • the channel connected between the controller 203 and the target device 204 through the configuration channel interface is a configuration channel
  • the channel connected between the controller 203 and the target device 204 through the DMA channel interface is a DMA channel
  • the configuration channel is used for transmitting CPU read and write operations.
  • Data, DMA channel is used to transmit DMA read and write operations.
  • the peer device and the protocol layer device perform data interaction through a high-speed serial bus SerDes, and the data form is a PCIe protocol packet; the protocol layer device and the controller exchange data through respective TLP interfaces.
  • the data format is a TLP packet; the protocol layer device can convert the PCIe protocol packet sent by the peer device into a TLP packet and then forward it to the controller, or convert the TLP packet sent by the controller into a PCIe protocol packet and forward the packet to the peer device.
  • a method for the peer device to perform CPU access read data from the target device, where the first working module of the controller works, and the processing procedure of the method includes the following steps:
  • Step 301 The peer device generates a CPU read operation command, and the CPU read operation command constitutes a PCIe protocol packet and sends the protocol to the protocol layer device through the high speed serial bus SerDes.
  • the assembled PCIe protocol packet is provided with a work type flag bit, and the work type flag bit is indicated as a read operation.
  • Step 302 The protocol layer device converts the PCIe protocol packet into a TLP packet, and sends the packet to the controller through the TLP interface.
  • the TLP packet is also referred to as a package of memory read or IO read commands in the PCIe protocol.
  • a work type flag bit is set on the TLP packet, and the work type flag bit is represented as a read operation.
  • Step 303 The controller allocates a TLP packet whose work type flag is a read operation to the first working module, where the first working module parses the received TLP packet, and then converts the parsed CPU read operation command into one Or multiple general-purpose register read operations to access commands.
  • the CPU read operation command includes a read enable, a read initial address, and a read data number;
  • the general register read operation access command includes a read enable and a read address; assuming that the read initial address is N,
  • the first working module parses the CPU read operation command, and converts the CPU read operation command into 10 general register read operation access commands: (read enable, read address N), (Read enable, read address N+1)... (Read enable, read address N+9).
  • Step 304 The first working module buffers the one or more general register read operation access commands into the first asynchronous first in first out buffer FIFO.
  • Step 305 The first asynchronous FIFO in the first working module converts the timing of the one or more general register read operation access commands into a timing conforming to the target device, and converts the one or more generals after the conversion.
  • a register read operation access command is sent to the target device through a configuration channel.
  • the first asynchronous FIFO in the first working module sends the one or more general register read operation access commands to the target device through a configuration channel interface.
  • Step 306 The target device performs a read operation according to the one or more general-purpose register read operation access commands, obtains read data, and sends the read data to the first working module through the configuration channel.
  • Step 307 The second asynchronous FIFO in the first working module receives the read data through a configuration channel, and converts the read data into a TLP packet structure form and timing that meets a PCIe protocol requirement; and the converted read Data is sent to the peer device through the protocol layer device.
  • the converted read data may be sent to the The protocol layer device, the protocol layer device sends the read data to the peer device through the high speed serial bus SerDes, thus completing the operation of the peer device to read data from the target device.
  • TLP packet packet structure form
  • the second asynchronous FIFO in the first working module does not receive the read address returned by the target device from the configuration channel within a first preset time (this first preset time may be manually configured according to actual conditions)
  • the read data indicates that the configuration channel is faulty or the target device is out. Now fault, etc., then a self-testing process.
  • the second asynchronous FIFO in the first working module automatically generates an invalid read data, and converts the invalid read data into a TLP packet structure form and timing that meets the requirements of the PCIe protocol, and then sends the data through the protocol layer device.
  • the peer device decides whether to read the data corresponding to the address again by reading the data again, or does not read the data corresponding to the address.
  • the method for writing data to the target device is performed by the peer device, where the second working module of the controller works, and the processing procedure of the method includes the following steps:
  • Step 401 The peer device generates a CPU write operation command, and the CPU write operation command is formed into a PCIe protocol packet and sent to the protocol layer device through the high speed serial bus SerDes.
  • the assembled PCIe protocol packet is provided with a work type flag bit, and the work type flag bit is represented as a write operation.
  • Step 402 The protocol layer device converts the PCIe protocol packet into a TLP packet, and sends the packet to the controller through the TLP interface.
  • the TLP packet is also referred to as a package of memory write or IO write commands in the PCIe protocol.
  • a work type flag is set on the TLP packet, and the work type flag is indicated as a write operation.
  • Step 403 The controller allocates a TLP packet whose work type flag is a write operation to a second working module, where the second working module parses the received TLP packet, and then converts the parsed CPU write operation command into one Or multiple general-purpose register write operations to access commands.
  • the CPU write operation command includes a write enable, a write data, an write initial address, and a write data number; and the general register write operation access command includes a write enable, a write address, and a single write data corresponding to the write address.
  • the controller parses the CPU write operation command and converts the CPU write operation command into 10 general-purpose register write operation access commands: (write enable, Write address N, write data 1), (write enable, write address N+1, write data 2)... (write enable, write address N+9, write data 10).
  • Step 404 The second working module writes the one or more general-purpose register access operations Cache into the third asynchronous FIFO.
  • Step 405 The third asynchronous FIFO in the second working module converts the timing of the one or more general-purpose register write operation access commands into a timing conforming to the target device, and converts the one or more generals after the conversion.
  • a register write access command is sent to the target device through a configuration channel.
  • the third asynchronous FIFO of the second working module sends the one or more general register write operation access commands to the target device through a configuration channel interface.
  • Step 406 The target device performs a write operation according to the one or more general-purpose register write operation access commands, and sends a write operation completion signal to the second work module after the write operation is completed.
  • Step 407 The second working module receives the write operation completion signal.
  • the second working module does not receive the write operation completion signal returned by the target device from the configuration channel within the second preset time (this second preset time can be artificially configured according to the actual situation), it indicates that the configuration channel is configured. A fault occurs or the target device fails, etc., a self-testing process. At this time, the second working module automatically generates a write operation completion signal, so that the second working module sends the next write operation command to the target device.
  • the method for transmitting the message stored in the peer device to the target device by means of DMA reading, the second working module and the third working module of the controller work in the method, and the processing flow of the method Includes the following steps:
  • Step 501 The peer device generates a CPU write operation command, and the CPU write operation command is formed into a PCIe protocol packet and sent to the protocol layer device through the high speed serial bus SerDes.
  • the assembled PCIe protocol packet is provided with a work type flag bit, and the work type flag bit is represented as a write operation.
  • Step 502 The protocol layer device converts the PCIe protocol packet into a TLP packet, and sends the packet to the controller through the TLP interface.
  • the TLP packet is also referred to as a package of memory write or IO write commands in the PCIe protocol.
  • Turn A work type flag bit is set on the replaced TLP packet, and the work type flag bit is represented as a write operation.
  • Step 503 The controller allocates a TLP packet whose work type flag is a write operation to a second working module, where the second working module parses the received TLP packet to obtain a DMA read operation command, and then starts the third working module. Sending the DMA read operation command to the third working module.
  • the DMA read operation command includes a DMA read operation command, where the DMA read operation command includes an initial address and an address space size of the message sending indication information, where the DMA read operation command is used to instruct the controller to enable the third working module. .
  • the initial address and the address space of the packet sending indication information are used to indicate the address of the packet sending indication information in the cache space.
  • Step 504 The third working module sends the address of the packet sending indication information to the peer device by using the protocol layer device.
  • the controller assembles the address of the packet sending indication information into a TLP packet and sends it to the protocol layer device through the TLP interface, and then the protocol layer device converts the TLP packet into a PCIe protocol packet and sends it to the pair through the high speed serial bus. End device.
  • the peer device has a buffer space for transmitting the indication information of the packet and a buffer space for sending the packet, and the initial address and the address space of the packet sending indication information are used to indicate that the packet sending indication information is in the cache space. address.
  • the address of the packet sending indication information sent by the third working module for the first time is the initial address of the packet sending indication information.
  • Step 505 The peer device sends the indication information content of the packet in the address of the packet sending indication information to the third working module by using the protocol layer device.
  • the peer device After receiving the address of the packet sending indication information, the peer device sends the content of the packet sending indication information corresponding to the address to the third working module in the buffer space of the buffering packet sending indication information.
  • the message sending indication information content includes a message sending effective indication information, a message The size and address of the message's initial cache.
  • Step 506 When the packet sending valid indication information is valid, the third working module sends the packet size and the initial buffer address of the packet to the peer device through the protocol layer device.
  • the size of the packet and the address of the initial buffer of the packet may determine the address of the packet.
  • the valid indication information of the packet is valid, it indicates that the packet needs to be sent in the address, and the controller will size the packet.
  • the address of the initial buffer of the message is sent to the peer device through the protocol layer device, and the conversion of the data form during the transmission is referred to the above description.
  • the controller repeatedly repeats the foregoing process until the sending indication information sent by the peer device is valid.
  • Step 507 The peer device obtains the sending packet according to the packet size and the initial buffer address of the packet, and sends the obtained sending packet to the third working module by using the protocol layer device.
  • Step 508 The third working module buffers the sent message into the fourth asynchronous FIFO, and after being converted by the timing conversion and the data bit width, is converted into a general packet structure form message, and is sent to the target device through the DMA channel.
  • the general packet structure of the message mainly includes the header (SOP), the end of packet (EOP), the contents of the packet (DATA), the packet indicator (the valid indicator VALID, the error indicator ERROR, and the last beat DATA byte number MOD). ), as well as information such as back pressure status (FC).
  • the DATA minimum bit width is 8 bits, and may have an integer multiple of 8 times. The data width can be converted according to the bit width of the message in the target device, converted into an appropriate data bit width, and then sent to Target device.
  • Step 509 The third working module sends a packet sending completion command to the peer device by using the protocol layer device, where the packet sending completion command is used to change the valid sending information of the packet corresponding to the sent packet to be invalid. .
  • the third working module After the sending, by the third working module, the sending packet to the target device, the sending packet corresponding to the sending packet does not need to be sent to the target device, and the packet corresponding to the sent packet is received.
  • the valid indication information is still valid.
  • the third working module needs to send a message sending completion command to the peer device, where the message sending completion command is used to instruct the peer device to send the packet corresponding to the sent packet.
  • the indication changed to invalid.
  • the controller After the address of the packet sending indication information is started from the initial address, after the packet corresponding to the initial address is sent to the target address according to the foregoing steps 504-509, the controller automatically sends the initial address of the packet sending indication information. If the value is incremented by 1, the process proceeds to steps 504-509, and after the completion of the process, the process is performed. Steps 504-509 are performed until the initial address of the packet sending indication information and the address space size defined by the step 503 are exceeded. Indicates the address of the message.
  • the method for transmitting the packet in the target device to the cache of the peer device by means of DMA write in the method, the second working module and the third working module of the controller work, the method
  • the processing flow includes the following steps:
  • Step 601 The peer device generates a CPU write operation command, and the CPU write operation command is formed into a PCIe protocol packet and sent to the protocol layer device through the high speed serial bus SerDes.
  • the assembled PCIe protocol packet is provided with a work type flag bit, and the work type flag bit is represented as a write operation.
  • Step 602 The protocol layer device converts the PCIe protocol packet into a TLP packet, and sends the packet to the controller through the TLP interface.
  • the TLP packet is also referred to as a package of memory write or IO write commands in the PCIe protocol.
  • the converted TLP packet is provided with a work type flag bit, and the work type flag bit is represented as a write operation.
  • Step 603 The controller allocates a TLP packet whose work type flag is a write operation to a second working module, where the second working module parses the received TLP packet to obtain a DMA write operation command, and then starts the fourth working module. Sending the DMA write operation command to the fourth working module.
  • the CPU write operation command includes a DMA write start instruction, and the message receives the indication information.
  • the initial address and the address space size of the packet receiving indication information are used to indicate that the packet receives the address indicating the information in the buffer space.
  • Step 604 The fourth working module sends the address of the packet receiving indication information to the peer device by using the protocol layer device.
  • the fourth working module assembles the address of the packet receiving indication information into a TLP packet and sends the TLP packet to the protocol layer device through the TLP interface, and then the protocol layer device converts the TLP packet into a PCIe protocol packet and sends the packet through the high speed serial bus. Give the peer device.
  • the peer device has a buffer space for receiving the message and a buffer space for receiving the message, and the initial address and the address space of the packet receiving indication information are used to indicate that the packet receiving indication information is in the cache space. address.
  • the address of the packet receiving indication information sent by the fourth working module for the first time is the initial address of the packet receiving indication information.
  • Step 605 The peer device sends the content of the packet receiving indication information in the address of the packet receiving indication information to the fourth working module by using the protocol layer device.
  • the peer device After receiving the address of the packet receiving indication information, the peer device sends the content of the packet receiving indication information corresponding to the address to the controller in the buffer space of the buffering packet receiving indication information.
  • the message receiving indication information content includes a message receiving valid indication information, and an initial cache address of the received message.
  • Step 606 The fifth asynchronous FIFO of the fourth working module converts the received packet in the form of a general packet structure sent by the target device into a TLP packet structure conforming to the PCIe protocol after being cached, time-series converted, and converted into a data bit width. And timing message packets.
  • the target device may send the received message to the fourth module of the controller through the DMA channel, and the fifth asynchronous FIFO of the fourth working module may buffer, time series and data bit width of the packet in the form of a general packet structure sent by the target device. After the conversion, it is converted into a packet data packet conforming to the TLC packet structure form and timing required by the PCIe protocol. What needs to be explained here is when the fourth working module When the cache in the fifth asynchronous FIFO is full, the fourth working module can notify the target device that the received message is no longer sent.
  • Step 607 When the message receiving valid indication information is valid, the controller sends the initial buffer address of the received message and the packet data packet in the form of a TLP packet output from the fifth asynchronous FIFO to the protocol layer device. Peer device.
  • the initial buffer address of the received packet is the initial address of the packet received by the peer device, and the received packet is valid when the valid indication information is valid, and the received packet can be buffered.
  • the fourth working module sends the initial buffer address of the received message and the packet data packet in the form of a TLP packet outputted from the fifth asynchronous FIFO to the peer device through the protocol layer device, and the data format conversion reference in the transmission process Described above.
  • the controller repeatedly repeats the foregoing process until the receiving indication information sent by the peer device is valid.
  • Step 608 The peer device caches a packet data packet from an initial buffer address of the received packet.
  • Step 609 The fourth working module sends a message receiving completion command to the peer device by using the protocol layer device, where the message receiving completion command is used by the peer device to correspond to the initial buffer address of the packet data packet.
  • the message receiving valid indication information is changed to invalid.
  • the peer device buffers the packet data packet from the initial buffer address of the received packet.
  • the buffer address corresponding to the initial buffer address of the text packet is occupied, and the valid indication information of the packet corresponding to the address is still valid.
  • the fourth working module needs to send a message receiving completion command to the peer device.
  • the message receiving completion command is used to instruct the peer device to change the packet receiving valid indication information corresponding to the initial buffer address of the packet data packet to be invalid.
  • the address of the message receiving indication information is started from the initial address, and after the received message is cached to the initial address according to the foregoing steps 604-609, the fourth working module will send the message.
  • the initial address of the receiving indication information is automatically incremented by one, and the steps 604-609 are continued, and then 1 is added after the completion, and the steps 604-609 are performed cyclically until the address of the packet receiving indication information exceeds the report parsed in step 603.
  • the text receives the initial address of the indication information and the address range of the message transmission and reception information defined by the size of the address space.
  • two or more working modules in the controller can work at the same time, so that the method in this embodiment can simultaneously perform CPU read/write access register operations and data message bidirectional based on a PCIe bus link.
  • Transmission which also greatly simplifies a PCIe bus device or system, and has the characteristics of flexible application diversity; and in the method of this embodiment, one of the controllers can simultaneously support one or more of the target devices, which is very good. Scalability.
  • the bidirectional transmission of the data message is performed in the DMA mode, and the DMA mode needs to control the switch enable and determine the data buffer space size and the data initial address by the CPU write operation.
  • the query and control DMA operations are implemented by the message sending and receiving indication information, and self-query, self-control, error or failure retransmission of data transmission, self-polling of the message transmission indication information space, and the like are implemented.
  • the embodiment of the present invention provides a data transmission apparatus, based on an enhanced peripheral interconnecting PCIe protocol bus.
  • the apparatus includes: a receiving module 701, an allocating module 702, a first working module 703, and a second a working module 704, a third working module 705, and a fourth working module 706, wherein
  • the receiving module 701 is configured to receive a data packet sent by the peer device, where the data packet carries a work type flag bit;
  • the allocating module 702 is configured to allocate the data packet to the first working module when the working type flag received by the receiving module 701 is indicated as a read operation;
  • the first working module 703 is configured to, when parsing the data packet allocated by the allocating module 702, obtain the read operation command, send the read operation command to the target device, receive the read data returned by the target device, and The read data is sent to the peer device;
  • the allocating module 702 is further configured to allocate the data packet to the second working module when the working type flag bit received by the receiving module 701 is represented as a write operation;
  • the second working module 704 is configured to, when parsing the data packet allocated by the allocating module 702, obtain a write operation command, send a write operation command in the data packet to the target device, and receive the return of the target device.
  • Write operation completion signal
  • the second working module 704 is further configured to: when parsing the data packet to obtain a DMA read operation command, start the third working module 705, and send the DMA read operation command to the third working module 705 ;
  • the third working module 705 is configured to obtain the sending message in the peer device according to the DMA read operation command sent by the second working module 704, and send the sending message to the target device;
  • the second working module 704 is further configured to: when parsing the data packet to obtain a DMA write operation command, start the fourth working module 706, and send the DMA write operation command to the fourth working module 706 ;
  • the fourth working module 706 is further configured to send the received packet sent by the target device to the peer device according to the DMA write operation command sent by the second working module 704.
  • the first working module 703 includes: a first processing module 7031, a first asynchronous first in first out buffer FIFO module 7032, and a second asynchronous FIFO module 7033;
  • the first processing module 7031 is configured to parse a data packet to obtain a CPU read operation command, and then convert the CPU read operation command into one or more general-purpose register read operation access commands; wherein the CPU read operation command includes Read enable, read initial address, read data, The general register read operation access command includes a read enable and a read address;
  • the first processing module 7031 is further configured to cache the one or more general-purpose register read operation access commands into the first asynchronous first-in first-out buffer FIFO module 7032;
  • the first asynchronous FIFO module 7032 is configured to convert a timing of one or more general register read operation access commands buffered by the first processing module 7031 into a timing conforming to a target device;
  • the first processing module 7031 is further configured to send the one or more general register read operation access commands converted by the first asynchronous FIFO module 7032 to the target device through a configuration channel;
  • the command is used by the target device to perform a read operation to obtain read data;
  • the second asynchronous FIFO is configured to receive the read data through a configuration channel, and convert the read data into a TLP packet structure form and timing that meets a PCIe protocol requirement;
  • the first processing module 7031 is configured to send the read data converted by the second asynchronous FIFO module 7033 to the peer device.
  • the first asynchronous FIFO module is further configured to generate invalid read data by itself when the read data sent by the target device is not received within the first preset time.
  • the second working module 704 includes: a second processing module 7041, and a third asynchronous FIFO module 7042; wherein
  • the second processing module 7041 is configured to parse the data packet to obtain a CPU write operation command, and then convert the CPU write operation command into one or more general-purpose register write operation access commands; wherein the CPU write operation command includes Write enable, write data, write initial address, write data number, the general register write operation access command includes a write enable, a write address, and a single write data corresponding to the write address;
  • the second processing module 7041 is further configured to buffer the one or more general-purpose register write operation access commands into the third asynchronous FIFO module 7042;
  • the third asynchronous FIFO module 7042 is configured to convert a timing of the one or more general-purpose register write operation access commands buffered by the second processing module 7041 into a timing conforming to a target device;
  • the second processing module 7041 is further configured to send the one or more general-purpose register write operation access commands converted by the third asynchronous FIFO module 7042 to the target device through a configuration channel;
  • the command is used by the target device to write a single write data corresponding to the write address at a write address;
  • the second processing module 7041 is further configured to receive, by using a configuration channel, a write operation completion signal sent by the target device.
  • the second processing module is further configured to generate the write operation completion signal when the write operation completion signal sent by the target device is not received within the second preset time.
  • the DMA read operation command includes an initial address and an address space size of the message sending indication information; as shown in FIG. 10, the third working module 705 includes a third processing module 7051 and a fourth asynchronous FIFO module 7052; wherein
  • the third processing module 7051 is configured to, when the i-th time, send the address of the packet sending indication information to the peer device according to the DMA read operation command, where the address of the packet sending indication information is the packet sending
  • the initial address of the indication information +i-1,i is an integer greater than or equal to 1; the address of the packet transmission indication information does not exceed the address range defined by the initial address and the address space size of the packet transmission indication information.
  • the third processing module 7051 is further configured to receive the packet sending indication information content in the address of the packet sending indication information sent by the peer device, where the packet sending indication information content includes the packet sending effective indication information , the packet size and the address of the initial buffer of the message;
  • the third processing module 7051 is further configured to: when the packet sending valid indication information is valid, send the packet size and the initial buffer address of the packet to the peer device;
  • the third processing module 7051 is further configured to receive the size of the packet sent by the peer device Sending a packet corresponding to the initial buffer address of the packet, and buffering the sent packet into the fourth asynchronous FIFO module 7052;
  • the fourth asynchronous FIFO module 7052 is configured to convert the sent message buffered by the third processing module 7051 into a general packet structure form message after being subjected to timing conversion and data bit width conversion, and sent to the target through the DMA channel. device;
  • the third processing module 7051 is further configured to: after the fourth asynchronous FIFO module 7052 sends the sent message to the target device, send a message sending completion command to the peer device, where the message sending completion command is used for The peer device changes the valid indication information for sending the packet corresponding to the sent packet to be invalid.
  • the DMA write operation command includes an initial address and an address space size of the packet receiving indication information.
  • the fourth working module 706 includes: a fourth processing module 7061 and a fifth.
  • Asynchronous FIFO module 7062 wherein
  • the fourth processing module 7061 is configured to send, according to the DMA write operation command, an address of the packet receiving indication information to the peer device at the jth time; wherein the address of the packet receiving indication information is a report
  • the initial address of the text receiving indication information +j-1, j is an integer greater than or equal to 1; the address of the packet receiving indication information does not exceed the address range defined by the initial address of the packet receiving indication information and the size of the address space;
  • the fourth processing module 7061 is further configured to receive the packet receiving indication information content in the address of the packet receiving indication information sent by the peer device, where the packet receiving indication information content includes the packet receiving effective Indication information, initial buffer address of the received message;
  • the fifth asynchronous FIFO module 7062 is configured to perform buffering, timing conversion, and data bit width conversion on the received packet in the form of a general packet structure sent by the target device, and then convert to a TLP packet structure form and timing conforming to the PCIe protocol requirement.
  • the fourth processing module 7061 is further configured to: when the message receiving valid indication information is valid, the initial buffer address of the received message and the fifth asynchronous FIFO module 7062 The output packet data packet is sent to the peer device; the initial buffer address of the received packet is used by the peer device to buffer the packet data packet from the initial buffer address of the received packet;
  • the fourth processing module 7061 is further configured to send a message receiving completion command to the peer device, where the message receiving completion command is used by the peer device to forward the packet corresponding to the initial buffer address of the packet data packet. Receive valid indication information changed to invalid.
  • the receiving module 701, the assigning module 702, the first working module 703, the second working module 704, the third working module 705, and the fourth working module 706 may be configured by a central processing unit (CPU) located on the controller, Implemented by a microprocessor (MPU), digital signal processor (DSP), or field programmable gate array (FPGA).
  • CPU central processing unit
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA field programmable gate array
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the device is implemented in a flow chart A function specified in a block or blocks of a process or multiple processes and/or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the controller receives the data packet sent by the peer device, where the data packet carries the work type flag bit; when the work type flag bit indicates the read operation, the data packet is allocated to the first working module.
  • the first working module parses the data packet to obtain a read operation command, sends the read operation command to a target device, receives read data returned by the target device, and sends the read data to the peer device;
  • the work type flag bit is indicated as a write operation, the data packet is allocated to the second work module, and when the second work module parses the data packet to obtain a write operation command, the write operation command in the data packet is sent Receiving, by the target device, a write operation completion signal returned by the target device; when the second working module parses the data packet to obtain a direct storage access DMA read operation command, starting the third working module, and using the DMA read operation command Sending to the third working module, the third working module obtains a sending message in the peer device according to the DMA read operation command, and the Sending a message to the
  • the two-way transmission is performed by DMA, which greatly simplifies the PCIe bus device or system, and has the characteristics of flexible application and diversity; in addition, one controller can support one or more target devices at the same time, which is very good. Scalability.

Abstract

一种数据传输方法、装置及存储介质，基于增强型外设互连(PCIe)协议总线，所述方法应用于控制器（203），所述控制器（203）中包括第一工作模块（703）、第二工作模块（704）、第三工作模块（705）和第四工作模块（706），所述方法包括：接收对端设备（201）发送的数据包，根据数据包的内容，由所述第一工作模块（703）处理读操作命令，所述第二工作模块（704）处理写操作命令；所述第三工作模块（705）处理直接存储访问(DMA)读操作命令；所述第四工作模块（706）处理DMA写操作命令。

Description

一种数据传输方法、装置及存储介质 技术领域
本发明涉及数据传输领域，尤其涉及一种基于增强型外设互连(PCIe，Peripheral Component Interconnect express)协议总线的数据传输方法、装置及存储介质。
背景技术
PCIe协议总线是第三代高性能接口总线，属于一种基于数据包的串行连接协议，它提供高速的、高带宽的、高性能的、高扩展性的、可热插拔的、点到点的、双单工的、串行差分信号链路来互联设备。并且，已经被广泛应用于计算机和电子通信领域的外围设备互连上。
基于PCIe协议总线在通信领域的应用，已出现了很多不同的类型，比如：基于PCIe协议总线的高级可扩展接口(AXI)；主机适配接口(HAL)；专利《基于PCIE协议的中央处理器(CPU)访问本地总线的装置及方法》(专利号：CN201310528347.9)阐述的一种通过PCIe实现CPU访问寄存器的方法；专利《在PCIE总线上传输报文的方法、设备和系统》(专利号：CN201110032172.3)阐述的一种以标识(ID)路由的方式从PCIe起始设备传输协议报文到目的设备的方法；等等，但这些已有技术都是基于某一个特定应用如单一实现CPU访问寄存器或者传输协议报文。
发明内容
有鉴于此，本发明实施例期望提供一种数据传输方法、装置及存储介质，可以基于一条PCIe总线同时实现CPU读写访问寄存器和数据报文以直接存储访问(DMA，Direct Memory Access)方式进行双向传输。
为达到上述目的，本发明的技术方案是这样实现的：
本发明实施例提供了一种数据传输方法，基于增强型外设互连PCIe协议总线，所述方法应用于控制器，所述控制器中包括第一工作模块、第二工作模块、第三工作模块和第四工作模块，所述方法包括：
接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；
在工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块，所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；
在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块，所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；
所述第二工作模块解析所述数据包获得直接存储访问DMA读操作命令时，启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块，所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备；
所述第二工作模块解析所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块，所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
上述方案中，所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备，包括：
所述第一工作模块解析数据包获得CPU读操作命令，然后将所述CPU读操作命令转换为一个或多个通用寄存器读操作访问命令；其中，所述CPU读操作命令中包括读使能、读初始地址、读数据个数，所述通用寄存器读 操作访问命令包括读使能、读地址；
第一工作模块将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO中；
所述第一工作模块中的第一异步FIFO将所述一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备；通用寄存器读操作访问命令用于所述目标设备进行读操作获得读数据；
所述第一工作模块中的第二异步FIFO通过配置通道接收所述读数据，并将所述读数据转换为符合PCIe协议要求的TLP包结构形式和时序；并将转换后的读数据发送给对端设备。
上述方案中，所述第一工作模块的第二异步FIFO在第一预设时间内未接收到所述目标设备发送的读数据时，自行生成无效读数据。
上述方案中，所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号，包括：
所述第二工作模块解析数据包获得CPU写操作命令，然后将所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令；其中，所述CPU写操作命令中包括写使能、写数据、写初始地址、写数据个数，所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据；
第二工作模块将所述一个或多个通用寄存器写操作访问命令缓存到第三异步FIFO中；
所述第二工作模块中的第三异步FIFO将所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备； 通用寄存器写操作访问命令用于所述目标设备在写地址写入所述写地址对应的单个写数据；
所述第二工作模块通过配置通道接收所述目标设备发送的写操作完成信号。
上述方案中，所述第二工作模块在第二预设时间内未接收到所述目标设备发送的写操作完成信号时，所述第二工作模块自行生成所述写操作完成信号。
上述方案中，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备，包括：
在第i次时，所述第三工作模块根据所述DMA读操作命令将报文发送指示信息的地址发送给对端设备；其中，所述报文发送指示信息的地址为报文发送指示信息的初始地址+i-1，i为大于等于1的整数；
所述第三工作模块接收对端设备发送的所述报文发送指示信息的地址中的报文发送指示信息内容；其中，所述报文发送指示信息内容包括报文发送有效指示信息、报文大小和报文初始缓存的地址；
所述第三工作模块在所述报文发送有效指示信息为有效时，将所述报文大小和报文初始缓存地址发送给对端设备；
所述第三工作模块接收所述对端设备发送的所述报文大小和报文初始缓存地址对应的发送报文；
所述第三工作模块将所述发送报文缓存到第四异步FIFO中，经过时序转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备；
所述第三工作模块向对端设备发送报文发送完成命令，所述报文发送完成命令用于所述对端设备将所述发送报文对应的报文发送有效指示信息 更改为无效；
依次循环进行上述步骤，直至所述报文发送指示信息的地址超出所述报文发送指示信息的初始地址和地址空间大小限定的地址范围。
上述方案中，所述DMA写操作命令中包括报文接收指示信息的初始地址和地址空间大小；所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备，包括：
在第j次时，所述第四工作模块根据所述DMA写操作命令将报文接收指示信息的地址发送给对端设备；其中，所述报文接收指示信息的地址为报文接收指示信息的初始地址+j-1，j为大于等于1的整数；
所述第四工作模块接收对端设备发送的所述报文接收指示信息的地址中的报文接收指示信息内容；其中，所述报文接收指示信息内容包括报文接收有效指示信息、接收报文的初始缓存地址；
所述第四工作模块的第五异步FIFO将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包；
在所述报文接收有效指示信息为有效时，所述第四工作模块将所述接收报文的初始缓存地址以及从第五异步FIFO输出的报文数据包发送给对端设备；所述接收报文的初始缓存地址用于所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包；
所述第四工作模块对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效；
依次循环进行上述步骤，直至所述报文接收指示信息的地址超出所述报文接收指示信息的初始地址和地址空间大小限定的地址范围。
本发明实施例还提供了一种数据传输装置，基于增强型外设互连PCIe 协议总线，所述装置包括：接收模块，分配模块，第一工作模块、第二工作模块、第三工作模块和第四工作模块，其中，
接收模块，配置为接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；
分配模块，配置为在所述接收模块接收到的工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块；
所述第一工作模块，配置为在解析出所述分配模块分配的数据包获得读操作命令时，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；
分配模块，还配置为在所述接收模块接收到的工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块；
所述第二工作模块，配置为在解析出所述分配模块分配的所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；
所述第二工作模块，还配置为在解析所述数据包获得直接存储访问DMA读操作命令时，启动所述第三工作模块，并将所述DMA读操作命令发送给所述第三工作模块；
所述第三工作模块，配置为根据所述第二工作模块发送的所述DMA读操作命令获得所述对端设备中的发送报文，并将所述发送报文发送给目标设备；
所述第二工作模块，还配置为在解析出所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块；
所述第四工作模块，配置为根据所述第二工作模块发送的所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
上述方案中，所述第一工作模块中包括：第一处理模块，第一异步先入先出缓存器FIFO模块和第二异步FIFO模块；其中，
所述第一处理模块，配置为解析数据包获得CPU读操作命令，然后将所述CPU读操作命令转换为一个或多个通用寄存器读操作访问命令；其中，所述CPU读操作命令中包括读使能、读初始地址、读数据个数，所述通用寄存器读操作访问命令包括读使能、读地址；
所述第一处理模块，还配置为将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO模块中；
所述第一异步FIFO模块，配置为将所述第一处理模块缓存的一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备；通用寄存器读操作访问命令用于所述目标设备进行读操作获得读数据；
所述第二异步FIFO模块，配置为通过配置通道接收所述读数据，并将所述读数据转换为符合PCIe协议要求的TLP包结构形式和时序；并将转换后的读数据发送给对端设备。
上述方案中，所述第一异步FIFO模块，还配置为在第一预设时间内未接收到所述目标设备发送的读数据时，自行生成无效读数据。
上述方案中，所述第二工作模块中包括：第二处理模块，第三异步FIFO模块；其中，
所述第二处理模块，配置为解析数据包获得CPU写操作命令，然后将所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令；其中，所述CPU写操作命令中包括写使能、写数据、写初始地址、写数据个数，所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据；
所述第二处理模块，还配置为将所述一个或多个通用寄存器写操作访问命令缓存到第三异步FIFO模块中；
所述第三异步FIFO模块，配置为将所述第二处理模块缓存的所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备；通用寄存器写操作访问命令用于所述目标设备在写地址写入所述写地址对应的单个写数据；
所述第二处理模块，还配置为通过配置通道接收所述目标设备发送的写操作完成信号。
上述方案中，所述第二处理模块，还配置为在第二预设时间内未接收到所述目标设备发送的写操作完成信号时，生成所述写操作完成信号。
上述方案中，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；所述第三工作模块包括第三处理模块和第四异步FIFO模块；其中，
第三处理模块，配置为在第i次时，根据所述DMA读操作命令将报文发送指示信息的地址发送给对端设备；其中，所述报文发送指示信息的地址为报文发送指示信息的初始地址+i-1，i为大于等于1的整数；所述报文发送指示信息的地址不超出所述报文发送指示信息的初始地址和地址空间大小限定的地址范围。
第三处理模块，还配置为接收对端设备发送的所述报文发送指示信息的地址中的报文发送指示信息内容；其中，所述报文发送指示信息内容包括报文发送有效指示信息、报文大小和报文初始缓存的地址；
第三处理模块，还配置为在所述报文发送有效指示信息为有效时，将所述报文大小和报文初始缓存地址发送给对端设备；
第三处理模块，还配置为接收所述对端设备发送的所述报文大小和报 文初始缓存地址对应的发送报文，并将所述发送报文缓存到第四异步FIFO模块中。
所述第四异步FIFO模块，配置为在将所述第三处理模块缓存的发送报文经过时序转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备；
第三处理模块，还配置为在所述第四异步FIFO模块将所述发送报文发送给目标设备后，向对端设备发送报文发送完成命令，所述报文发送完成命令用于所述对端设备将所述发送报文对应的报文发送有效指示信息更改为无效。
上述方案中，所述DMA写操作命令中包括报文接收指示信息的初始地址和地址空间大小；所述第四工作模块包括：第四处理模块和第五异步FIFO模块，其中，
所述第四处理模块，配置为在第j次时，根据所述DMA写操作命令将报文接收指示信息的地址发送给对端设备；其中，所述报文接收指示信息的地址为报文接收指示信息的初始地址+j-1，j为大于等于1的整数；所述报文接收指示信息的地址未超出所述报文接收指示信息的初始地址和地址空间大小限定的地址范围；
所述第四处理模块，还配置为接收对端设备发送的所述报文接收指示信息的地址中的报文接收指示信息内容；其中，所述报文接收指示信息内容包括报文接收有效指示信息、接收报文的初始缓存地址；
所述第五异步FIFO模块，配置为将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包；
所述第四处理模块，还配置为在所述报文接收有效指示信息为有效时，将所述接收报文的初始缓存地址以及所述第五异步FIFO模块输出的报文 数据包发送给对端设备；所述接收报文的初始缓存地址用于所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包；
所述第四处理模块，还配置为向对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质存储有计算机程序，该计算机程序配置为执行本发明实施例的上述数据传输方法。
本发明实施例提供的数据传输方法、装置及存储介质，控制器中两个或两个以上的工作模块可以同时工作，这样，基于一条PCIe总线链路，可以实现同时进行CPU读写访问寄存器操作和数据报文以DMA方式进行双向传输，从而也大大简化了PCIe总线设备或系统，具有应用灵活多样性的特点；另外，一个所述控制器可以同时支持一个或一个以上的目标设备，具有非常好的扩展性。
附图说明
图1为本发明实施例1提供的一种基于PCIe协议总线的数据传输方法的流程示意图；
图2为本发明实施例2提供的基于PCIe协议总线的系统架构框图；
图3为本发明实施例2提供的第一种数据传输方法的流程示意图；
图4为本发明实施例2提供的第二种数据传输方法的流程示意图；
图5为本发明实施例2提供的第三种数据传输方法的流程示意图；
图6为本发明实施例2提供的第四种数据传输方法的流程示意图；
图7为本发明实施例3提供的一种基于PCIe协议总线的数据传输装置的结构框图；
图8为本发明实施例3提供的第一工作模块的结构框图；
图9为本发明实施例3提供的第二工作模块的结构框图；
图10为本发明实施例3提供的第三工作模块的结构框图；
图11为本发明实施例3提供的第四工作模块的结构框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
实施例1
本发明实施例提供了一种数据传输方法，所述方法基于PCIe协议总线，应用于控制器，所述控制器中包括第一工作模块、第二工作模块、第三工作模块和第四工作模块，如图1所示，本实施例方法的处理流程包括以下步骤：
步骤101、接收对端设备发送的数据包，所述数据包上携带有工作类型标志位。
本实施例方法是对端设备与目标设备的之间的数据传输方法，主要传输类型有CPU读、CPU写、DMA读、DMA写；对端设备发送给控制器的数据包上携带有工作类型标志位，以使控制器区分工作类型，进而应用不同的模块进行数据处理。
步骤102、在工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块。
步骤103、所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备。
这里，第一工作模块用来处理对端设备发送来的读操作数据包，读操作数据包中会携带有读操作命令，读操作命令中会指明要求目标设备进行读操作的地址，控制器将读操作命令转发给目标设备后，目标设备会根据 读操作命令在相应地址处读取数据获得读数据，然后将读数据转发给控制器，控制器再将该读数据转发给对端设备，这就完成了一次读操作。
需要说明的是，在上述过程中，两个设备之间进行数据传输时要按照适应的数据格式进行传输，可以进行格式转换，将数据转换为适应的格式。
步骤104、在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块。
步骤105、所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号。
这里，第二工作模块用来处理对端设备发送来的写操作数据包，写操作数据包中会携带有写操作命令，写操作命令中会指明要求目标设备进行写操作的地址以及写数据，第二工作模块将写操作命令转发给目标设备后，目标设备会根据写操作命令将该写数据写到相应地址处，然后发送写操作完成信号给第二工作模块，第二工作模块决定接收到写操作完成信号后决定是否可以发送下一个写操作命令给目标设备。
在上述过程中，两个设备之间进行数据传输时要按照适应的数据格式进行传输，可以进行格式转换，将数据转换为适应的格式。
步骤106、所述第二工作模块解析所述数据包获得DMA读操作命令时，启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块。
步骤107、所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备。
这里，在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块，所述第二工作模块解析所述数据包获得DMA读操作命令时，启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块。 所述第三工作模块根据所述DMA读操作命令与对端设备进行信息交互获得对端设备要发送给目标设备的发送报文，然后第三工作模块将获得的所述发送报文发送给目标设备。
步骤108、所述第二工作模块解析所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块。
步骤109、所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
这里，在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块，所述第二工作模块解析所述数据包获得DMA读操作命令时，启动所述第四工作模块，将所述DMA读操作命令发送给所述第四工作模块。所述第四工作模块根据所述DMA写操作命令与对端设备进行信息交互获得对端设备给接收报文分配的缓存地址，然后第三工作模块将获得的所述目标设备发送的接收报文转发给对端设备，使对端设备在给接收报文分配的缓存地址缓存该接收报文。
上述过程中，步骤102-103和步骤104-105没有先后顺序之分，步骤105、步骤106-107和步骤108-109也没有先后顺序之分，控制器只是根据数据包的内容选取工作模块进行上述步骤。
本实施例方法中，控制器中两个或两个以上的工作模块可以同时工作，这样基于一条PCIe总线链路，本实施例方法可以实现同时进行CPU读写访问寄存器操作和数据报文以DMA的方式双向传输，从而也大大简化了一个PCIe总线设备或系统，也具有应用灵活多样性的特点；且本实施例方法中，一个所述控制器可以同时支持一个或一个以上所述目标设备，具有非常好的扩展性。
实施例2
本发明实施例提供了一种基于PCIe协议总线的数据传输方法，该方法是基于如图2所示的PCIe链路系统架构，如图2所示，所述PCIe链路系统包括对端设备201、协议层设备202、控制器203、目标设备204；其中，
所述对端设备201能产生CPU读操作命令和CPU写操作命令；具有报文接收指示信息和报文发送指示信息的缓存空间；具有缓存接收报文和发送报文的缓存空间；在整个PCIe链路系统中作为一个PCIe根设备、交换设备或端点设备工作；与所述协议层设备202通过PCIe链路(即：高速串行总线SerDes)进行信息的高速、多带宽的点对点通信。
协议层设备202是为了实现PCIe协议层的功能和要求，使得本设备在整个PCIe链路系统中作为一个PCIe端点设备工作。它具有一个高速串行(SerDes)接口和一个事务层包(TLP)接口，其中SerDes接口是与所述对端设备201进行互联和数据交互，TLP接口是与所述控制器203进行互联和数据交互。
控制器203中包括第一工作模块、第二工作模块、第三工作模块和第四工作模块，控制器203通过第一工作模块执行所述对端设备201通过协议层设备202发送过来的CPU读操作命令，通过第二工作模块执行所述对端设备201通过协议层设备202发送过来的CPU写操作命令；通过第二工作模块和第三工作模块协作执行所述对端设备201通过协议层设备202发送过来的DMA写操作命令，通过第二工作模块和第四工作模块协作执行所述对端设备201通过协议层设备202发送过来的DMA读操作命令。
所述控制器203上设置有配置通道接口和DMA通道接口。配置通道接口接口用于发送和接收CPU读写指令，DMA通道接口用于发送和接收DMA读写指令。
目标设备204包括但不限于具有符合所述控制器203的配置通道接口和DMA通道接口中的至少一种接口。在本实施例中，所述控制器203可以 与一个或一个以上的所述目标设备204进行数据通信。控制器203与目标设备204之间通过配置通道接口连接的通道为配置通道，控制器203与目标设备204之间通过DMA通道接口连接的通道为DMA通道，配置通道用于传输CPU读写操作的数据，DMA通道用于传输DMA读写操作的报文。
下述方法中，所述对端设备与协议层设备之间通过高速串行总线SerDes进行数据交互，数据形式为PCIe协议包；协议层设备与控制器之间通过各自的TLP接口进行数据交互，数据形式为TLP包；协议层设备可以将对端设备发送的PCIe协议包转换为TLP包后转发给控制器，或者，将控制器发送的TLP包转换为PCIe协议包后转发给对端设备。
如图3所示，为对端设备从目标设备进行CPU访问读数据的方法，所述方法中控制器的第一工作模块进行工作，该方法的处理流程包括以下步骤：
步骤301、对端设备产生CPU读操作命令，并将所述CPU读操作命令组成PCIe协议包通过高速串行总线SerDes发送给协议层设备。
组装成的PCIe协议包上设置有工作类型标志位，所述工作类型标志位表示为读操作。
步骤302、协议层设备将PCIe协议包转换成TLP包，并通过TLP接口发送给控制器。
该TLP包在PCIe协议中又称存储(memory)读或IO读命令的包。所述TLP包上设置有工作类型标志位，所述工作类型标志位表示为读操作。
步骤303、控制器将工作类型标志位为读操作的TLP包分配给第一工作模块，所述第一工作模块解析接收到的TLP包，然后将解析出的所述CPU读操作命令转换为一个或多个通用寄存器读操作访问命令。
所述CPU读操作命令中包括读使能，读初始地址，读数据个数；所述通用寄存器读操作访问命令包括读使能、读地址；假设读初始地址为N， 读数据个数10，则第一工作模块解析出所述CPU读操作命令后，会将所述CPU读操作命令转换为10个通用寄存器读操作访问命令：(读使能，读地址N)、(读使能，读地址N+1)……(读使能，读地址N+9)。
步骤304、第一工作模块将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO中。
步骤305、所述第一工作模块中的第一异步FIFO将所述一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备。
所述第一工作模块中的第一异步FIFO会通过配置通道接口将所述一个或多个通用寄存器读操作访问命令发送给所述目标设备。
步骤306、所述目标设备根据所述一个或多个通用寄存器读操作访问命令进行读操作，获得读数据，并将所述读数据通过配置通道发送给第一工作模块。
步骤307、所述第一工作模块中的第二异步FIFO通过配置通道接收所述读数据，并将所述读数据转换为符合PCIe协议要求的TLP包结构形式和时序；并将转换后的读数据通过所述协议层设备发送到所述对端设备。
所述第一工作模块中的第二异步FIFO将所述读数据转换为符合PCIe协议要求的包结构形式(TLP包)和时序后，就可以通过TLP接口将转换后的读数据发送给所述协议层设备，所述协议层设备将该读数据通过高速串行总线SerDes发送给对端设备，这样就完成了所述对端设备从目标设备读数据的操作。
如果所述第一工作模块中的第二异步FIFO在第一预设时间内(这个第一预设时间可根据实际情况人为配置)未从配置通道上接收到目标设备返回的所述读地址对应的读数据，则表明是配置通道出现故障或目标设备出 现故障等，这时一个自检测的过程。此时所述第一工作模块中的第二异步FIFO会自动产生一个无效读数据，并将该无效读数据转换为符合PCIe协议要求的TLP包结构形式和时序后，通过所述协议层设备发送到所述对端设备。所述对端设备接收到该无效读数据后，自主决定是再次进行读操作读该地址对应的数据，还是不再读该地址对应的数据。
如图4所示，为对端设备向目标设备写数据的方法，所述方法中控制器的第二工作模块进行工作，该方法的处理流程包括以下步骤：
步骤401、对端设备产生CPU写操作命令，并将所述CPU写操作命令组成PCIe协议包通过高速串行总线SerDes发送给协议层设备。
组装成的PCIe协议包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤402、协议层设备将所述PCIe协议包转换成TLP包，并通过TLP接口发送给控制器。
该TLP包在PCIe协议中又称存储(memory)写或IO写命令的包。转换成TLP包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤403、控制器将工作类型标志位为写操作的TLP包分配给第二工作模块，所述第二工作模块解析接收到的TLP包，然后将解析出的所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令。
所述CPU写操作命令中包括写使能，写数据，写初始地址，写数据个数；所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据。假设写初始地址为N，写数据个数10，则控制器解析出所述CPU写操作命令后，会将所述CPU写操作命令转换为10个通用寄存器写操作访问命令：(写使能，写地址N，写数据1)、(写使能，写地址N+1，写数据2)……(写使能，写地址N+9，写数据10)。
步骤404、第二工作模块将所述一个或多个通用寄存器写操作访问命令 缓存到第三异步FIFO中。
步骤405、所述第二工作模块中的第三异步FIFO将所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备。
所述第二工作模块中的第三异步FIFO会通过配置通道接口将所述一个或多个通用寄存器写操作访问命令发送给所述目标设备。
步骤406、所述目标设备根据所述一个或多个通用寄存器写操作访问命令进行写操作，并在写操作完成后给第二工作模块发送写操作完成信号。
步骤407、所述第二工作模块接收所述写操作完成信号。
如果所述第二工作模块在第二预设时间内(这个第二预设时间内可根据实际情况人为配置)未从配置通道上接收到目标设备返回的写操作完成信号，则表明是配置通道出现故障或目标设备出现故障等，这时一个自检测的过程。此时所述第二工作模块会自动产生一个写操作完成信号，以便第二工作模块发送下一个写操作命令给目标设备。
如图5所示，为对端设备中存储的报文以DMA读的方式传输到目标设备的方法，本方法中控制器的第二工作模块和第三工作模块进行工作，该方法的处理流程包括以下步骤：
步骤501、对端设备产生CPU写操作命令，并将所述CPU写操作命令组成PCIe协议包通过高速串行总线SerDes发送给协议层设备。
组装成的PCIe协议包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤502、协议层设备将所述PCIe协议包转换成TLP包，并通过TLP接口发送给控制器。
该TLP包在PCIe协议中又称存储(memory)写或IO写命令的包。转 换成的TLP包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤503、控制器将工作类型标志位为写操作的TLP包分配给第二工作模块，所述第二工作模块解析接收到的TLP包获得DMA读操作命令，然后启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块。
所述CPU写操作命令中包括DMA读操作命令，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；其中，DMA读操作命令用于指示控制器开启第三工作模块。所述报文发送指示信息的初始地址和地址空间大小用于指示报文发送指示信息在缓存空间中的地址。
步骤504、所述第三工作模块将报文发送指示信息的地址通过协议层设备发送给对端设备。
在传输过程中，控制器将报文发送指示信息的地址组装成TLP包通过TLP接口发送给协议层设备，再由协议层设备将该TLP包转换成PCIe协议包通过高速串行总线发送给对端设备。
所述对端设备中具有报文发送指示信息的缓存空间以及发送报文的缓存空间，所述报文发送指示信息的初始地址和地址空间大小用于指示报文发送指示信息在缓存空间中的地址。启动第三工作模块时，所述第三工作模块首次发送的报文发送指示信息的地址为报文发送指示信息的初始地址。
步骤505、所述对端设备将所述报文发送指示信息的地址中的报文发送指示信息内容，通过协议层设备发送给第三工作模块。
所述对端设备接收到报文发送指示信息的地址后，会在缓存报文发送指示信息的缓存空间中将该地址对应的报文发送指示信息内容发送给第三工作模块。所述报文发送指示信息内容包括报文发送有效指示信息、报文 大小和报文初始缓存的地址。
步骤506、在所述报文发送有效指示信息为有效时，第三工作模块将所述报文大小和报文初始缓存地址通过协议层设备发送给对端设备。
报文大小和报文初始缓存的地址可以确定报文的地址；在所述报文发送有效指示信息为有效时表明该地址内有发送报文需要发送，此时控制器将所述报文大小和报文初始缓存的地址通过协议层设备发送给对端设备，在此传输过程中数据形式的转换参考上文描述。
若所述报文发送有效指示信息为无效或不正确时，则所述控制器会反复重复上述过程，直到所述对端设备发送的所述发送指示信息为有效为止。
步骤507、对端设备根据所述报文大小和报文初始缓存地址获取发送报文，并将获取到的发送报文通过协议层设备发送给第三工作模块。
步骤508、第三工作模块将所述发送报文缓存到第四异步FIFO中，经过时序转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备。
报文的通用包结构形式，主要包含了包头(SOP)、包尾(EOP)、包内容(DATA)、包指示符(有效指示符VALID、错误指示符ERROR和最后一拍DATA字节数MOD)，以及反压状态(FC)等信息。而所述DATA最小位宽为8比特，还可具有8的整数倍的其他位宽，可以根据目标设备中报文的位宽进行数据位宽转换，转换成合适的数据位宽后再发送给目标设备。
步骤509、所述第三工作模块通过协议层设备向对端设备发送报文发送完成命令，所述报文发送完成命令用于将所述发送报文对应的报文发送有效指示信息更改为无效。
所述第三工作模块将所述发送报文发送给目标设备后，由于对端设备中该发送报文不需要再被发送给目标设备，而该发送报文对应的报文接收 有效指示信息还是有效的，此时第三工作模块就需要向对端设备发送报文发送完成命令，该报文发送完成命令用于指示对端设备将所述发送报文对应的报文发送有效指示信息更改为无效。
所述报文发送指示信息的地址是从初始地址开始，按照上述步骤504-509将该初始地址对应的报文发送给目标地址后，所述控制器会将报文发送指示信息的初始地址自动加1，继续进行步骤504-509，完成后再加1，以此循环进行步骤504-509，直至超过了步骤503解析出的报文发送指示信息的初始地址和地址空间大小限定的报文发送指示信息的地址。
如图6所示，为目标设备中的报文以DMA写的方式传输到对端设备的缓存中的方法，本方法中控制器的第二工作模块和第三工作模块进行工作，该方法的处理流程包括以下步骤：
步骤601、对端设备产生CPU写操作命令，并将所述CPU写操作命令组成PCIe协议包通过高速串行总线SerDes发送给协议层设备。
组装成的PCIe协议包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤602、协议层设备将所述PCIe协议包转换成TLP包，并通过TLP接口发送给控制器。
该TLP包在PCIe协议中又称存储(memory)写或IO写命令的包。转换成的TLP包上设置有工作类型标志位，所述工作类型标志位表示为写操作。
步骤603、控制器将工作类型标志位为写操作的TLP包分配给第二工作模块，所述第二工作模块解析接收到的TLP包获得DMA写操作命令，然后启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块。
所述CPU写操作命令中包括DMA写启动指令，报文接收指示信息的 初始地址和地址空间大小；其中，DMA写操作命令用于指示控制器开启第四工作模块。所述报文接收指示信息的初始地址和地址空间大小用于指示报文接收指示信息在缓存空间中的地址。
步骤604、第四工作模块将报文接收指示信息的地址通过协议层设备发送给对端设备。
在传输过程中，第四工作模块将报文接收指示信息的地址组装成TLP包通过TLP接口发送给协议层设备，再由协议层设备将该TLP包转换成PCIe协议包通过高速串行总线发送给对端设备。
所述对端设备中具有报文接收指示信息的缓存空间以及接收报文的缓存空间，所述报文接收指示信息的初始地址和地址空间大小用于指示报文接收指示信息在缓存空间中的地址。启动第四工作模块时，第四工作模块首次发送的报文接收指示信息的地址为报文接收指示信息的初始地址。
步骤605、所述对端设备将所述报文接收指示信息的地址中的报文接收指示信息内容，通过协议层设备发送给第四工作模块。
所述对端设备接收到报文接收指示信息的地址后，会在缓存报文接收指示信息的缓存空间中将该地址对应的报文接收指示信息内容发送给控制器。所述报文接收指示信息内容包括报文接收有效指示信息、接收报文的初始缓存地址。
步骤606、所述第四工作模块的第五异步FIFO将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包。
目标设备可以将接收报文通过DMA通道发送给控制器的第四模块，第四工作模块的第五异步FIFO可以将目标设备发送的通用包结构形式的报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包。在这里需要说明的是，当第四工作模块 的第五异步FIFO中的缓存存满的时，第四工作模块可以通知目标设备不再发送接收报文过来。
步骤607、在所述报文接收有效指示信息为有效时，控制器将所述接收报文的初始缓存地址以及从第五异步FIFO输出的TLP包形式的报文数据包通过协议层设备发送给对端设备。
接收报文的初始缓存地址为对端设备将接收到的报文进行缓存的初始地址；在所述报文接收有效指示信息为有效时表明该地址为空可以缓存接收到的报文，此时第四工作模块将所述接收报文的初始缓存地址以及从第五异步FIFO输出的TLP包形式的报文数据包通过协议层设备发送给对端设备，在此传输过程中数据形式的转换参考上文描述。
若所述报文接收有效指示信息为无效或不正确时，则所述控制器会反复重复上述过程，直到所述对端设备发送的所述接收指示信息为有效。
步骤608、所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包。
步骤609、所述第四工作模块通过协议层设备向对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效。
所述第四工作模块将所述接收报文的报文数据包发送给对端设备后，由于对端设备会将从所述接收报文的初始缓存地址处缓存报文数据包，所述报文数据包初始缓存地址对应的缓存地址处就会被占用，而该地址对应的报文接收有效指示信息还是有效的，此时第四工作模块就需要向对端设备发送报文接收完成命令，该报文接收完成命令用于指示对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效。
所述报文接收指示信息的地址是从初始地址开始，按照上述步骤604-609将接收到的报文缓存到该初始地址后，所述第四工作模块会将报文 接收指示信息的初始地址自动加1，继续进行步骤604-609，完成后再加1，以此循环进行步骤604-609，直至所述报文接收指示信息的地址超出了步骤603解析出的报文接收指示信息的初始地址和地址空间大小限定的报文发送接收信息的地址范围。
本实施例方法中，控制器中两个或两个以上的工作模块可以同时工作，这样基于一条PCIe总线链路，本实施例方法可以实现同时进行CPU读写访问寄存器操作和数据报文的双向传输，从而也大大简化了一个PCIe总线设备或系统，也具有应用灵活多样性的特点；且本实施例方法中，一个所述控制器可以同时支持一个或一个以上所述目标设备，具有非常好的扩展性。数据报文的双向传输以DMA方式进行，且该DMA方式需通过所述CPU写操作来控制其开关使能和确定数据缓存空间大小、数据初始地址。特别是，通过所述报文收发指示信息实现了查询和控制DMA操作，以及实现了数据传输的自查询、自控制、错误或失败重传、所述报文发送指示信息空间的自轮询等特点，并兼具有数据位宽转换、异步时钟域转换、统计等功能；且一个所述控制器可以同时支持一个或一个以上所述目标设备，具有非常好的扩展性。
实施例3
本发明实施例提供了一种数据传输装置，基于增强型外设互连PCIe协议总线，如图7所示，所述装置包括：接收模块701，分配模块702，第一工作模块703、第二工作模块704、第三工作模块705和第四工作模块706，其中，
接收模块701，配置为接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；
分配模块702，配置为在所述接收模块701接收到的工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块；
所述第一工作模块703，配置为在解析出所述分配模块702分配的数据包获得读操作命令时，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；
分配模块702，还配置为在所述接收模块701接收到的工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块；
所述第二工作模块704，配置为在解析出所述分配模块702分配的所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；
所述第二工作模块704，还配置为在解析所述数据包获得DMA读操作命令时，启动所述第三工作模块705，并将所述DMA读操作命令发送给所述第三工作模块705；
所述第三工作模块705，配置为根据所述第二工作模块704发送的所述DMA读操作命令获得所述对端设备中的发送报文，并将所述发送报文发送给目标设备；
所述第二工作模块704，还配置为在解析出所述数据包获得DMA写操作命令时，启动所述第四工作模块706，将所述DMA写操作命令发送给所述第四工作模块706；
所述第四工作模块706，还配置为根据所述第二工作模块704发送的所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
可选的，如图8所示，所述第一工作模块703中包括：第一处理模块7031，第一异步先入先出缓存器FIFO模块7032和第二异步FIFO模块7033；其中，
所述第一处理模块7031，配置为解析数据包获得CPU读操作命令，然后将所述CPU读操作命令转换为一个或多个通用寄存器读操作访问命令；其中，所述CPU读操作命令中包括读使能、读初始地址、读数据个数，所 述通用寄存器读操作访问命令包括读使能、读地址；
所述第一处理模块7031，还配置为将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO模块7032中；
所述第一异步FIFO模块7032，配置为将所述第一处理模块7031缓存的一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序；
所述第一处理模块7031，还配置为将所述第一异步FIFO模块7032转换后的所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备；通用寄存器读操作访问命令用于所述目标设备进行读操作获得读数据；
所述第二异步FIFO，配置为通过配置通道接收所述读数据，并将所述读数据转换为符合PCIe协议要求的TLP包结构形式和时序；
所述第一处理模7031，配置为将所述第二异步FIFO模块7033转换后的读数据发送给对端设备。
所述第一异步FIFO模块，还配置为在第一预设时间内未接收到所述目标设备发送的读数据时，自行生成无效读数据。
可选的，如图9所示，所述第二工作模块704中包括：第二处理模块7041，第三异步FIFO模块7042；其中，
所述第二处理模块7041，配置为解析数据包获得CPU写操作命令，然后将所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令；其中，所述CPU写操作命令中包括写使能、写数据、写初始地址、写数据个数，所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据；
所述第二处理模块7041，还配置为将所述一个或多个通用寄存器写操作访问命令缓存到第三异步FIFO模块7042中；
所述第三异步FIFO模块7042，配置为将所述第二处理模块7041缓存的所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序；
所述第二处理模块7041，还配置为将所述第三异步FIFO模块7042转换后的所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备；通用寄存器写操作访问命令用于所述目标设备在写地址写入所述写地址对应的单个写数据；
所述第二处理模块7041，还配置为通过配置通道接收所述目标设备发送的写操作完成信号。
所述第二处理模块，还配置为在第二预设时间内未接收到所述目标设备发送的写操作完成信号时，生成所述写操作完成信号。
在一实施例中，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；如图10所示，所述第三工作模块705包括第三处理模块7051和第四异步FIFO模块7052；其中，
第三处理模块7051，配置为在第i次时，根据所述DMA读操作命令将报文发送指示信息的地址发送给对端设备；其中，所述报文发送指示信息的地址为报文发送指示信息的初始地址+i-1，i为大于等于1的整数；所述报文发送指示信息的地址不超出所述报文发送指示信息的初始地址和地址空间大小限定的地址范围。
第三处理模块7051，还配置为接收对端设备发送的所述报文发送指示信息的地址中的报文发送指示信息内容；其中，所述报文发送指示信息内容包括报文发送有效指示信息、报文大小和报文初始缓存的地址；
第三处理模块7051，还配置为在所述报文发送有效指示信息为有效时，将所述报文大小和报文初始缓存地址发送给对端设备；
第三处理模块7051，还配置为接收所述对端设备发送的所述报文大小 和报文初始缓存地址对应的发送报文，并将所述发送报文缓存到第四异步FIFO模块7052中；
所述第四异步FIFO模块7052，配置为在将所述第三处理模块7051缓存的发送报文经过时序转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备；
第三处理模块7051，还配置为在所述第四异步FIFO模块7052将所述发送报文发送给目标设备后，向对端设备发送报文发送完成命令，所述报文发送完成命令用于所述对端设备将所述发送报文对应的报文发送有效指示信息更改为无效。
在一实施例中，所述DMA写操作命令中包括报文接收指示信息的初始地址和地址空间大小；如图11所示，所述第四工作模块706包括：第四处理模块7061和第五异步FIFO模块7062，其中，
所述第四处理模块7061，配置为在第j次时，根据所述DMA写操作命令将报文接收指示信息的地址发送给对端设备；其中，所述报文接收指示信息的地址为报文接收指示信息的初始地址+j-1，j为大于等于1的整数；所述报文接收指示信息的地址未超出所述报文接收指示信息的初始地址和地址空间大小限定的地址范围；
所述第四处理模块7061，还配置为接收对端设备发送的所述报文接收指示信息的地址中的报文接收指示信息内容；其中，所述报文接收指示信息内容包括报文接收有效指示信息、接收报文的初始缓存地址；
所述第五异步FIFO模块7062，配置为将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包；
所述第四处理模块7061，还配置为在所述报文接收有效指示信息为有效时，将所述接收报文的初始缓存地址以及所述第五异步FIFO模块7062 输出的报文数据包发送给对端设备；所述接收报文的初始缓存地址用于所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包；
所述第四处理模块7061，还配置为向对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效。
在实际应用中，接收模块701，分配模块702，第一工作模块703、第二工作模块704、第三工作模块705和第四工作模块706可以由位于控制器上的中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等器件实现。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个 流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例控制器接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；在工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块，所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块，所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；所述第二工作模块解析所述数据包获得直接存储访问DMA读操作命令时，启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块，所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备；所述第二工作模块解析所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块，所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。如此，控制器中两个或两个以上的工作模块可以同时工作，这样，基于一条PCIe总线链路，可以实现同时进行CPU读写访问寄存器操作和数 据报文以DMA方式进行双向传输，从而也大大简化了PCIe总线设备或系统，具有应用灵活多样性的特点；另外，一个所述控制器可以同时支持一个或一个以上的目标设备，具有非常好的扩展性。

Claims (15)

  1. 一种数据传输方法，所述方法应用于控制器，所述控制器中包括第一工作模块、第二工作模块、第三工作模块和第四工作模块，所述方法包括：
    接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；
    在工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块，所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；
    在工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块，所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；
    所述第二工作模块解析所述数据包获得直接存储访问DMA读操作命令时，启动所述第三工作模块，将所述DMA读操作命令发送给所述第三工作模块，所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备；
    所述第二工作模块解析所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工作模块，所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
  2. 根据权利要求1所述的方法，其中，所述第一工作模块解析所述数据包获得读操作命令，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备，包括：
    所述第一工作模块解析数据包获得CPU读操作命令，然后将所述CPU 读操作命令转换为一个或多个通用寄存器读操作访问命令；其中，所述CPU读操作命令中包括读使能、读初始地址、读数据个数，所述通用寄存器读操作访问命令包括读使能、读地址；
    第一工作模块将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO中；
    所述第一工作模块中的第一异步FIFO将所述一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备；通用寄存器读操作访问命令用于所述目标设备进行读操作获得读数据；
    所述第一工作模块中的第二异步FIFO通过配置通道接收所述读数据，并将所述读数据转换为符合增强型外设互连PCIe协议要求的TLP包结构形式和时序；并将转换后的读数据发送给对端设备。
  3. 根据权利要求2所述的方法，其中，所述第一工作模块的第二异步FIFO在第一预设时间内未接收到所述目标设备发送的读数据时，自行生成无效读数据。
  4. 根据权利要求1所述的方法，其中，所述第二工作模块解析所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号，包括：
    所述第二工作模块解析数据包获得CPU写操作命令，然后将所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令；其中，所述CPU写操作命令中包括写使能、写数据、写初始地址、写数据个数，所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据；
    第二工作模块将所述一个或多个通用寄存器写操作访问命令缓存到第三异步FIFO中；
    所述第二工作模块中的第三异步FIFO将所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备；通用寄存器写操作访问命令用于所述目标设备在写地址写入所述写地址对应的单个写数据；
    所述第二工作模块通过配置通道接收所述目标设备发送的写操作完成信号。
  5. 根据权利要求4所述的方法，其中，所述第二工作模块在第二预设时间内未接收到所述目标设备发送的写操作完成信号时，所述第二工作模块自行生成所述写操作完成信号。
  6. 根据权利要求1所述的方法，其中，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；所述第三工作模块根据所述DMA读操作命令获得所述对端设备中的发送报文，将所述发送报文发送给目标设备，包括：
    在第i次时，所述第三工作模块根据所述DMA读操作命令将报文发送指示信息的地址发送给对端设备；其中，所述报文发送指示信息的地址为报文发送指示信息的初始地址+i-1，i为大于等于1的整数；
    所述第三工作模块接收对端设备发送的所述报文发送指示信息的地址中的报文发送指示信息内容；其中，所述报文发送指示信息内容包括报文发送有效指示信息、报文大小和报文初始缓存的地址；
    所述第三工作模块在所述报文发送有效指示信息为有效时，将所述报文大小和报文初始缓存地址发送给对端设备；
    所述第三工作模块接收所述对端设备发送的所述报文大小和报文初始缓存地址对应的发送报文；
    所述第三工作模块将所述发送报文缓存到第四异步FIFO中，经过时序 转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备；
    所述第三工作模块向对端设备发送报文发送完成命令，所述报文发送完成命令用于所述对端设备将所述发送报文对应的报文发送有效指示信息更改为无效；
    依次循环进行上述步骤，直至所述报文发送指示信息的地址超出所述报文发送指示信息的初始地址和地址空间大小限定的地址范围。
  7. 根据权利要求1所述的方法，其中，所述DMA写操作命令中包括报文接收指示信息的初始地址和地址空间大小；所述第四工作模块根据所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备，包括：
    在第j次时，所述第四工作模块根据所述DMA写操作命令将报文接收指示信息的地址发送给对端设备；其中，所述报文接收指示信息的地址为报文接收指示信息的初始地址+j-1，j为大于等于1的整数；
    所述第四工作模块接收对端设备发送的所述报文接收指示信息的地址中的报文接收指示信息内容；其中，所述报文接收指示信息内容包括报文接收有效指示信息、接收报文的初始缓存地址；
    所述第四工作模块的第五异步FIFO将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包；
    在所述报文接收有效指示信息为有效时，所述第四工作模块将所述接收报文的初始缓存地址以及从第五异步FIFO输出的报文数据包发送给对端设备；所述接收报文的初始缓存地址用于所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包；
    所述第四工作模块对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收 有效指示信息更改为无效；
    依次循环进行上述步骤，直至所述报文接收指示信息的地址超出所述报文接收指示信息的初始地址和地址空间大小限定的地址范围。
  8. 一种数据传输装置，所述装置包括：接收模块，分配模块，第一工作模块、第二工作模块、第三工作模块和第四工作模块，其中，
    接收模块，配置为接收对端设备发送的数据包，所述数据包上携带有工作类型标志位；
    分配模块，配置为在所述接收模块接收到的工作类型标志位表示为读操作时，将所述数据包分配给第一工作模块；
    所述第一工作模块，配置为在解析出所述分配模块分配的数据包获得读操作命令时，将所述读操作命令发送给目标设备，接收目标设备返回的读数据，并将所述读数据发送给所述对端设备；
    分配模块，还配置为在所述接收模块接收到的工作类型标志位表示为写操作时，将所述数据包分配给第二工作模块；
    所述第二工作模块，配置为在解析出所述分配模块分配的所述数据包获得写操作命令时，将所述数据包中的写操作命令发送给目标设备，接收目标设备返回的写操作完成信号；
    所述第二工作模块，还配置为在解析所述数据包获得直接存储访问DMA读操作命令时，启动所述第三工作模块，并将所述DMA读操作命令发送给所述第三工作模块；
    所述第三工作模块，配置为根据所述第二工作模块发送的所述DMA读操作命令获得所述对端设备中的发送报文，并将所述发送报文发送给目标设备；
    所述第二工作模块，还配置为在解析出所述数据包获得DMA写操作命令时，启动所述第四工作模块，将所述DMA写操作命令发送给所述第四工 作模块；
    所述第四工作模块，配置为根据所述第二工作模块发送的所述DMA写操作命令将目标设备发送的接收报文，发送给对端设备。
  9. 根据权利要求8所述的装置，其中，所述第一工作模块中包括：第一处理模块，第一异步先入先出缓存器FIFO模块和第二异步FIFO模块；其中，
    所述第一处理模块，配置为解析数据包获得CPU读操作命令，然后将所述CPU读操作命令转换为一个或多个通用寄存器读操作访问命令；其中，所述CPU读操作命令中包括读使能、读初始地址、读数据个数，所述通用寄存器读操作访问命令包括读使能、读地址；
    所述第一处理模块，还配置为将所述一个或多个通用寄存器读操作访问命令缓存到第一异步先入先出缓存器FIFO模块中；
    所述第一异步FIFO模块，配置为将所述第一处理模块缓存的一个或多个通用寄存器读操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器读操作访问命令通过配置通道发送给所述目标设备；通用寄存器读操作访问命令用于所述目标设备进行读操作获得读数据；
    所述第二异步FIFO模块，配置为通过配置通道接收所述读数据，并将所述读数据转换为符合增强型外设互连PCIe协议要求的TLP包结构形式和时序；并将转换后的读数据发送给对端设备。
  10. 根据权利要求9所述的装置，其中，所述第一异步FIFO模块，还配置为在第一预设时间内未接收到所述目标设备发送的读数据时，自行生成无效读数据。
  11. 根据权利要求8所述的装置，其中，所述第二工作模块中包括：第二处理模块，第三异步FIFO模块；其中，
    所述第二处理模块，配置为解析数据包获得CPU写操作命令，然后将所述CPU写操作命令转换为一个或多个通用寄存器写操作访问命令；其中，所述CPU写操作命令中包括写使能、写数据、写初始地址、写数据个数，所述通用寄存器写操作访问命令包括写使能、写地址、所述写地址对应的单个写数据；
    所述第二处理模块，还配置为将所述一个或多个通用寄存器写操作访问命令缓存到第三异步FIFO模块中；
    所述第三异步FIFO模块，配置为将所述第二处理模块缓存的所述一个或多个通用寄存器写操作访问命令的时序转换为符合目标设备的时序，并在转换后将所述一个或多个通用寄存器写操作访问命令通过配置通道发送给所述目标设备；通用寄存器写操作访问命令用于所述目标设备在写地址写入所述写地址对应的单个写数据；
    所述第二处理模块，还配置为通过配置通道接收所述目标设备发送的写操作完成信号。
  12. 根据权利要求11所述的装置，其中，所述第二处理模块，还配置为在第二预设时间内未接收到所述目标设备发送的写操作完成信号时，生成所述写操作完成信号。
  13. 根据权利要求8所述的装置，其中，所述DMA读操作命令中包括报文发送指示信息的初始地址和地址空间大小；所述第三工作模块包括第三处理模块和第四异步FIFO模块；其中，
    第三处理模块，配置为在第i次时，根据所述DMA读操作命令将报文发送指示信息的地址发送给对端设备；其中，所述报文发送指示信息的地址为报文发送指示信息的初始地址+i-1，i为大于等于1的整数；所述报文发送指示信息的地址不超出所述报文发送指示信息的初始地址和地址空间大小限定的地址范围。
    第三处理模块，还配置为接收对端设备发送的所述报文发送指示信息的地址中的报文发送指示信息内容；其中，所述报文发送指示信息内容包括报文发送有效指示信息、报文大小和报文初始缓存的地址；
    第三处理模块，还配置为在所述报文发送有效指示信息为有效时，将所述报文大小和报文初始缓存地址发送给对端设备；
    第三处理模块，还配置为接收所述对端设备发送的所述报文大小和报文初始缓存地址对应的发送报文，并将所述发送报文缓存到第四异步FIFO模块中。
    所述第四异步FIFO模块，配置为在将所述第三处理模块缓存的发送报文经过时序转换、数据位宽转换后，转换为通用包结构形式报文，通过DMA通道发送给目标设备；
    第三处理模块，还配置为在所述第四异步FIFO模块将所述发送报文发送给目标设备后，向对端设备发送报文发送完成命令，所述报文发送完成命令用于所述对端设备将所述发送报文对应的报文发送有效指示信息更改为无效。
  14. 根据权利要求8所述的装置，其中，所述DMA写操作命令中包括报文接收指示信息的初始地址和地址空间大小；所述第四工作模块包括：第四处理模块和第五异步FIFO模块，其中，
    所述第四处理模块，配置为在第j次时，根据所述DMA写操作命令将报文接收指示信息的地址发送给对端设备；其中，所述报文接收指示信息的地址为报文接收指示信息的初始地址+j-1，j为大于等于1的整数；所述报文接收指示信息的地址未超出所述报文接收指示信息的初始地址和地址空间大小限定的地址范围；
    所述第四处理模块，还配置为接收对端设备发送的所述报文接收指示信息的地址中的报文接收指示信息内容；其中，所述报文接收指示信息内 容包括报文接收有效指示信息、接收报文的初始缓存地址；
    所述第五异步FIFO模块，配置为将目标设备发送的通用包结构形式的接收报文进行缓存、时序转换和数据位宽转换后，转换为符合PCIe协议要求的TLP包结构形式和时序的报文数据包；
    所述第四处理模块，还配置为在所述报文接收有效指示信息为有效时，将所述接收报文的初始缓存地址以及所述第五异步FIFO模块输出的报文数据包发送给对端设备；所述接收报文的初始缓存地址用于所述对端设备从所述接收报文的初始缓存地址处缓存报文数据包；
    所述第四处理模块，还配置为向对端设备发送报文接收完成命令，所述报文接收完成命令用于所述对端设备将所述报文数据包初始缓存地址对应的报文接收有效指示信息更改为无效。
  15. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至7任一项所述的数据传输方法。
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