JP2010531000A5 - - Google Patents

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Publication number
JP2010531000A5
JP2010531000A5 JP2010507479A JP2010507479A JP2010531000A5 JP 2010531000 A5 JP2010531000 A5 JP 2010531000A5 JP 2010507479 A JP2010507479 A JP 2010507479A JP 2010507479 A JP2010507479 A JP 2010507479A JP 2010531000 A5 JP2010531000 A5 JP 2010531000A5
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JP
Japan
Prior art keywords
logic
input signal
delayed
signal
circuit
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JP2010507479A
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English (en)
Japanese (ja)
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JP2010531000A (ja
JP5410414B2 (ja
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Priority claimed from US12/117,711 external-priority patent/US7908574B2/en
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Publication of JP2010531000A5 publication Critical patent/JP2010531000A5/ja
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JP2010507479A 2007-05-09 2008-05-09 回路エミュレーションの入力及び遅延入力のマルチプレクシング Active JP5410414B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91703307P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91701507P 2007-05-09 2007-05-09
US60/917,024 2007-05-09
US60/917,033 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US12/117,711 2008-05-08
US12/117,711 US7908574B2 (en) 2007-05-09 2008-05-08 Techniques for use with automated circuit design and simulations
PCT/US2008/006009 WO2008140789A1 (en) 2007-05-09 2008-05-09 Multiplexing of inputs and delayed inputs of a circuit emulation

Publications (3)

Publication Number Publication Date
JP2010531000A JP2010531000A (ja) 2010-09-16
JP2010531000A5 true JP2010531000A5 (enExample) 2011-06-30
JP5410414B2 JP5410414B2 (ja) 2014-02-05

Family

ID=39736888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010507479A Active JP5410414B2 (ja) 2007-05-09 2008-05-09 回路エミュレーションの入力及び遅延入力のマルチプレクシング

Country Status (5)

Country Link
US (1) US7908574B2 (enExample)
EP (1) EP2145272B1 (enExample)
JP (1) JP5410414B2 (enExample)
CN (1) CN101720467B (enExample)
WO (1) WO2008140789A1 (enExample)

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US8756557B2 (en) 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
JP2009193165A (ja) * 2008-02-12 2009-08-27 Toshiba Corp デバッグ装置およびデバッグ方法
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US8255702B1 (en) * 2009-12-03 2012-08-28 Altera Corporation Programmable logic device with improved security
US8661383B1 (en) * 2010-07-28 2014-02-25 VSYNC Circuits, Ltd. VLSI black-box verification
US8707229B1 (en) 2010-07-28 2014-04-22 VSYNC Circuit, Ltd. Static analysis of VLSI reliability
US8443313B2 (en) * 2010-08-18 2013-05-14 International Business Machines Corporation Circuit design optimization
US8631364B1 (en) 2010-12-26 2014-01-14 VSYNC Circuits Ltd. Constraining VLSI circuits
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CN103941105B (zh) * 2013-01-17 2016-08-17 德律科技股份有限公司 时序分析装置及时序分析方法
US8775986B1 (en) * 2013-02-25 2014-07-08 Xilinx, Inc. Software debugging of synthesized hardware
US9495492B1 (en) * 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US10140413B2 (en) * 2015-04-21 2018-11-27 Synopsys, Inc. Efficient resolution of latch race conditions in emulation
US10210919B2 (en) * 2015-06-03 2019-02-19 Altera Corporation Integrated circuits with embedded double-clocked components
CN107103116B (zh) * 2017-03-27 2019-07-30 中国科学院计算技术研究所 一种复用追踪缓存的触发装置及设计方法
JP7180043B2 (ja) * 2018-07-30 2022-11-30 東芝情報システム株式会社 ディジタル検証支援装置及びディジタル検証支援用プログラム
US11106437B2 (en) 2019-01-14 2021-08-31 Microsoft Technology Licensing, Llc Lookup table optimization for programming languages that target synchronous digital circuits
US11275568B2 (en) 2019-01-14 2022-03-15 Microsoft Technology Licensing, Llc Generating a synchronous digital circuit from a source code construct defining a function call
US11144286B2 (en) 2019-01-14 2021-10-12 Microsoft Technology Licensing, Llc Generating synchronous digital circuits from source code constructs that map to circuit implementations
US11113176B2 (en) * 2019-01-14 2021-09-07 Microsoft Technology Licensing, Llc Generating a debugging network for a synchronous digital circuit during compilation of program source code
US11093682B2 (en) 2019-01-14 2021-08-17 Microsoft Technology Licensing, Llc Language and compiler that generate synchronous digital circuits that maintain thread execution order
LU101294B1 (en) * 2019-07-03 2021-01-20 Onespin Solutions Gmbh Method of checking equivalence between a first design comprising a shift register logic srl chain and a second design
CN112291080B (zh) * 2020-09-27 2023-07-04 青岛矽昌通信技术有限公司 一种通信模拟的控制方法及系统
WO2022178793A1 (zh) * 2021-02-26 2022-09-01 华为技术有限公司 一种延迟补偿方法以及相关设备

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US5553275A (en) * 1993-07-13 1996-09-03 Intel Corporation Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock
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