JP2010531002A5 - - Google Patents
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- Publication number
- JP2010531002A5 JP2010531002A5 JP2010507481A JP2010507481A JP2010531002A5 JP 2010531002 A5 JP2010531002 A5 JP 2010531002A5 JP 2010507481 A JP2010507481 A JP 2010507481A JP 2010507481 A JP2010507481 A JP 2010507481A JP 2010531002 A5 JP2010531002 A5 JP 2010531002A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clock
- phase relationship
- circuit
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 15
- 230000007704 transition Effects 0.000 claims 10
- 238000005070 sampling Methods 0.000 claims 7
- 230000003111 delayed effect Effects 0.000 claims 4
- 230000010076 replication Effects 0.000 claims 3
- 238000004088 simulation Methods 0.000 claims 3
- 238000001514 detection method Methods 0.000 claims 2
Applications Claiming Priority (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US91703307P | 2007-05-09 | 2007-05-09 | |
| US91702707P | 2007-05-09 | 2007-05-09 | |
| US91702407P | 2007-05-09 | 2007-05-09 | |
| US91701507P | 2007-05-09 | 2007-05-09 | |
| US60/917,024 | 2007-05-09 | ||
| US60/917,033 | 2007-05-09 | ||
| US60/917,027 | 2007-05-09 | ||
| US60/917,015 | 2007-05-09 | ||
| US12/117,714 US7904859B2 (en) | 2007-05-09 | 2008-05-08 | Method and apparatus for determining a phase relationship between asynchronous clock signals |
| US12/117,714 | 2008-05-08 | ||
| PCT/US2008/006012 WO2008140791A2 (en) | 2007-05-09 | 2008-05-09 | Computation of phase relationship by clock sampling |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010531002A JP2010531002A (ja) | 2010-09-16 |
| JP2010531002A5 true JP2010531002A5 (enExample) | 2011-06-23 |
| JP5432127B2 JP5432127B2 (ja) | 2014-03-05 |
Family
ID=39776985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010507481A Active JP5432127B2 (ja) | 2007-05-09 | 2008-05-09 | 自動回路設計及びシミュレーションに使用するための技術 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7904859B2 (enExample) |
| EP (1) | EP2145273B1 (enExample) |
| JP (1) | JP5432127B2 (enExample) |
| CN (1) | CN101720465B (enExample) |
| WO (1) | WO2008140791A2 (enExample) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8756557B2 (en) | 2007-05-09 | 2014-06-17 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US8271918B2 (en) * | 2009-01-31 | 2012-09-18 | Mentor Graphics Corporation | Formal verification of clock domain crossings |
| US8255702B1 (en) * | 2009-12-03 | 2012-08-28 | Altera Corporation | Programmable logic device with improved security |
| US8479135B2 (en) * | 2009-12-15 | 2013-07-02 | Apple Inc. | Automated framework for programmable logic device implementation of integrated circuit design |
| US8302038B2 (en) * | 2009-12-15 | 2012-10-30 | Apple Inc. | Engineering change order language for modifying integrated circuit design files for programmable logic device implementation |
| US8332795B2 (en) * | 2009-12-15 | 2012-12-11 | Apple Inc. | Automated pin multiplexing for programmable logic device implementation of integrated circuit design |
| US8166437B2 (en) | 2009-12-15 | 2012-04-24 | Apple Inc. | Automated pad ring generation for programmable logic device implementation of integrated circuit design |
| US8397195B2 (en) * | 2010-01-22 | 2013-03-12 | Synopsys, Inc. | Method and system for packet switch based logic replication |
| US8638792B2 (en) * | 2010-01-22 | 2014-01-28 | Synopsys, Inc. | Packet switch based logic replication |
| US8751986B2 (en) * | 2010-08-06 | 2014-06-10 | Synopsys, Inc. | Method and apparatus for automatic relative placement rule generation |
| GB2484295A (en) * | 2010-10-05 | 2012-04-11 | St Microelectronics Ltd | Circuit simulation |
| US8584067B2 (en) | 2010-11-02 | 2013-11-12 | Advanced Micro Devices, Inc. | Clock domain crossing buffer |
| US8826057B1 (en) | 2012-03-30 | 2014-09-02 | Integrated Device Technology Inc. | Multiple time domain synchronizer circuits |
| US8943242B1 (en) | 2012-03-30 | 2015-01-27 | Integrated Device Technology Inc. | Timing controllers having partitioned pipelined delay chains therein |
| US9098486B1 (en) * | 2013-03-14 | 2015-08-04 | Altera Corporation | Methods and apparatus for testing multiple clock domain memories |
| CN104702249B (zh) * | 2013-12-10 | 2019-08-02 | 苏州普源精电科技有限公司 | 一种具有猝发同步功能的信号发生器 |
| US9361417B2 (en) | 2014-02-07 | 2016-06-07 | Synopsys, Inc. | Placement of single-bit and multi-bit flip-flops |
| GB2519181B (en) | 2014-03-31 | 2015-09-09 | Imagination Tech Ltd | Clock verification |
| US9495492B1 (en) * | 2015-01-05 | 2016-11-15 | Cadence Design Systems, Inc. | Implementing synchronous triggers for waveform capture in an FPGA prototyping system |
| KR102254715B1 (ko) * | 2015-02-03 | 2021-05-24 | 삼성전자주식회사 | 소프트웨어 프로그래밍을 위한 레지스터 방법 및 장치 |
| US10325046B2 (en) * | 2016-09-20 | 2019-06-18 | Synopsys, Inc. | Formal method for clock tree analysis and optimization |
| CN107528658B (zh) * | 2017-08-02 | 2019-02-19 | 北京交通大学 | 一种时钟恢复方法及装置 |
| LU101294B1 (en) * | 2019-07-03 | 2021-01-20 | Onespin Solutions Gmbh | Method of checking equivalence between a first design comprising a shift register logic srl chain and a second design |
| CN112580278B (zh) * | 2020-12-07 | 2023-06-09 | 海光信息技术股份有限公司 | 逻辑电路的优化方法、优化装置以及存储介质 |
| US11776600B2 (en) * | 2021-02-03 | 2023-10-03 | Micron Technology, Inc. | Memory clock management and estimation procedures |
| CN113392606B (zh) * | 2021-06-11 | 2024-10-22 | 北京物芯科技有限责任公司 | 内部接口信号的采样方法、装置及计算设备 |
| US11755336B2 (en) | 2021-09-29 | 2023-09-12 | Advanced Micro Devices, Inc. | Distributed geometry |
| US11947473B2 (en) * | 2021-10-12 | 2024-04-02 | Advanced Micro Devices, Inc. | Duplicated registers in chiplet processing units |
| US20230409788A1 (en) * | 2022-06-21 | 2023-12-21 | Synopsys, Inc. | Synchronizing distributed simulations of a circuit design |
| US12147265B2 (en) * | 2022-11-21 | 2024-11-19 | Ati Technologies Ulc | Avoid reduced effective bandwidth on transmission lines in the presence of clock domain differences |
Family Cites Families (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1533577A (en) * | 1975-11-05 | 1978-11-29 | Computer Technology Ltd | Synchronising means |
| US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
| US5596742A (en) * | 1993-04-02 | 1997-01-21 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
| US5553275A (en) * | 1993-07-13 | 1996-09-03 | Intel Corporation | Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock |
| US5659716A (en) * | 1994-11-23 | 1997-08-19 | Virtual Machine Works, Inc. | Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
| US5878221A (en) * | 1996-02-05 | 1999-03-02 | Xinex Networks Inc. | Network for multimedia asynchronous transfer mode digital signal transmission and components thereof |
| US6052748A (en) * | 1997-03-18 | 2000-04-18 | Edwin A. Suominen | Analog reconstruction of asynchronously sampled signals from a digital signal processor |
| US5943490A (en) * | 1997-05-30 | 1999-08-24 | Quickturn Design Systems, Inc. | Distributed logic analyzer for use in a hardware logic emulation system |
| US6694464B1 (en) * | 1997-05-30 | 2004-02-17 | Quickturn Design Systems, Inc. | Method and apparatus for dynamically testing electrical interconnect |
| US6473439B1 (en) * | 1997-10-10 | 2002-10-29 | Rambus Incorporated | Method and apparatus for fail-safe resynchronization with minimum latency |
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| US5990734A (en) * | 1998-06-19 | 1999-11-23 | Datum Telegraphic Inc. | System and methods for stimulating and training a power amplifier during non-transmission events |
| KR20010006983A (ko) | 1999-06-26 | 2001-01-26 | 양세양 | 신속 프로토타이핑 장치와 그것의 입출력 탐침방법 및그것을 이용한 혼합 검증 방법 |
| KR100710972B1 (ko) | 1999-06-26 | 2007-04-24 | 양세양 | 혼합된 에뮬레이션과 시뮬레이션이 가능한 혼합 검증 장치및 이를 이용한 혼합 검증 방법 |
| WO2001001245A1 (en) * | 1999-06-26 | 2001-01-04 | Yang Sei Yang | Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it |
| US6823497B2 (en) * | 1999-11-30 | 2004-11-23 | Synplicity, Inc. | Method and user interface for debugging an electronic system |
| US7072818B1 (en) * | 1999-11-30 | 2006-07-04 | Synplicity, Inc. | Method and system for debugging an electronic system |
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| US7379859B2 (en) * | 2001-04-24 | 2008-05-27 | Mentor Graphics Corporation | Emulator with switching network connections |
| US6691301B2 (en) * | 2001-01-29 | 2004-02-10 | Celoxica Ltd. | System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures |
| KR100794916B1 (ko) | 2001-09-14 | 2008-01-14 | 양세양 | 에뮬레이션과 시뮬레이션을 혼용한 점진적 설계 검증을위한 설계검증 장치 및 이를 이용한 설계 검증 방법 |
| JP2003283313A (ja) * | 2002-03-26 | 2003-10-03 | Fujitsu Ltd | 位相比較器および位相同期ループ回路 |
| JP2004061339A (ja) * | 2002-07-30 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 位相検出装置 |
| US6904576B2 (en) * | 2002-08-09 | 2005-06-07 | Synplicity, Inc. | Method and system for debugging using replicated logic |
| US7213216B2 (en) * | 2002-08-09 | 2007-05-01 | Synplicity, Inc. | Method and system for debugging using replicated logic and trigger logic |
| US7398445B2 (en) * | 2002-08-09 | 2008-07-08 | Synplicity, Inc. | Method and system for debug and test using replicated logic |
| US6727740B2 (en) * | 2002-08-29 | 2004-04-27 | Micron Technology, Inc. | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals |
| US7007254B1 (en) * | 2003-01-17 | 2006-02-28 | Synplicity, Inc. | Method and apparatus for the design and analysis of digital circuits with time division multiplexing |
| US7440884B2 (en) | 2003-01-23 | 2008-10-21 | Quickturn Design Systems, Inc. | Memory rewind and reconstruction for hardware emulator |
| US7245684B2 (en) * | 2003-05-09 | 2007-07-17 | Hewlett-Packard Development Company, L.P. | System and method for compensating for skew between a first clock signal and a second clock signal |
| WO2005022819A1 (en) * | 2003-08-29 | 2005-03-10 | Koninklijke Philips Electronics N.V. | Phase detector |
| DE10345150B3 (de) * | 2003-09-29 | 2005-04-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren, Vorrichtung und System zum Analysieren digitaler Schaltungen |
| US7031221B2 (en) * | 2003-12-30 | 2006-04-18 | Intel Corporation | Fixed phase clock and strobe signals in daisy chained chips |
| US20060062341A1 (en) * | 2004-09-20 | 2006-03-23 | Edmondson John H | Fast-lock clock-data recovery system |
| US7334203B2 (en) * | 2004-10-01 | 2008-02-19 | Dynetix Design Solutions, Inc. | RaceCheck: a race logic analyzer program for digital integrated circuits |
| US7617470B1 (en) * | 2005-10-11 | 2009-11-10 | California Institute Of Technology | Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit |
| US7908574B2 (en) * | 2007-05-09 | 2011-03-15 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US7984400B2 (en) * | 2007-05-09 | 2011-07-19 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US8756557B2 (en) * | 2007-05-09 | 2014-06-17 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
-
2008
- 2008-05-08 US US12/117,714 patent/US7904859B2/en active Active
- 2008-05-09 EP EP08754341.9A patent/EP2145273B1/en active Active
- 2008-05-09 JP JP2010507481A patent/JP5432127B2/ja active Active
- 2008-05-09 WO PCT/US2008/006012 patent/WO2008140791A2/en not_active Ceased
- 2008-05-09 CN CN2008800230858A patent/CN101720465B/zh active Active
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