JP5432127B2 - 自動回路設計及びシミュレーションに使用するための技術 - Google Patents

自動回路設計及びシミュレーションに使用するための技術 Download PDF

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JP5432127B2
JP5432127B2 JP2010507481A JP2010507481A JP5432127B2 JP 5432127 B2 JP5432127 B2 JP 5432127B2 JP 2010507481 A JP2010507481 A JP 2010507481A JP 2010507481 A JP2010507481 A JP 2010507481A JP 5432127 B2 JP5432127 B2 JP 5432127B2
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circuit
clock
design
logic
signal
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JP2010531002A5 (enExample
JP2010531002A (ja
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リチャード シー メクスナー
マリオ ラルシュ
チュン キット ヌグ
ケニス マケルヴェイン
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Synopsys Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2010507481A 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術 Active JP5432127B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91703307P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91701507P 2007-05-09 2007-05-09
US60/917,024 2007-05-09
US60/917,033 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US12/117,714 US7904859B2 (en) 2007-05-09 2008-05-08 Method and apparatus for determining a phase relationship between asynchronous clock signals
US12/117,714 2008-05-08
PCT/US2008/006012 WO2008140791A2 (en) 2007-05-09 2008-05-09 Computation of phase relationship by clock sampling

Publications (3)

Publication Number Publication Date
JP2010531002A JP2010531002A (ja) 2010-09-16
JP2010531002A5 JP2010531002A5 (enExample) 2011-06-23
JP5432127B2 true JP5432127B2 (ja) 2014-03-05

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JP2010507481A Active JP5432127B2 (ja) 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術

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US (1) US7904859B2 (enExample)
EP (1) EP2145273B1 (enExample)
JP (1) JP5432127B2 (enExample)
CN (1) CN101720465B (enExample)
WO (1) WO2008140791A2 (enExample)

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Also Published As

Publication number Publication date
US7904859B2 (en) 2011-03-08
US20080313589A1 (en) 2008-12-18
WO2008140791A2 (en) 2008-11-20
EP2145273B1 (en) 2018-11-07
CN101720465B (zh) 2013-10-02
EP2145273A2 (en) 2010-01-20
JP2010531002A (ja) 2010-09-16
CN101720465A (zh) 2010-06-02
WO2008140791A3 (en) 2009-03-12

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