JP2010531001A5 - - Google Patents

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Publication number
JP2010531001A5
JP2010531001A5 JP2010507480A JP2010507480A JP2010531001A5 JP 2010531001 A5 JP2010531001 A5 JP 2010531001A5 JP 2010507480 A JP2010507480 A JP 2010507480A JP 2010507480 A JP2010507480 A JP 2010507480A JP 2010531001 A5 JP2010531001 A5 JP 2010531001A5
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JP
Japan
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additional
register
memory
design
input signal
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JP2010507480A
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English (en)
Japanese (ja)
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JP2010531001A (ja
JP5405451B2 (ja
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Priority claimed from US12/117,705 external-priority patent/US7984400B2/en
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Publication of JP2010531001A5 publication Critical patent/JP2010531001A5/ja
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JP2010507480A 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術 Active JP5405451B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91703307P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91701507P 2007-05-09 2007-05-09
US60/917,024 2007-05-09
US60/917,033 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US12/117,705 US7984400B2 (en) 2007-05-09 2008-05-08 Techniques for use with automated circuit design and simulations
US12/117,705 2008-05-08
PCT/US2008/006011 WO2008140790A2 (en) 2007-05-09 2008-05-09 Recording of emulation states using replicated memory elements

Publications (3)

Publication Number Publication Date
JP2010531001A JP2010531001A (ja) 2010-09-16
JP2010531001A5 true JP2010531001A5 (enExample) 2011-06-30
JP5405451B2 JP5405451B2 (ja) 2014-02-05

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ID=39722659

Family Applications (1)

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JP2010507480A Active JP5405451B2 (ja) 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術

Country Status (5)

Country Link
US (1) US7984400B2 (enExample)
EP (1) EP2165280B1 (enExample)
JP (1) JP5405451B2 (enExample)
CN (1) CN101720466B (enExample)
WO (1) WO2008140790A2 (enExample)

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US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US8001497B2 (en) * 2008-10-01 2011-08-16 Lsi Corporation Control signal source replication
US20130144589A1 (en) * 2010-06-08 2013-06-06 Delon Levi Systems and methods for circuit design, synthesis, simulation, and modeling
US8661383B1 (en) 2010-07-28 2014-02-25 VSYNC Circuits, Ltd. VLSI black-box verification
US8707229B1 (en) 2010-07-28 2014-04-22 VSYNC Circuit, Ltd. Static analysis of VLSI reliability
US8631364B1 (en) * 2010-12-26 2014-01-14 VSYNC Circuits Ltd. Constraining VLSI circuits
US8886507B2 (en) * 2011-07-13 2014-11-11 General Electric Company Methods and systems for simulating circuit operation
CN102955713B (zh) * 2011-08-31 2015-11-25 北京中电华大电子设计有限责任公司 一种802.11n无线网卡芯片仿真固件优化的处理方法
US9230046B2 (en) 2012-03-30 2016-01-05 International Business Machines Corporation Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
US9286423B2 (en) 2012-03-30 2016-03-15 International Business Machines Corporation Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
JP5949410B2 (ja) 2012-04-23 2016-07-06 株式会社ソシオネクスト 半導体装置
US9495492B1 (en) * 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US9552456B2 (en) * 2015-05-29 2017-01-24 Altera Corporation Methods and apparatus for probing signals from a circuit after register retiming
TWI579768B (zh) * 2016-01-12 2017-04-21 英業達股份有限公司 複雜可程式邏輯裝置之韌體之更新系統及其更新方法
CN107066707B (zh) * 2017-03-27 2019-07-30 中国科学院计算技术研究所 一种使用快照的可调试性设计追踪方法及装置
CN117112452B (zh) * 2023-08-24 2024-04-02 上海合芯数字科技有限公司 寄存器模拟配置方法、装置、计算机设备和存储介质
CN117113907B (zh) * 2023-10-17 2023-12-22 北京开源芯片研究院 一种验证方法、装置、电子设备及可读存储介质

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US5553275A (en) * 1993-07-13 1996-09-03 Intel Corporation Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock
US5659716A (en) * 1994-11-23 1997-08-19 Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US5761488A (en) * 1996-06-13 1998-06-02 International Business Machines Corporation Logic translation method for increasing simulation emulation efficiency
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WO2001001245A1 (en) * 1999-06-26 2001-01-04 Yang Sei Yang Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it
KR100710972B1 (ko) 1999-06-26 2007-04-24 양세양 혼합된 에뮬레이션과 시뮬레이션이 가능한 혼합 검증 장치및 이를 이용한 혼합 검증 방법
KR20010006983A (ko) 1999-06-26 2001-01-26 양세양 신속 프로토타이핑 장치와 그것의 입출력 탐침방법 및그것을 이용한 혼합 검증 방법
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US7398445B2 (en) * 2002-08-09 2008-07-08 Synplicity, Inc. Method and system for debug and test using replicated logic
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US7245684B2 (en) * 2003-05-09 2007-07-17 Hewlett-Packard Development Company, L.P. System and method for compensating for skew between a first clock signal and a second clock signal
DE10345150B3 (de) * 2003-09-29 2005-04-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren, Vorrichtung und System zum Analysieren digitaler Schaltungen
CN100447796C (zh) * 2005-09-29 2008-12-31 上海奇码数字信息有限公司 电路状态扫描链、数据采集系统和仿真验证方法
US7908574B2 (en) * 2007-05-09 2011-03-15 Synopsys, Inc. Techniques for use with automated circuit design and simulations

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