JP2010527476A5 - - Google Patents

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Publication number
JP2010527476A5
JP2010527476A5 JP2010507476A JP2010507476A JP2010527476A5 JP 2010527476 A5 JP2010527476 A5 JP 2010527476A5 JP 2010507476 A JP2010507476 A JP 2010507476A JP 2010507476 A JP2010507476 A JP 2010507476A JP 2010527476 A5 JP2010527476 A5 JP 2010527476A5
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Japan
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circuit
design
logic
description
module
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JP2010507476A
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Japanese (ja)
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JP2010527476A (ja
JP5432126B2 (ja
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Priority claimed from US12/117,693 external-priority patent/US8756557B2/en
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JP2010507476A 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術 Active JP5432126B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91701507P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91703307P 2007-05-09 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US60/917,033 2007-05-09
US60/917,024 2007-05-09
US12/117,693 2008-05-08
US12/117,693 US8756557B2 (en) 2007-05-09 2008-05-08 Techniques for use with automated circuit design and simulations
PCT/US2008/005989 WO2008140778A2 (en) 2007-05-09 2008-05-09 Transfer of emulator state to a hdl simulator

Publications (3)

Publication Number Publication Date
JP2010527476A JP2010527476A (ja) 2010-08-12
JP2010527476A5 true JP2010527476A5 (https=) 2011-06-23
JP5432126B2 JP5432126B2 (ja) 2014-03-05

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JP2010507476A Active JP5432126B2 (ja) 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術

Country Status (5)

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US (1) US8756557B2 (https=)
EP (1) EP2145271A2 (https=)
JP (1) JP5432126B2 (https=)
CN (1) CN101720464B (https=)
WO (1) WO2008140778A2 (https=)

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