JP5432126B2 - 自動回路設計及びシミュレーションに使用するための技術 - Google Patents

自動回路設計及びシミュレーションに使用するための技術 Download PDF

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JP5432126B2
JP5432126B2 JP2010507476A JP2010507476A JP5432126B2 JP 5432126 B2 JP5432126 B2 JP 5432126B2 JP 2010507476 A JP2010507476 A JP 2010507476A JP 2010507476 A JP2010507476 A JP 2010507476A JP 5432126 B2 JP5432126 B2 JP 5432126B2
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circuit
design
logic
clock
module
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JP2010527476A5 (https=
JP2010527476A (ja
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チュン キット ヌグ
リチャード シー メクスナー
マリオ ラルシュ
ケニス エス マケルヴェイン
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Synopsys Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2010507476A 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術 Active JP5432126B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91701507P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91703307P 2007-05-09 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US60/917,033 2007-05-09
US60/917,024 2007-05-09
US12/117,693 2008-05-08
US12/117,693 US8756557B2 (en) 2007-05-09 2008-05-08 Techniques for use with automated circuit design and simulations
PCT/US2008/005989 WO2008140778A2 (en) 2007-05-09 2008-05-09 Transfer of emulator state to a hdl simulator

Publications (3)

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JP2010527476A JP2010527476A (ja) 2010-08-12
JP2010527476A5 JP2010527476A5 (https=) 2011-06-23
JP5432126B2 true JP5432126B2 (ja) 2014-03-05

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JP2010507476A Active JP5432126B2 (ja) 2007-05-09 2008-05-09 自動回路設計及びシミュレーションに使用するための技術

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US (1) US8756557B2 (https=)
EP (1) EP2145271A2 (https=)
JP (1) JP5432126B2 (https=)
CN (1) CN101720464B (https=)
WO (1) WO2008140778A2 (https=)

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Also Published As

Publication number Publication date
WO2008140778A2 (en) 2008-11-20
JP2010527476A (ja) 2010-08-12
WO2008140778A3 (en) 2009-02-19
CN101720464A (zh) 2010-06-02
US8756557B2 (en) 2014-06-17
EP2145271A2 (en) 2010-01-20
WO2008140778A8 (en) 2009-05-07
US20080301601A1 (en) 2008-12-04
CN101720464B (zh) 2013-10-23

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