CN101720464B - 从仿真器状态至hdl模拟器的转换 - Google Patents

从仿真器状态至hdl模拟器的转换 Download PDF

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Publication number
CN101720464B
CN101720464B CN2008800230665A CN200880023066A CN101720464B CN 101720464 B CN101720464 B CN 101720464B CN 2008800230665 A CN2008800230665 A CN 2008800230665A CN 200880023066 A CN200880023066 A CN 200880023066A CN 101720464 B CN101720464 B CN 101720464B
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circuit
design
logic
clock
replica
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CN101720464A (zh
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C·K·额
R·C·迈克斯纳
M·拉罗歇
K·S·麦克尔文
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Synopsys Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
CN2008800230665A 2007-05-09 2008-05-09 从仿真器状态至hdl模拟器的转换 Active CN101720464B (zh)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US91701507P 2007-05-09 2007-05-09
US91702707P 2007-05-09 2007-05-09
US91702407P 2007-05-09 2007-05-09
US91703307P 2007-05-09 2007-05-09
US60/917,027 2007-05-09
US60/917,015 2007-05-09
US60/917,033 2007-05-09
US60/917,024 2007-05-09
US12/117,693 2008-05-08
US12/117,693 US8756557B2 (en) 2007-05-09 2008-05-08 Techniques for use with automated circuit design and simulations
PCT/US2008/005989 WO2008140778A2 (en) 2007-05-09 2008-05-09 Transfer of emulator state to a hdl simulator

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CN101720464A CN101720464A (zh) 2010-06-02
CN101720464B true CN101720464B (zh) 2013-10-23

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US (1) US8756557B2 (https=)
EP (1) EP2145271A2 (https=)
JP (1) JP5432126B2 (https=)
CN (1) CN101720464B (https=)
WO (1) WO2008140778A2 (https=)

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WO2016200718A1 (en) * 2015-06-06 2016-12-15 The Board Of Trustees Of The Leland Stanford Junior University System-level validation of systems-on-a-chip (soc)
WO2018023363A1 (zh) * 2016-08-02 2018-02-08 邹霞 一种故障仿真系统
KR102376725B1 (ko) * 2017-11-08 2022-03-21 삼성전자 주식회사 Rf 칩을 연결하는 전송선로의 위상 측정 방법 및 이를 위한 장치
US11258446B2 (en) 2020-04-29 2022-02-22 Apple Inc. No-enable setup clock gater based on pulse
CN112416054B (zh) * 2020-10-30 2022-11-08 山东浪潮科学研究院有限公司 一种用于测试fpga设计的跨时钟域信号同步的方法
CN117113890B (zh) * 2023-10-23 2024-02-06 深圳安森德半导体有限公司 一种cpu芯片设计方法及系统

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WO2008140778A2 (en) 2008-11-20
JP2010527476A (ja) 2010-08-12
WO2008140778A3 (en) 2009-02-19
CN101720464A (zh) 2010-06-02
US8756557B2 (en) 2014-06-17
EP2145271A2 (en) 2010-01-20
JP5432126B2 (ja) 2014-03-05
WO2008140778A8 (en) 2009-05-07
US20080301601A1 (en) 2008-12-04

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