JP2008544337A5 - - Google Patents

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Publication number
JP2008544337A5
JP2008544337A5 JP2008507729A JP2008507729A JP2008544337A5 JP 2008544337 A5 JP2008544337 A5 JP 2008544337A5 JP 2008507729 A JP2008507729 A JP 2008507729A JP 2008507729 A JP2008507729 A JP 2008507729A JP 2008544337 A5 JP2008544337 A5 JP 2008544337A5
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Japan
Prior art keywords
circuit
trigger
logic
representation
selecting
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JP2008507729A
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Japanese (ja)
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JP2008544337A (ja
JP4989629B2 (ja
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Priority claimed from US11/112,092 external-priority patent/US7213216B2/en
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Publication of JP2008544337A5 publication Critical patent/JP2008544337A5/ja
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Publication of JP4989629B2 publication Critical patent/JP4989629B2/ja
Anticipated expiration legal-status Critical
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JP2008507729A 2005-04-22 2006-04-12 複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム Expired - Lifetime JP4989629B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/112,092 US7213216B2 (en) 2002-08-09 2005-04-22 Method and system for debugging using replicated logic and trigger logic
US11/112,092 2005-04-22
PCT/US2006/013910 WO2006115812A2 (en) 2005-04-22 2006-04-12 Method and system for debugging using replicated logic and trigger logic

Publications (3)

Publication Number Publication Date
JP2008544337A JP2008544337A (ja) 2008-12-04
JP2008544337A5 true JP2008544337A5 (https=) 2009-05-28
JP4989629B2 JP4989629B2 (ja) 2012-08-01

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ID=37067503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008507729A Expired - Lifetime JP4989629B2 (ja) 2005-04-22 2006-04-12 複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム

Country Status (4)

Country Link
US (3) US7213216B2 (https=)
EP (1) EP1872288A2 (https=)
JP (1) JP4989629B2 (https=)
WO (1) WO2006115812A2 (https=)

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