WO2009037770A1 - メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 - Google Patents
メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 Download PDFInfo
- Publication number
- WO2009037770A1 WO2009037770A1 PCT/JP2007/068258 JP2007068258W WO2009037770A1 WO 2009037770 A1 WO2009037770 A1 WO 2009037770A1 JP 2007068258 W JP2007068258 W JP 2007068258W WO 2009037770 A1 WO2009037770 A1 WO 2009037770A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- latch circuit
- memory circuit
- data
- circuit
- reading out
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
Abstract
メモリ回路が、各々が入力されたデータがクロック信号のタイミングで書き込まれこれを保持する第1ラッチ回路および第2のラッチ回路と、ライトイネーブル信号が書き込み可を示す状態の際に前記第1のラッチ回路および第2のラッチ回路にデータを入力するデータ入力回路と、ライトイネーブル信号が書き込み不可を示す状態の際に前記第2のラッチ回路の保持データを前記第1のラッチ回路に入力するライトバック回路とよりなり、第2のラッチ回路は第1のラッチ回路に比してノイズに対する耐性が高められた構成とされてなる。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009533002A JP4888562B2 (ja) | 2007-09-20 | 2007-09-20 | メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 |
PCT/JP2007/068258 WO2009037770A1 (ja) | 2007-09-20 | 2007-09-20 | メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 |
US12/656,697 US8320195B2 (en) | 2007-09-20 | 2010-02-12 | Memory circuit and method of writing data to and reading data from memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/068258 WO2009037770A1 (ja) | 2007-09-20 | 2007-09-20 | メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/656,697 Continuation US8320195B2 (en) | 2007-09-20 | 2010-02-12 | Memory circuit and method of writing data to and reading data from memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009037770A1 true WO2009037770A1 (ja) | 2009-03-26 |
Family
ID=40467601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/068258 WO2009037770A1 (ja) | 2007-09-20 | 2007-09-20 | メモリ回路およびメモリ回路のデータ書き込み・読み出し方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8320195B2 (ja) |
JP (1) | JP4888562B2 (ja) |
WO (1) | WO2009037770A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8081538B2 (en) * | 2009-04-30 | 2011-12-20 | Hynix Semiconductor Inc. | Semiconductor memory device and driving method thereof |
JP2013008442A (ja) * | 2011-06-23 | 2013-01-10 | Thales | 高エネルギー粒子の衝突の影響を補正するメモリ素子 |
JP2013050318A (ja) * | 2011-08-30 | 2013-03-14 | Renesas Electronics Corp | 出力制御スキャンフリップフロップ、それを備えた半導体集積回路及び半導体集積回路の設計方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8588009B2 (en) * | 2011-09-28 | 2013-11-19 | International Business Machines Corporation | Circuit for memory cell recovery |
KR20130105100A (ko) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | 키퍼 회로 및 이를 포함하는 전자 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233215A (ja) * | 1988-07-22 | 1990-02-02 | Fujitsu Ltd | ラッチ回路 |
JPH04372214A (ja) * | 1991-06-21 | 1992-12-25 | Fujitsu Ltd | ラッチ回路 |
JP2007124343A (ja) * | 2005-10-28 | 2007-05-17 | Toshiba Corp | データ保持回路 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5016070A (en) * | 1989-06-30 | 1991-05-14 | Texas Instruments Incorporated | Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors |
US5327566A (en) * | 1991-07-12 | 1994-07-05 | Hewlett Packard Company | Stage saving and restoring hardware mechanism |
JPH06237151A (ja) * | 1993-02-10 | 1994-08-23 | Fujitsu Ltd | 半導体集積回路装置 |
US6028488A (en) * | 1996-11-08 | 2000-02-22 | Texas Instruments Incorporated | Digitally-controlled oscillator with switched-capacitor frequency selection |
US5860160A (en) * | 1996-12-18 | 1999-01-12 | Cypress Semiconductor Corp. | High speed FIFO mark and retransmit scheme using latches and precharge |
US6696873B2 (en) * | 1999-12-23 | 2004-02-24 | Intel Corporation | Single event upset hardened latch |
US6864733B2 (en) * | 2003-05-29 | 2005-03-08 | Intel Corporation | Data-enabled static flip-flop circuit with no extra forward-path delay penalty |
US6826090B1 (en) * | 2003-06-05 | 2004-11-30 | International Business Machines Corporation | Apparatus and method for a radiation resistant latch |
US7278074B2 (en) * | 2005-01-26 | 2007-10-02 | Intel Corporation | System and shadow circuits with output joining circuit |
US7506230B2 (en) * | 2005-02-03 | 2009-03-17 | International Business Machines Corporation | Transient noise detection scheme and apparatus |
US7415645B2 (en) * | 2005-07-28 | 2008-08-19 | International Business Machines Corporation | Method and apparatus for soft-error immune and self-correcting latches |
JP5223302B2 (ja) * | 2007-11-08 | 2013-06-26 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4372214B1 (ja) | 2008-09-29 | 2009-11-25 | キヤノン株式会社 | カラー電子写真画像形成装置 |
-
2007
- 2007-09-20 WO PCT/JP2007/068258 patent/WO2009037770A1/ja active Application Filing
- 2007-09-20 JP JP2009533002A patent/JP4888562B2/ja not_active Expired - Fee Related
-
2010
- 2010-02-12 US US12/656,697 patent/US8320195B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233215A (ja) * | 1988-07-22 | 1990-02-02 | Fujitsu Ltd | ラッチ回路 |
JPH04372214A (ja) * | 1991-06-21 | 1992-12-25 | Fujitsu Ltd | ラッチ回路 |
JP2007124343A (ja) * | 2005-10-28 | 2007-05-17 | Toshiba Corp | データ保持回路 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8081538B2 (en) * | 2009-04-30 | 2011-12-20 | Hynix Semiconductor Inc. | Semiconductor memory device and driving method thereof |
JP2013008442A (ja) * | 2011-06-23 | 2013-01-10 | Thales | 高エネルギー粒子の衝突の影響を補正するメモリ素子 |
JP2013050318A (ja) * | 2011-08-30 | 2013-03-14 | Renesas Electronics Corp | 出力制御スキャンフリップフロップ、それを備えた半導体集積回路及び半導体集積回路の設計方法 |
Also Published As
Publication number | Publication date |
---|---|
US8320195B2 (en) | 2012-11-27 |
US20100149885A1 (en) | 2010-06-17 |
JPWO2009037770A1 (ja) | 2011-01-06 |
JP4888562B2 (ja) | 2012-02-29 |
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