JP4989629B2 - 複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム - Google Patents

複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム Download PDF

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JP4989629B2
JP4989629B2 JP2008507729A JP2008507729A JP4989629B2 JP 4989629 B2 JP4989629 B2 JP 4989629B2 JP 2008507729 A JP2008507729 A JP 2008507729A JP 2008507729 A JP2008507729 A JP 2008507729A JP 4989629 B2 JP4989629 B2 JP 4989629B2
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circuit
logic
trigger
representation
processing system
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JP2008544337A (ja
JP2008544337A5 (https=
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チュン キット ング
マリオ ラルーシュ
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2008507729A 2005-04-22 2006-04-12 複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム Expired - Lifetime JP4989629B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/112,092 US7213216B2 (en) 2002-08-09 2005-04-22 Method and system for debugging using replicated logic and trigger logic
US11/112,092 2005-04-22
PCT/US2006/013910 WO2006115812A2 (en) 2005-04-22 2006-04-12 Method and system for debugging using replicated logic and trigger logic

Publications (3)

Publication Number Publication Date
JP2008544337A JP2008544337A (ja) 2008-12-04
JP2008544337A5 JP2008544337A5 (https=) 2009-05-28
JP4989629B2 true JP4989629B2 (ja) 2012-08-01

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Family Applications (1)

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JP2008507729A Expired - Lifetime JP4989629B2 (ja) 2005-04-22 2006-04-12 複製ロジック及びトリガロジックを用いたデバッグのための方法及びシステム

Country Status (4)

Country Link
US (3) US7213216B2 (https=)
EP (1) EP1872288A2 (https=)
JP (1) JP4989629B2 (https=)
WO (1) WO2006115812A2 (https=)

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US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
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US7882473B2 (en) * 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
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US8122410B2 (en) 2008-11-05 2012-02-21 International Business Machines Corporation Specifying and validating untimed nets
US8381038B2 (en) * 2009-05-26 2013-02-19 Hitachi, Ltd. Management server and management system
US8638792B2 (en) * 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
US8966319B2 (en) * 2011-02-22 2015-02-24 Apple Inc. Obtaining debug information from a flash memory device
US9158661B2 (en) 2012-02-15 2015-10-13 Apple Inc. Enhanced debugging for embedded devices
US9495492B1 (en) * 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US9430358B1 (en) * 2015-06-23 2016-08-30 Ca, Inc. Debugging using program state definitions
US9672135B2 (en) 2015-11-03 2017-06-06 Red Hat, Inc. System, method and apparatus for debugging of reactive applications
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Also Published As

Publication number Publication date
JP2008544337A (ja) 2008-12-04
US20100122132A1 (en) 2010-05-13
WO2006115812A2 (en) 2006-11-02
EP1872288A2 (en) 2008-01-02
US20060190860A1 (en) 2006-08-24
US7213216B2 (en) 2007-05-01
US7665046B2 (en) 2010-02-16
WO2006115812A3 (en) 2007-03-22
US8392859B2 (en) 2013-03-05
US20070186195A1 (en) 2007-08-09

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