JP2010522426A - ハイブリッド基板の製造方法 - Google Patents

ハイブリッド基板の製造方法 Download PDF

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Publication number
JP2010522426A
JP2010522426A JP2009554093A JP2009554093A JP2010522426A JP 2010522426 A JP2010522426 A JP 2010522426A JP 2009554093 A JP2009554093 A JP 2009554093A JP 2009554093 A JP2009554093 A JP 2009554093A JP 2010522426 A JP2010522426 A JP 2010522426A
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JP
Japan
Prior art keywords
substrate
silicon
bonding
manufacturing
species
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2009554093A
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English (en)
Japanese (ja)
Inventor
コンスタンティン ブールデル，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2010522426A publication Critical patent/JP2010522426A/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Laminated Bodies (AREA)
JP2009554093A 2007-03-20 2008-02-26 ハイブリッド基板の製造方法 Withdrawn JP2010522426A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0702004A FR2914110B1 (fr) 2007-03-20 2007-03-20 Procede de fabrication d'un substrat hybride
PCT/IB2008/000567 WO2008114107A2 (fr) 2007-03-20 2008-02-26 Procédé de fabrication d'un substrat hybride

Publications (1)

Publication Number Publication Date
JP2010522426A true JP2010522426A (ja) 2010-07-01

Family

ID=38529493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009554093A Withdrawn JP2010522426A (ja) 2007-03-20 2008-02-26 ハイブリッド基板の製造方法

Country Status (6)

Country Link
EP (1) EP2137755A2 (fr)
JP (1) JP2010522426A (fr)
KR (1) KR101428614B1 (fr)
CN (1) CN101568992B (fr)
FR (1) FR2914110B1 (fr)
WO (1) WO2008114107A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016508291A (ja) * 2012-12-28 2016-03-17 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法
JP2019511834A (ja) * 2016-02-16 2019-04-25 ジーレイ スイッツァーランド エスアー 接合インターフェースを横断する電荷輸送のための構造、システムおよび方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2938117B1 (fr) * 2008-10-31 2011-04-15 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree
US20130154049A1 (en) * 2011-06-22 2013-06-20 George IMTHURN Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2701709B2 (ja) * 1993-02-16 1998-01-21 株式会社デンソー ２つの材料の直接接合方法及び材料直接接合装置
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
CN1260907A (zh) * 1997-06-19 2000-07-19 旭化成工业株式会社 Soi衬底及其制造方法和半导体器件及其制造方法
CA2482258A1 (fr) * 2001-04-17 2002-10-24 California Institute Of Technology Procede utilisant un transfert de la couche au germanium au si pour applications photovoltaiques, et heterostructures realisees par ce procede
FR2834123B1 (fr) * 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report
FR2835097B1 (fr) * 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
KR100504163B1 (ko) 2002-09-12 2005-07-27 주성엔지니어링(주) Ｓｏｉ 기판 및 그 제조방법
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
FR2868599B1 (fr) 2004-03-30 2006-07-07 Soitec Silicon On Insulator Traitement chimique optimise de type sc1 pour le nettoyage de plaquettes en materiau semiconducteur
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016508291A (ja) * 2012-12-28 2016-03-17 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法
JP2018085536A (ja) * 2012-12-28 2018-05-31 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法
JP2019511834A (ja) * 2016-02-16 2019-04-25 ジーレイ スイッツァーランド エスアー 接合インターフェースを横断する電荷輸送のための構造、システムおよび方法

Also Published As

Publication number Publication date
FR2914110A1 (fr) 2008-09-26
CN101568992A (zh) 2009-10-28
EP2137755A2 (fr) 2009-12-30
WO2008114107A3 (fr) 2008-12-11
KR20090122176A (ko) 2009-11-26
WO2008114107A2 (fr) 2008-09-25
FR2914110B1 (fr) 2009-06-05
KR101428614B1 (ko) 2014-08-11
CN101568992B (zh) 2011-03-30

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