JP2010192784A - Wiring substrate, probe card, and electronic device - Google Patents

Wiring substrate, probe card, and electronic device Download PDF

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JP2010192784A
JP2010192784A JP2009037344A JP2009037344A JP2010192784A JP 2010192784 A JP2010192784 A JP 2010192784A JP 2009037344 A JP2009037344 A JP 2009037344A JP 2009037344 A JP2009037344 A JP 2009037344A JP 2010192784 A JP2010192784 A JP 2010192784A
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wiring
layer
insulating resin
ceramic
resin layer
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Hitoshi Tega
仁 手賀
Sadakatsu Yoshida
定功 吉田
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability wiring substrate with reduced possibility of wire fracture, even if a thermal stress is generated between an insulating resin layer and a ceramic wiring substrate. <P>SOLUTION: This wiring substrate includes a ceramic wiring substrate 1, a plurality of insulating resin layers 2 laminated on the upper surface of the ceramic wiring substrate 1, a plurality of wiring layers 3 on the upper surface of the respective insulating resin layers 2, via conductors 4 that connects the wiring layers 3, 3 disposed on the upper side and lower side of the insulating resin layer 2, and a through conductor 6 that reaches from the upper surface of the lowest layer of the insulating resin layer 2 to the inside of the ceramic wiring substrate 1 and connects the wiring layer 3 of the upper surface of the lowest layer of the insulating resin layer 2 with an external wiring 7a of the upper surface of the ceramic wiring substrate 1. Since there is no connection portion between the end surface of the via conductor 4 with a comparatively weak connecting strength and the external wiring 7a in the interface between the ceramic wiring substrate 1 and the lowest layer of the insulating resin layer 2, whose thermal stress tends to increase, the possibility of wire fracture is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、プローブカードに用いられる配線基板または半導体素子や圧電振動子等の電子部品を搭載するための配線基板、ならびにそのような配線基板を用いたプローブカードおよび電子装置に関する。   The present invention relates to a wiring board used for a probe card or a wiring board for mounting electronic components such as a semiconductor element and a piezoelectric vibrator, and a probe card and an electronic apparatus using such a wiring board.

近年、電子機器の小型化・高密度化に伴い、電子機器に使用される半導体素子のみならず、その半導体素子が搭載されるパッケージや配線基板、あるいは半導体素子の電気的な検査をするためのプローブカードに対しても配線の微細化および高密度化が要求されている。また、半導体素子の高速化に伴って高周波信号の伝送が可能であることも求められ、プローブカードに対しては平坦性に優れていることも求められている。   In recent years, along with miniaturization and higher density of electronic devices, not only semiconductor elements used in electronic devices but also packages, wiring boards on which the semiconductor elements are mounted, or electrical inspection of semiconductor elements The probe card is also required to have finer wiring and higher density. In addition, it is required that a high-frequency signal can be transmitted with an increase in the speed of the semiconductor element, and the probe card is also required to have excellent flatness.

このような要求にこたえるものとして、微細なパターン加工が可能であり、平坦性および高周波特性に優れた基板として、研磨加工により平坦化したセラミック基板上に薄膜導体と薄膜の絶縁層とを複数層形成した多層配線部を形成した、いわゆるビルドアップ方式の配線基板がある(例えば、特許文献1を参照。)。図6は、従来の配線基板の一例を示す断面図である。従来の配線基板は、複数のセラミック絶縁層18と内部配線15および外部配線17とから成るセラミック配線基板11の上面に絶縁樹脂層12と配線層13とを交互に積層して形成されていた。そして、絶縁樹脂層12の上下に位置する配線層13同士、および最下層の絶縁樹脂層12の上面の配線層13とセラミック配線基板11の上面の外部配線17aとはビア導体14により接続されているものであった。   In order to meet these requirements, fine patterning is possible, and as a substrate with excellent flatness and high frequency characteristics, a thin film conductor and a thin insulating layer are formed on a ceramic substrate flattened by polishing. There is a so-called build-up type wiring board in which the formed multilayer wiring portion is formed (see, for example, Patent Document 1). FIG. 6 is a cross-sectional view showing an example of a conventional wiring board. The conventional wiring board is formed by alternately laminating insulating resin layers 12 and wiring layers 13 on the upper surface of a ceramic wiring board 11 composed of a plurality of ceramic insulating layers 18, internal wirings 15 and external wirings 17. The wiring layers 13 positioned above and below the insulating resin layer 12, and the wiring layer 13 on the upper surface of the lowermost insulating resin layer 12 and the external wiring 17a on the upper surface of the ceramic wiring substrate 11 are connected by via conductors 14. It was a thing.

特開2004−214586号公報Japanese Patent Laid-Open No. 2004-214586

しかしながら、従来の配線基板は、最下層の絶縁樹脂層12に形成されたビア導体14とセラミック配線基板11の上面に形成された外部配線17aとの接続部に、絶縁樹脂層12の熱膨張係数とセラミック配線基板11の熱膨張係数の差による熱応力が加わりやすいものであった。これは、セラミック配線基板11の上面の外部配線17aはその厚みが薄く、絶縁樹脂層12に比べてセラミック配線基板11のセラミック絶縁層18との接合強度が高いので、熱膨張の挙動は、セラミック配線基板11(セラミック絶縁層18)の挙動に準じた挙動を示し、ビア導体14は絶縁樹脂層12内に形成されているので絶縁樹脂層12の挙動に準じた挙動を示すことから、最下層の絶縁樹脂層12に形成されたビア導体14とセラミック配線基板11の上面に形成された外部配線17aとの接合界面の位置が、セラミック配線基板11と絶縁樹脂層12との間の熱応力が大きくなる位置と実質的に一致するからである。   However, the conventional wiring board has a thermal expansion coefficient of the insulating resin layer 12 at the connection portion between the via conductor 14 formed in the lowermost insulating resin layer 12 and the external wiring 17a formed on the upper surface of the ceramic wiring board 11. Thermal stress due to the difference in thermal expansion coefficient between the ceramic wiring board 11 and the ceramic wiring board 11 was easily applied. This is because the external wiring 17a on the upper surface of the ceramic wiring board 11 is thin and the bonding strength between the ceramic wiring board 11 and the ceramic insulating layer 18 is higher than that of the insulating resin layer 12. Since the behavior according to the behavior of the wiring substrate 11 (ceramic insulating layer 18) is shown and the via conductor 14 is formed in the insulating resin layer 12, the behavior according to the behavior of the insulating resin layer 12 is shown. The position of the bonding interface between the via conductor 14 formed in the insulating resin layer 12 and the external wiring 17a formed on the upper surface of the ceramic wiring board 11 is caused by the thermal stress between the ceramic wiring board 11 and the insulating resin layer 12 This is because it substantially coincides with the position where it increases.

このような従来の配線基板に対して、配線層13のさらなる微細化が求められ、ビア導体14のセラミック配線基板11の上面の外部配線17aとの接続部が、例えば直径50μm程度以下の小さいものとなると、ビア導体14とセラミック配線基板11の上面に形成された外部配線17aとの接続強度が小さくなる。また、半導体素子の電気的な検査はウエハ上の多数の半導体素子をプローブカードにて同時に行なうが、半導体素子のコスト低下のためにこのウエハの大きさが大きくなると、プローブカードも大型にする必要があり、プローブカード用の配線基板が大型になると、ビア導体14のセラミック配線基板11の上面の外部配線17aとの接続部に加わる熱応力も大きいものとなる。そのため、最下層の絶縁樹脂層12のビア導体14とセラミック配線基板11の上面の外部配線17aとの間で断線しやすくなるという問題があった。   With respect to such a conventional wiring board, further miniaturization of the wiring layer 13 is required, and the connection portion of the via conductor 14 with the external wiring 17a on the upper surface of the ceramic wiring board 11 is small, for example, about 50 μm or less in diameter. Then, the connection strength between the via conductor 14 and the external wiring 17a formed on the upper surface of the ceramic wiring board 11 is reduced. In addition, the electrical inspection of semiconductor elements is performed simultaneously with a probe card on a large number of semiconductor elements on the wafer. However, if the size of the wafer increases to reduce the cost of the semiconductor elements, the probe card must also be enlarged. When the wiring board for the probe card becomes large, the thermal stress applied to the connection portion with the external wiring 17a on the upper surface of the ceramic wiring board 11 of the via conductor 14 becomes large. Therefore, there has been a problem that it is easy to break between the via conductor 14 of the lowermost insulating resin layer 12 and the external wiring 17a on the upper surface of the ceramic wiring board 11.

本発明は上記課題を解決するためになされたものであり、その目的は、絶縁樹脂層12とセラミック配線基板11との間に熱応力発生したとしても、配線が破断してしまう可能性がより低減された高信頼性の配線基板を提供することにある。   The present invention has been made to solve the above-described problems, and the purpose of the present invention is to increase the possibility of the wiring breaking even if thermal stress is generated between the insulating resin layer 12 and the ceramic wiring board 11. An object is to provide a reduced and highly reliable wiring board.

本発明の配線基板は、セラミック配線基板と、該セラミック配線基板の上面に積層された複数の絶縁樹脂層と、複数の該絶縁樹脂層それぞれの上面の配線層と、前記絶縁樹脂層の上下に位置する前記配線層間を接続するビア導体と、セラミック配線基板内から最下層の前記絶縁樹脂層の上面に至り、セラミック配線基板の表面配線層と最下層の前記絶縁樹脂層の上面の前記配線層とを接続する貫通導体とを具備することを特徴とするものである。   The wiring board of the present invention includes a ceramic wiring board, a plurality of insulating resin layers laminated on the upper surface of the ceramic wiring board, a wiring layer on the upper surface of each of the plurality of insulating resin layers, and above and below the insulating resin layer. Via conductors connecting between the wiring layers positioned, and reaching the upper surface of the lowermost insulating resin layer from within the ceramic wiring substrate, and the wiring layers on the upper surface of the insulating wiring layer of the ceramic wiring substrate and the lowermost insulating resin layer And a through conductor that connects the two to each other.

本発明の配線基板は、上記構成において、前記貫通導体は最下層の前記絶縁樹脂層の上面から最下層の前記絶縁樹脂層の上面の配線層内に突出していることを特徴とするものである。   In the above configuration, the wiring board of the present invention is characterized in that the through conductor protrudes from the upper surface of the lowermost insulating resin layer into the wiring layer on the upper surface of the lowermost insulating resin layer. .

本発明のプローブカードは、上記構成の本発明の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続されたプローブピンとを具備することを特徴とするものである。   The probe card of the present invention comprises the wiring board of the present invention having the above-described configuration and probe pins connected to the wiring layer on the upper surface of the uppermost insulating resin layer.

本発明の電子装置は、上記構成の本発明の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続された電子部品とを具備することを特徴とするものである。   An electronic device of the present invention includes the wiring board of the present invention having the above-described configuration and an electronic component connected to the wiring layer on the upper surface of the uppermost insulating resin layer.

本発明の配線基板によれば、最下層の絶縁樹脂層の上面からセラミック配線基板内に至り、最下層の絶縁樹脂層の上面の配線層とセラミック配線基板の上面の外部配線とを接続する貫通導体とを具備することから、熱応力が大きくなるセラミック配線基板と最下層の絶縁樹脂層との界面に、比較的接続強度の弱いビア導体の端面と外部配線との接続部を有さず、貫通導体は熱応力によりせん断破壊され難いので、配線が破断してしまう可能性が低減された高信頼性の配線基板となる。   According to the wiring board of the present invention, the penetration extends from the upper surface of the lowermost insulating resin layer into the ceramic wiring board and connects the wiring layer on the upper surface of the lowermost insulating resin layer and the external wiring on the upper surface of the ceramic wiring board. Since it has a conductor, the interface between the ceramic wiring board and the lowermost insulating resin layer where the thermal stress is increased does not have a connection portion between the end face of the via conductor having relatively low connection strength and the external wiring, Since the through conductor is hardly sheared by thermal stress, it becomes a highly reliable wiring board in which the possibility that the wiring breaks is reduced.

本発明の配線基板によれば、上記構成において、貫通導体が最下層の絶縁樹脂層の上面から最下層の絶縁樹脂層の上面の配線層内に突出しているときには、絶縁樹脂層とセラミック配線基板との界面に最も近い貫通導体と最下層の絶縁樹脂層の上面の配線層との接続部において、貫通導体と最下層の絶縁樹脂層の上面の配線層との接続界面に平行な方向に働く熱応力に対して、貫通導体と最下層の絶縁樹脂層の上面の配線層との接続面積が大きく、かつ貫通導体の突出した部分の側面でも応力を受ける構造となっているので、この接続部の接続強度が高いものとなり、配線が破断してしまう可能性がより低減された高信頼性の配線基板となる。   According to the wiring substrate of the present invention, in the above configuration, when the through conductor protrudes from the upper surface of the lowermost insulating resin layer into the wiring layer on the upper surface of the lowermost insulating resin layer, the insulating resin layer and the ceramic wiring substrate Acts in a direction parallel to the connection interface between the through conductor and the upper wiring layer of the lowermost insulating resin layer at the connection portion between the through conductor closest to the interface with the upper wiring layer of the lowermost insulating resin layer Since the connection area between the through conductor and the wiring layer on the upper surface of the lowermost insulating resin layer is large against thermal stress, the side of the protruding part of the through conductor is also subjected to stress. This results in a high connection strength and a highly reliable wiring board in which the possibility of the wiring breaking is further reduced.

本発明のプローブカードによれば、上記構成の本発明の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続されたプローブピンとを具備することから、大型のウエハに対応する大型のものであっても、温度変化により配線が破断してしまう可能性が低減された高信頼性のプローブカードとなる。   According to the probe card of the present invention, the wiring board of the present invention having the above-described configuration and the probe pin connected to the wiring layer on the upper surface of the uppermost insulating resin layer are provided. Even if it is a thing, it becomes a highly reliable probe card by which possibility that the wiring will fracture | rupture by a temperature change was reduced.

本発明の電子装置によれば、上記構成の本発明の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続された電子部品とを具備することから、温度変化により配線が破断してしまう可能性が小さいので、微細配線の半導体素子のようなより小型の電子部品が搭載されたより小型で高信頼性の電子装置となる。   According to the electronic device of the present invention, since the wiring board of the present invention having the above configuration and the electronic component connected to the wiring layer on the upper surface of the uppermost insulating resin layer are provided, the wiring breaks due to a temperature change. Therefore, it is possible to obtain a smaller and more reliable electronic device on which a smaller electronic component such as a semiconductor element with fine wiring is mounted.

本発明の配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the wiring board of this invention. 図1のA部を拡大して示す断面図である。It is sectional drawing which expands and shows the A section of FIG. 本発明の配線基板の他の例の要部を拡大して示す断面図である。It is sectional drawing which expands and shows the principal part of the other example of the wiring board of this invention. 本発明の配線基板の他の例の要部を拡大して示す断面図である。It is sectional drawing which expands and shows the principal part of the other example of the wiring board of this invention. 本発明の配線基板の他の例の要部を拡大して示す断面図である。It is sectional drawing which expands and shows the principal part of the other example of the wiring board of this invention. 従来の配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the conventional wiring board.

本発明の配線基板ならびにそれを用いたプローブカードおよび電子装置について添付の図面を参照しつつ詳細に説明する。図1は、本発明の配線基板の実施の形態の一例を示す断面図である。図2は、図1のA部を拡大して示す断面図である。図3〜図5は、図2と同様の本発明の配線基板の他の例の要部を拡大して示す断面図である。図1〜図5において、1はセラミック配線基板、2は絶縁樹脂層、3は絶縁樹脂層2の上に形成された配線層、4は絶縁樹脂層2を貫通して形成されたビア導体、5はセラミック配線基板1の内部配線、6は貫通導体、7はセラミック配線基板1の表面の外部配線、7aはセラミック配線基板1の上面の外部配線、8はセラミック配線基板1のセラミック絶縁層である。図1に示す例では、配線基板の最表面の配線層3は4つで、絶縁樹脂層2は2層、セラミック配線基板1のセラミック絶縁層8も3層と簡略化した例を示している。配線基板に搭載する電子部品の端子の数や、プローブカードで検査するウエハ上の半導体素子の数および半導体素子の端子の数、およびそれらの配置に応じて、絶縁樹脂層2,配線層3,ビア導体4,内部配線5,貫通導体6,外部配線7の大きさや配置が設定される。   A wiring board of the present invention, a probe card using the wiring board, and an electronic device will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is an enlarged cross-sectional view showing a portion A of FIG. 3 to 5 are cross-sectional views showing, in an enlarged manner, main portions of other examples of the wiring board of the present invention similar to FIG. 1 to 5, 1 is a ceramic wiring board, 2 is an insulating resin layer, 3 is a wiring layer formed on the insulating resin layer 2, 4 is a via conductor formed through the insulating resin layer 2, 5 is an internal wiring of the ceramic wiring board 1, 6 is a through conductor, 7 is an external wiring on the surface of the ceramic wiring board 1, 7a is an external wiring on the upper surface of the ceramic wiring board 1, and 8 is a ceramic insulating layer of the ceramic wiring board 1. is there. In the example shown in FIG. 1, the wiring board 3 on the outermost surface of the wiring board has four wiring layers, the insulating resin layer 2 has two layers, and the ceramic insulating layer 8 of the ceramic wiring board 1 has three layers. . Depending on the number of terminals of electronic components mounted on the wiring board, the number of semiconductor elements on the wafer to be inspected by the probe card, the number of terminals of the semiconductor elements, and their arrangement, the insulating resin layer 2, the wiring layer 3, The size and arrangement of the via conductor 4, the internal wiring 5, the through conductor 6, and the external wiring 7 are set.

本発明の配線基板は、図1〜図5に示す例のように、セラミック配線基板1と、セラミック配線基板1の上面に積層された複数の絶縁樹脂層2と、複数の絶縁樹脂層2それぞれの上面の配線層3と、絶縁樹脂層2の上下に位置する配線層3・3間を接続するビア導体4と、最下層の絶縁樹脂層2の上面からセラミック配線基板1内に至り、最下層の絶縁樹脂層2の上面の配線層3とセラミック配線基板1の上面の外部配線7aとを接続する貫通導体6とを具備することを特徴とするものである。このような構成としたことから、熱応力が大きくなるセラミック配線基板1と最下層の絶縁樹脂層2との界面に、比較的接続強度の弱いビア導体4の端面と外部配線7aとの接続部を有さず、貫通導体6は熱応力によりせん断破壊され難いので、配線が破断してしまう可能性が低減された高信頼性の配線基板となる。また、図1〜図5に示す例のように、貫通導体6は、セラミック配線基板1の内部配線5とはセラミック配線基板1の上面の外部配線7aを介して接続しているので、貫通導体6の寸法やセラミック配線基板1内に埋設された部分の深さをセラミック配線基板1の内部配線5の大きさや配置を考慮せずに決めることができるので、設計の自由度の高い配線基板となる。   The wiring board of the present invention includes a ceramic wiring board 1, a plurality of insulating resin layers 2 laminated on the upper surface of the ceramic wiring board 1, and a plurality of insulating resin layers 2, as in the examples shown in FIGS. The upper wiring layer 3, the via conductors 4 connecting the wiring layers 3 and 3 positioned above and below the insulating resin layer 2, and the lowermost insulating resin layer 2 from the upper surface into the ceramic wiring substrate 1, A through conductor 6 for connecting the wiring layer 3 on the upper surface of the lower insulating resin layer 2 and the external wiring 7a on the upper surface of the ceramic wiring substrate 1 is provided. Because of such a configuration, a connection portion between the end face of the via conductor 4 having a relatively low connection strength and the external wiring 7a is formed at the interface between the ceramic wiring substrate 1 and the lowermost insulating resin layer 2 where thermal stress increases. Since the through conductors 6 are not easily broken by thermal stress, the wiring conductor 6 is a highly reliable wiring board that is less likely to break the wiring. 1 to 5, the through conductor 6 is connected to the internal wiring 5 of the ceramic wiring board 1 through the external wiring 7a on the upper surface of the ceramic wiring board 1, so that the through conductor 6 and the depth of the portion embedded in the ceramic wiring board 1 can be determined without considering the size and arrangement of the internal wiring 5 of the ceramic wiring board 1. Become.

また、本発明の配線基板は、図3に示す例のように、上記構成において、貫通導体6は最下層の絶縁樹脂層2の上面から最下層の絶縁樹脂層2の上面に位置する配線層3内に突出していることが好ましい。このような構成としたときには、絶縁樹脂層2とセラミック配線基板1との界面に最も近い貫通導体6と最下層の絶縁樹脂層2の上面の配線層3との接続部において、貫通導体6と最下層の絶縁樹脂層2の上面の配線層3との接続界面に平行な方向に働く熱応力に対して、貫通導体6と最下層の絶縁樹脂層2の上面の配線層3との接続面積が大きく、かつ貫通導体6の突出した部分の側面でも応力を受ける構造となっているので、この接続部の接続強度が高いものとなり、配線が破断してしまう可能性がより低減された高信頼性の配線基板となる。   Further, as in the example shown in FIG. 3, in the wiring board of the present invention, in the above configuration, the through conductor 6 is a wiring layer located on the upper surface of the lowermost insulating resin layer 2 from the upper surface of the lowermost insulating resin layer 2. It is preferable that it protrudes into 3. In such a configuration, the through conductor 6 is connected to the through conductor 6 closest to the interface between the insulating resin layer 2 and the ceramic wiring substrate 1 and the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2. The connection area between the through conductor 6 and the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2 against thermal stress acting in a direction parallel to the connection interface with the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2 Since the structure is large and the side surface of the protruding portion of the through conductor 6 is also subjected to stress, the connection strength of the connection portion is high, and the possibility that the wiring breaks is further reduced. Wiring board.

本発明のプローブカードは、上記構成の本発明の配線基板と、最上層の絶縁樹脂層2の上面の配線層3に接続されたプローブピンとを具備することを特徴とするものである。このことにより、大型のウエハに対応する大型のものであっても、温度変化により配線が破断してしまう可能性が低減された高信頼性のプローブカードとなる。   The probe card of the present invention comprises the wiring board of the present invention configured as described above and probe pins connected to the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2. As a result, even a large card corresponding to a large wafer is a highly reliable probe card in which the possibility that the wiring breaks due to a temperature change is reduced.

また、本発明の電子装置は、上記構成の本発明の配線基板と、最上層の絶縁樹脂層2の上面の配線層3に接続された電子部品とを具備することを特徴とするものである。このことにより、大型のウエハに対応する大型のものであっても、温度変化により配線が破断してしまう可能性が低減された高信頼性のプローブカードとなる。   An electronic device according to the present invention includes the above-configured wiring board according to the present invention and an electronic component connected to the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2. . As a result, even a large card corresponding to a large wafer is a highly reliable probe card in which the possibility that the wiring breaks due to a temperature change is reduced.

セラミック配線基板1は、セラミックスから成る絶縁基体とその表面に形成された外部配線7・7aおよび内部に形成された内部配線5を有する。絶縁基体を図1〜図5に示す例のように複数のセラミック絶縁層8で構成し、内部配線5を展開することでセラミック配線基板1の下面の外部配線7の間隔を大きくすることができる。絶縁樹脂層2の上面の配線層3の間隔が大きい場合は、内部配線5を展開する必要がないので、セラミック絶縁層8は1層で構成してもよい。セラミック配線基板1の下面の外部配線7は配線基板を外部回路に接続するためのものであり、セラミック配線基板1の上面の外部配線7aはその上の絶縁樹脂層2に形成されたビア導体4および配線層3と貫通導体6を介して接続するためのものである。内部配線5は、セラミック配線基板1の下面の外部配線7と絶縁樹脂層2に形成された配線層3等とをセラミック配線基板1の上面の外部配線7aを介して電気的に接続するためのものであり、セラミック絶縁層8・8間の内部配線層と、セラミック絶縁層8を貫通して内部配線層間や内部配線層と外部配線7とを接続する内部貫通導体とがある。   The ceramic wiring board 1 has an insulating base made of ceramics, external wirings 7 and 7a formed on the surface thereof, and internal wiring 5 formed inside. As shown in the examples shown in FIGS. 1 to 5, the insulating base is composed of a plurality of ceramic insulating layers 8, and by expanding the internal wiring 5, the interval between the external wirings 7 on the lower surface of the ceramic wiring substrate 1 can be increased. . When the interval between the wiring layers 3 on the upper surface of the insulating resin layer 2 is large, it is not necessary to develop the internal wiring 5, so the ceramic insulating layer 8 may be composed of one layer. The external wiring 7 on the lower surface of the ceramic wiring board 1 is for connecting the wiring board to an external circuit, and the external wiring 7a on the upper surface of the ceramic wiring board 1 is a via conductor 4 formed in the insulating resin layer 2 thereon. In addition, the wiring layer 3 and the through conductor 6 are connected to each other. The internal wiring 5 is used to electrically connect the external wiring 7 on the lower surface of the ceramic wiring substrate 1 and the wiring layer 3 formed on the insulating resin layer 2 via the external wiring 7a on the upper surface of the ceramic wiring substrate 1. There are an internal wiring layer between the ceramic insulating layers 8 and 8 and an internal through conductor that passes through the ceramic insulating layer 8 and connects the internal wiring layer and the internal wiring layer and the external wiring 7.

セラミック配線基板1のセラミック絶縁層8は、酸化アルミニウム(アルミナ:Al)質焼結体,窒化アルミニウム(AlN)質焼結体,炭化珪素(SiC)質焼結体,ムライト質焼結体,ガラスセラミックス等のセラミックスから成るものである。プローブカードに用いる場合は、熱膨張係数がウエハを形成するシリコン(Si)に近い、酸化アルミニウム(Al)質焼結体またはガラスセラミックスが好ましい。セラミック絶縁層8がこのようなセラミックスから成るものであると、配線基板上にプローブ端子を形成する際に、プローブ端子やプローブ端子の接合部に加わる、プローブ端子とともに接合されるウエハと配線基板との熱膨張差による熱応力が比較的小さなものとなるので好ましい。また、プローブカードとして用いた場合に、半導体素子の電気特性の測定時における熱負荷に対する熱変形を有効に防止でき、さらに、高い熱伝達性により内部に熱を滞留させることがない。 The ceramic insulating layer 8 of the ceramic wiring substrate 1 includes an aluminum oxide (alumina: Al 2 O 3 ) sintered body, an aluminum nitride (AlN) sintered body, a silicon carbide (SiC) sintered body, and a mullite sintered body. Body and ceramics such as glass ceramics. When used for a probe card, an aluminum oxide (Al 2 O 3 ) sintered material or glass ceramics having a thermal expansion coefficient close to that of silicon (Si) forming a wafer is preferable. When the ceramic insulating layer 8 is made of such ceramics, when the probe terminal is formed on the wiring board, the wafer and the wiring board joined together with the probe terminal, which are added to the probe terminal and the joint portion of the probe terminal, This is preferable because the thermal stress due to the difference in thermal expansion is relatively small. Further, when used as a probe card, it is possible to effectively prevent thermal deformation with respect to a thermal load during measurement of the electrical characteristics of the semiconductor element, and furthermore, heat is not retained inside due to high heat transfer properties.

セラミック配線基板1の内部配線5および外部配線7・7aは、セラミック絶縁層8と同時焼成により形成される、タングステン(W),モリブデン(Mo),モリブデン−マンガン(Mo−Mn)合金,銀(Ag),銅(Cu),金(Au),銀−パラジウム(Pd)合金等の金属を主成分とするメタライズからなるものである。   The internal wiring 5 and the external wirings 7 and 7a of the ceramic wiring substrate 1 are formed by simultaneous firing with the ceramic insulating layer 8, and tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn) alloy, silver ( Ag), copper (Cu), gold (Au), silver-palladium (Pd) alloy and the like, which is made of metallization mainly composed of metal.

このようなセラミック配線基板1は、以下の方法により製作される。例えば、セラミック絶縁層8が酸化アルミニウム質焼結体で形成される場合には、まず、酸化アルミニウム,酸化珪素,酸化マグネシウムおよび酸化カルシウムの原材料粉末に適当な有機バインダおよび溶媒を添加混合して泥漿状となすとともに、これをドクターブレード法等によってシート状に成形し、セラミック絶縁層8となる複数のセラミックグリーンシートを作製する。   Such a ceramic wiring substrate 1 is manufactured by the following method. For example, when the ceramic insulating layer 8 is formed of an aluminum oxide sintered body, first, an appropriate organic binder and solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, magnesium oxide and calcium oxide, and the slurry is mixed. This is formed into a sheet shape by a doctor blade method or the like to produce a plurality of ceramic green sheets to be the ceramic insulating layer 8.

次に、セラミックグリーンシートの内部貫通導体が形成される所定位置に適当な打ち抜き加工により貫通孔を形成するとともに、貫通孔に導体ペーストを充填する。また、スクリーン印刷法等によってセラミックグリーンシートの所定位置に内部配線層となる導体ペースト層を10〜20μmの厚みに形成する。導体ペーストは、タングステン(W),モリブデン(Mo),モリブデン−マンガン(Mo−Mn)合金等の融点の高い金属粉末と適当な樹脂バインダおよび溶剤とを混練することにより作製される。   Next, a through hole is formed by a suitable punching process at a predetermined position where the internal through conductor of the ceramic green sheet is formed, and the through hole is filled with a conductive paste. Further, a conductor paste layer serving as an internal wiring layer is formed to a thickness of 10 to 20 μm at a predetermined position of the ceramic green sheet by screen printing or the like. The conductive paste is produced by kneading a metal powder having a high melting point such as tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn) alloy, an appropriate resin binder, and a solvent.

最後に、これらセラミックグリーンシートを重ね合わせて圧着して積層体を作製し、この積層体を1500℃〜1600℃程度の高温で焼成することによりセラミック配線基板1が作製される。セラミック配線基板1の外部配線7・7aの表面には、腐食防止や外部回路との接続性のために、厚さ1〜10μm程度のニッケルめっき層および厚さ0.1〜3μm程度の金めっき層を順次形成するとよい。内部配線5(内部貫通導体)のセラミック配線基板1の表面に露出する部分にも同様のめっき層を形成してもよい。   Finally, these ceramic green sheets are superposed and pressure-bonded to produce a laminate, and the laminate is fired at a high temperature of about 1500 ° C. to 1600 ° C., thereby producing the ceramic wiring substrate 1. On the surface of the external wiring 7 and 7a of the ceramic wiring board 1, a nickel plating layer with a thickness of about 1 to 10 μm and a gold plating layer with a thickness of about 0.1 to 3 μm are provided to prevent corrosion and connect with external circuits. It may be formed sequentially. A similar plating layer may be formed on a portion of the internal wiring 5 (internal through conductor) exposed on the surface of the ceramic wiring substrate 1.

セラミック配線基板1の上面の外部配線7aは、外部配線7aを有さないセラミック配線基板1を作製して、その上面を研磨するなどして平坦にした後に、モリマン法等のメタライズ法や蒸着法,スパッタリング法,イオンプレーティング法等の薄膜形成法により形成してもよい。メタライズ法の場合は、例えば、スクリーン印刷法等によってセラミック配線基板1の所定位置にタングステン(W),モリブデン(Mo),マンガン(Mn)等の金属粉末と適当な樹脂バインダおよび溶剤を含む金属ペーストを塗布し、1400℃以上の高温で熱処理することにより作製される。薄膜形成法の場合は、セラミック配線基板1の上面の全面に、0.1μm〜3μm程度の厚みの、例えばクロム(Cr)−Cu合金層やチタン(Ti)−Cu合金層から成る下地導体層を形成し、その上に外部配線7aのパターン形状の開口を有するレジスト膜を形成して、このレジスト膜をマスクとしてめっき等で銅や金等の金属から成る、2μm〜10μm程度の厚みの主導体層を形成する。そして、レジスト膜を剥離除去し、下地導体層の露出した部分をエッチングにより除去することで外部配線7aが形成される。その表面には、さらに、めっき法によりニッケルや金のめっき層を形成するとよい。   The external wiring 7a on the upper surface of the ceramic wiring substrate 1 is made by flattening the upper surface of the ceramic wiring substrate 1 having no external wiring 7a by polishing the upper surface, and then metallizing or vapor deposition such as the Moriman method. Alternatively, a thin film forming method such as a sputtering method or an ion plating method may be used. In the case of the metallization method, for example, a metal paste containing a metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn), an appropriate resin binder and solvent at a predetermined position of the ceramic wiring substrate 1 by a screen printing method or the like. And is heat-treated at a high temperature of 1400 ° C. or higher. In the case of the thin film forming method, a base conductor layer made of, for example, a chromium (Cr) -Cu alloy layer or a titanium (Ti) -Cu alloy layer having a thickness of about 0.1 μm to 3 μm is formed on the entire upper surface of the ceramic wiring substrate 1. A resist film having a pattern-shaped opening of the external wiring 7a is formed thereon, and a main conductor having a thickness of about 2 μm to 10 μm made of a metal such as copper or gold by plating or the like using the resist film as a mask. Form a layer. Then, the resist film is peeled and removed, and the exposed portion of the underlying conductor layer is removed by etching, whereby the external wiring 7a is formed. A nickel or gold plating layer may be further formed on the surface by plating.

絶縁樹脂層2は、ポリイミド樹脂,ポリフェニレンサルファイド樹脂,全芳香族ポリエステル樹脂,BCB(ベンゾシクロブテン)樹脂,エポキシ樹脂,ビスマレイミドトリアジン樹脂,ポリフェニレンエーテル樹脂,ポリキノリン樹脂,フッ素樹脂等の絶縁性の樹脂から成るものである。   The insulating resin layer 2 is made of an insulating resin such as polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, BCB (benzocyclobutene) resin, epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, polyquinoline resin, or fluororesin. It consists of

セラミック配線基板1の上に絶縁樹脂層2を形成するには、例えば、ポリイミド樹脂からなる場合には、ワニス状のポリイミド前駆体を基板1の上面にスピンコート法・ダイコート法・カーテンコート法・印刷法等の塗布法により塗布し、しかる後、400℃程度の熱で硬化させてポリイミド化させることによって10μm〜50μm程度の厚みに形成する。あるいは、上記樹脂から成る10μm〜50μm程度のシートの下面に、シロキサン変性ポリアミドイミド樹脂,シロキサン変性ポリイミド樹脂,ポリイミド樹脂,ビスマレイミドトリアジン樹脂,エポキシ樹脂等の樹脂接着剤を乾燥厚みで5μm〜20μm程度にドクターブレード法等の塗布法にて塗布して乾燥させることで接着剤層を形成し、これをセラミック配線基板1の上に重ねて加熱プレスすることで形成する。いずれの方法においても、絶縁樹脂層2にビア導体4および配線層3を形成して上記工程を必要な絶縁樹脂層2の数だけ繰り返すことで複数の絶縁樹脂層2が形成される。フィルムの樹脂を用いる方法は、複数のフィルムを一括してプレスすることが可能であり、1層毎に塗布および硬化を行なう必要がないので、製造工程を短くすることができる。   In order to form the insulating resin layer 2 on the ceramic wiring substrate 1, for example, when it is made of polyimide resin, a varnish-like polyimide precursor is applied to the upper surface of the substrate 1 by spin coating, die coating, curtain coating, The film is applied by a coating method such as a printing method, and then cured by heat at about 400 ° C. to form a polyimide, thereby forming a thickness of about 10 μm to 50 μm. Alternatively, a resin adhesive such as a siloxane-modified polyamideimide resin, a siloxane-modified polyimide resin, a polyimide resin, a bismaleimide triazine resin, or an epoxy resin is dried on the lower surface of a sheet of about 10 μm to 50 μm made of the above resin with a dry thickness of about 5 to 20 μm An adhesive layer is formed by applying and drying by a coating method such as a doctor blade method, and the adhesive layer is formed on the ceramic wiring substrate 1 by heating and pressing. In any method, the plurality of insulating resin layers 2 are formed by forming the via conductors 4 and the wiring layers 3 in the insulating resin layer 2 and repeating the above steps as many times as the number of necessary insulating resin layers 2. In the method using a resin for a film, a plurality of films can be pressed at once, and it is not necessary to apply and cure for each layer, so that the manufacturing process can be shortened.

絶縁樹脂層2にはビア導体4が形成されるので、この部分には例えば、直径20μm〜100μmの貫通孔が形成される。この貫通孔の形成方法は、まず絶縁樹脂層2に開口を有するレジスト膜を形成するとともにこのレジスト膜の開口に位置する絶縁樹脂層2をエッチングすることによって、あるいはレーザを使い直接絶縁樹脂層2の一部を除去することによって形成される。このときのレーザはエキシマレーザ,COレーザ等を用いることができるが、貫通孔の内壁の形状を垂直に近く調整でき、さらに貫通孔の内壁面を滑らかに加工できる紫外線レーザで形成しておくのが望ましい。あるいは、ワニス状の樹脂を塗布する方法の場合であれば、感光性の樹脂を用いて、例えば露光により貫通孔が形成される部分以外を硬化させて、貫通孔が形成される部分の樹脂をエッチングにより除去することにより貫通孔を形成してもよい。 Since the via conductor 4 is formed in the insulating resin layer 2, for example, a through hole having a diameter of 20 μm to 100 μm is formed in this portion. This through hole is formed by first forming a resist film having an opening in the insulating resin layer 2 and etching the insulating resin layer 2 located in the opening of the resist film, or directly using a laser. It is formed by removing a part of. As the laser at this time, an excimer laser, a CO 2 laser, or the like can be used. However, the shape of the inner wall of the through hole can be adjusted almost vertically, and the inner wall surface of the through hole can be formed with an ultraviolet laser that can be processed smoothly. Is desirable. Alternatively, in the case of a method of applying a varnish-like resin, a photosensitive resin is used, for example, a portion other than a portion where a through-hole is formed by exposure is cured, and a resin in a portion where the through-hole is formed is obtained. The through hole may be formed by removing by etching.

配線層3の形成は、まず、蒸着法やスパッタリング法、イオンプレーティング法等の薄膜形成法により、絶縁樹脂層2の主面の全面に、0.1μm〜3μm程度の厚みの、例えばクロム(Cr)−Cu合金層やチタン(Ti)−Cu合金層から成る下地導体層を形成する。次に、下地導体層の上に配線層3のパターン形状の開口を有するレジスト膜を形成して、このレジスト膜をマスクとしてめっき等で銅や金等の電気抵抗の小さい金属から成る、2μm〜10μm程度の厚みの主導体層を形成する。そして、レジスト膜を剥離除去し、下地導体層の露出した部分をエッチングにより除去することで配線層3が形成される。最上層の配線層3の表面には、外部配線7と同様に、めっき法によりニッケルや金のめっき層を形成するとよい。   First, the wiring layer 3 is formed by, for example, chromium (Cr) having a thickness of about 0.1 μm to 3 μm on the entire main surface of the insulating resin layer 2 by a thin film forming method such as vapor deposition, sputtering, or ion plating. ) A base conductor layer made of a -Cu alloy layer or a titanium (Ti) -Cu alloy layer is formed. Next, a resist film having a pattern-shaped opening of the wiring layer 3 is formed on the underlying conductor layer, and the resist film is used as a mask to form a metal having a low electrical resistance such as copper or gold by plating or the like. A main conductor layer having a thickness of about 10 μm is formed. Then, the wiring layer 3 is formed by removing the resist film and removing the exposed portion of the underlying conductor layer by etching. Similar to the external wiring 7, a nickel or gold plating layer may be formed on the surface of the uppermost wiring layer 3 by plating.

配線層3は、図4に示す例のように、絶縁樹脂層2に配線層3と同形状の凹部を形成しておき、その凹部内に配線層3を形成すると、絶縁樹脂層2の上面と配線層3の上面との間に段差がなく平坦になるので、複数の絶縁樹脂層2を積層しても配線基板の上面は平坦となり、最上層の絶縁樹脂層2の上面の配線層3に電子部品やプローブピンをより良好に接続することが可能となるので好ましい。絶縁樹脂層2に凹部を形成するには、絶縁樹脂層2の表面に配線層3のパターン形状の開口を有するレジスト膜を形成して、RIE(Reactive Ion Etching)等のエッチング法により絶縁樹脂層2の露出した部分の表面を除去して形成すればよい。   As shown in the example shown in FIG. 4, when the wiring layer 3 is formed with a recess having the same shape as the wiring layer 3 in the insulating resin layer 2 and the wiring layer 3 is formed in the recess, the upper surface of the insulating resin layer 2 is formed. Since there is no step between the wiring layer 3 and the upper surface of the wiring layer 3, the upper surface of the wiring substrate is flat even if a plurality of insulating resin layers 2 are stacked, and the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2. It is preferable because an electronic component and a probe pin can be connected better. In order to form a recess in the insulating resin layer 2, a resist film having a pattern-shaped opening of the wiring layer 3 is formed on the surface of the insulating resin layer 2, and the insulating resin layer is etched by an etching method such as RIE (Reactive Ion Etching). The surface of the exposed portion of 2 may be removed.

貫通導体6が最下層の絶縁樹脂層2の上面から最下層の絶縁樹脂層2の上面の配線層3内に突出している場合は、最下層の絶縁樹脂層2の上面から突出する貫通導体6を形成しておき、それに重なるように上記の方法で配線層3を形成すればよい。図3に示す例では貫通導体6の上面にも配線層3が形成されて接続されているが、配線層3を貫通導体6が貫通して貫通導体6の側面と配線層3とが接続されていてもよい。   When the through conductor 6 protrudes from the upper surface of the lowermost insulating resin layer 2 into the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2, the through conductor 6 protrudes from the upper surface of the lowermost insulating resin layer 2. And the wiring layer 3 may be formed by the above-described method so as to overlap therewith. In the example shown in FIG. 3, the wiring layer 3 is also formed and connected to the upper surface of the through conductor 6, but the side surface of the through conductor 6 and the wiring layer 3 are connected through the wiring layer 3. It may be.

ビア導体4は、配線層3を形成する前に、例えば、銅等の金属粉末と樹脂を主成分とする導体ペーストを絶縁樹脂層2の貫通孔に充填しておくことにより、図1〜図5に示す例のような、貫通孔が導体により充填されたものが形成される。導体ペーストは、銅等の金属粉末と樹脂と溶媒から成り、貫通孔に充填した後に乾燥させることにより固化するものである。あるいは、配線層3を形成する際に、貫通孔の内面にも下地導体層および主導体層を形成することにより、配線層3と同時に形成してもよい。この場合のビア導体4は、絶縁樹脂層2の貫通孔の内面に被着して形成され、貫通孔は導体により充填されたものとはならない。主導体層を形成する際のめっき厚みを厚くすると、図1〜図5に示す例のような、貫通孔が導体により充填されたものとすることができる。ビア導体4を配線層3と同時に形成する場合は、貫通孔の内面に薄膜により下地導体層を良好に形成することができるように、図1〜図5に示す例のように、貫通孔は絶縁樹脂層2の上面側のほうが大きくなるような形状にするのが好ましい。このような形状の貫通孔は、エッチングにより貫通孔を形成する場合はエッチング条件により、レーザにより貫通孔を形成する場合はレーザの出力等の調節により、感光性樹脂を用いる場合は露光条件やエッチング条件により形成することができる。   Before forming the wiring layer 3, the via conductor 4 is formed by filling a through hole of the insulating resin layer 2 with a conductive paste mainly composed of metal powder such as copper and resin, as shown in FIGS. As shown in the example shown in FIG. 5, a through hole filled with a conductor is formed. The conductor paste is made of a metal powder such as copper, a resin, and a solvent, and is solidified by filling the through holes and then drying. Alternatively, when the wiring layer 3 is formed, it may be formed simultaneously with the wiring layer 3 by forming the base conductor layer and the main conductor layer on the inner surface of the through hole. In this case, the via conductor 4 is formed by being attached to the inner surface of the through hole of the insulating resin layer 2, and the through hole is not filled with the conductor. When the plating thickness at the time of forming the main conductor layer is increased, the through-holes can be filled with the conductor as in the examples shown in FIGS. When the via conductor 4 is formed at the same time as the wiring layer 3, the through hole is formed as shown in the example shown in FIGS. 1 to 5 so that the base conductor layer can be satisfactorily formed by a thin film on the inner surface of the through hole. It is preferable to make the shape so that the upper surface side of the insulating resin layer 2 becomes larger. The through hole having such a shape is controlled by etching conditions when the through hole is formed by etching, by adjusting the output of the laser when the through hole is formed by a laser, or by exposure condition or etching when using a photosensitive resin. It can be formed depending on conditions.

貫通導体6は、最下層の絶縁樹脂層2の上面からセラミック配線基板1内に至るもの、あるいは、さらに最下層の絶縁樹脂層2の上面から最下層の絶縁樹脂層2の上面の配線層3内に突出しているものであるが、最下層の絶縁樹脂層2のビア導体4がセラミック配線基板1内まで延びているものであってもよく、セラミック配線基板1と同時焼成で形成され、セラミック配線基板1の最上層のセラミック絶縁層8から突出しているものであってもよい。   The through conductor 6 extends from the upper surface of the lowermost insulating resin layer 2 into the ceramic wiring substrate 1, or further from the upper surface of the lowermost insulating resin layer 2 to the upper wiring layer 3 of the lowermost insulating resin layer 2. The via conductor 4 of the lowermost insulating resin layer 2 may extend into the ceramic wiring substrate 1 and is formed by simultaneous firing with the ceramic wiring substrate 1 and is ceramic. It may protrude from the uppermost ceramic insulating layer 8 of the wiring board 1.

貫通導体6が、最下層の絶縁樹脂層2のビア導体4がセラミック配線基板1内まで延びたものである場合は、以下のようにして形成することができる。まず、上面に貫通導体6の下部が入る穴を有するセラミック配線基板1を作製する。上記のようにしてセラミック配線基板1を作製した後にレーザ加工やマスクを用いたブラスト加工により穴を形成してもよいし、焼成前の積層体あるいは最上層のセラミック絶縁層8となるセラミックグリーンシートにレーザ加工等により穴を形成してもよい。このようにして作製したセラミック配線基板1は、例えば、図1〜図4に示す例のようなものとなる。あるいは、最上層のセラミック絶縁層8となるセラミックグリーンシートに、穴となる貫通孔を形成しておいてセラミック配線基板1を作製してもよい。このようにして作製したセラミック配線基板1は図5に示す例のようなものとなる。次に、この穴を有するセラミック配線基板1の上に絶縁樹脂層2を形成して貫通孔を形成する。そして、上記したビア導体4の形成方法により貫通導体6が形成される。貫通導体6を最下層の絶縁樹脂層2の上面から最下層の絶縁樹脂層2の上面の配線層3内に突出させる場合は、必要に応じて最下層の絶縁樹脂層2の貫通孔の周囲に予めレジストを形成しておき、貫通導体6となるめっき皮膜の厚みを厚くすればよい。このときに、めっきは電解めっきとし、内部配線5を電極として内部配線5上に銅等のめっき皮膜が析出するようにすると、アスペクト比が高い場合であってもボイドが含まれない貫通導体6を形成できるので、高強度で高接合信頼性、低電気抵抗な貫通導体6となるので好ましい。   When the through conductor 6 is one in which the via conductor 4 of the lowermost insulating resin layer 2 extends into the ceramic wiring substrate 1, it can be formed as follows. First, the ceramic wiring board 1 having a hole into which the lower portion of the through conductor 6 enters is prepared on the upper surface. After the ceramic wiring substrate 1 is manufactured as described above, holes may be formed by laser processing or blast processing using a mask, or a ceramic green sheet that becomes the laminated body before firing or the uppermost ceramic insulating layer 8 A hole may be formed by laser processing or the like. The ceramic wiring board 1 manufactured as described above is, for example, as shown in FIGS. Alternatively, the ceramic wiring substrate 1 may be manufactured by forming a through hole to be a hole in a ceramic green sheet to be the uppermost ceramic insulating layer 8. The ceramic wiring board 1 produced in this way is as shown in the example shown in FIG. Next, the insulating resin layer 2 is formed on the ceramic wiring substrate 1 having the holes to form through holes. Then, the through conductor 6 is formed by the method of forming the via conductor 4 described above. When the through conductor 6 is projected from the upper surface of the lowermost insulating resin layer 2 into the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2, if necessary, the periphery of the through hole of the lowermost insulating resin layer 2 A resist is formed in advance, and the thickness of the plating film to be the through conductor 6 may be increased. At this time, if the plating is electrolytic plating and a plating film such as copper is deposited on the internal wiring 5 using the internal wiring 5 as an electrode, the through conductor 6 that does not contain voids even when the aspect ratio is high. Therefore, it is preferable because the through conductor 6 has high strength, high bonding reliability, and low electrical resistance.

あるいは、上記ビア導体4と同様に、例えば、銅等の金属粉末と樹脂を主成分とする導体ペーストを絶縁樹脂層2の貫通孔に充填することでも、図1〜図5に示す例のような、貫通孔が導体により充填された貫通導体6を形成することができる。   Alternatively, as in the case of the via conductor 4, for example, a conductive paste mainly composed of a metal powder such as copper and a resin is filled in the through holes of the insulating resin layer 2 as in the examples shown in FIGS. 1 to 5. In addition, the through conductor 6 in which the through hole is filled with the conductor can be formed.

このような、貫通導体6が最下層の絶縁樹脂層2のビア導体4がセラミック配線基板1内まで延びたものである場合で、ワニス状の樹脂を塗布して絶縁樹脂層2を形成するときは、セラミック配線基板1の上面の穴にワニス状の樹脂が入らないように、孔の上部の絶縁樹脂層2に開口する貫通孔が形成されるように、孔の周囲に塗布するとよい。孔へのワニス状の樹脂の流入を防止するためには、図5に示す例のように、絶縁樹脂層2の貫通孔の径をセラミック配線基板1の上面の穴の径より大きくなるように塗布するのが好ましい。ただし、ワニスが穴に入った場合であってもレーザやRIE等のエッチングにより除去することは可能である。樹脂シートを加熱プレスにより接着する方法の場合は、セラミック配線基板1の上面の穴に樹脂が流入することがないので好ましい。   When the through conductor 6 is a via conductor 4 of the lowermost insulating resin layer 2 extending into the ceramic wiring substrate 1 and the insulating resin layer 2 is formed by applying a varnish-like resin. Is preferably applied to the periphery of the hole so that a through hole opening in the insulating resin layer 2 above the hole is formed so that the varnish-like resin does not enter the hole on the upper surface of the ceramic wiring substrate 1. In order to prevent the varnish-like resin from flowing into the hole, the diameter of the through hole of the insulating resin layer 2 is made larger than the diameter of the hole on the upper surface of the ceramic wiring board 1 as in the example shown in FIG. It is preferable to apply. However, even if the varnish enters the hole, it can be removed by etching such as laser or RIE. The method of bonding the resin sheet by a hot press is preferable because the resin does not flow into the hole on the upper surface of the ceramic wiring substrate 1.

貫通導体6が、セラミック配線基板1と同時焼成で形成され、セラミック配線基板1の最上層のセラミック絶縁層8から突出したものである場合は、以下のようにして形成することができる。まず、貫通導体6が上から2番目のセラミック絶縁層8から最上層のセラミック絶縁層8にかけて形成され、最上層のセラミック絶縁層8には内部配線5が形成されていないセラミック配線基板1を作製する。この配線セラミック配線基板1の上面を平坦に研磨し、貫通導体6が上面に露出した部分にレジスト膜を形成する。次にセラミック配線基板1の上面をサンドブラストで研削することにより最上層のセラミック絶縁層8だけを研削した後、レジストを剥離することによって、貫通導体6の一部が上面から突出するとともに内部配線5が表面に露出したセラミック配線基板1が製作される。   When the through conductor 6 is formed by simultaneous firing with the ceramic wiring substrate 1 and protrudes from the uppermost ceramic insulating layer 8 of the ceramic wiring substrate 1, it can be formed as follows. First, the through wiring conductor 6 is formed from the second ceramic insulating layer 8 from the top to the uppermost ceramic insulating layer 8, and the ceramic wiring substrate 1 in which the inner wiring 5 is not formed in the uppermost ceramic insulating layer 8 is manufactured. To do. The upper surface of the wiring ceramic wiring substrate 1 is polished flat, and a resist film is formed on the portion where the through conductor 6 is exposed on the upper surface. Next, the upper surface of the ceramic wiring substrate 1 is ground by sandblasting to grind only the uppermost ceramic insulating layer 8 and then the resist is peeled off so that a part of the through conductor 6 protrudes from the upper surface and the internal wiring 5 The ceramic wiring board 1 with the surface exposed is manufactured.

または、貫通導体6よりセラミック絶縁層8の方がエッチングレートが大きいエッチング方法を用いてもよい。例えば、セラミック絶縁層8がガラスセラミックスであり、貫通導体6が銅を主成分とする場合であれば、貫通導体6の銅よりもセラミック絶縁層8のガラスセラミックスの方がRIEエッチングの加工レートが速いので、銅を主成分とする貫通導体6の上部を柱状に残したままセラミック絶縁層8の表面の除去が可能である。フッ化アンモニウム等のガラスが溶解しやすく、金属は溶解しにくいものをエッチング液として用いても同様にできる。   Alternatively, an etching method in which the ceramic insulating layer 8 has a higher etching rate than the through conductor 6 may be used. For example, when the ceramic insulating layer 8 is made of glass ceramics and the through conductor 6 is mainly composed of copper, the glass ceramic of the ceramic insulating layer 8 has a processing rate of RIE etching rather than the copper of the through conductor 6. Since it is fast, it is possible to remove the surface of the ceramic insulating layer 8 while leaving the upper part of the through conductor 6 mainly composed of copper in a columnar shape. Even when glass such as ammonium fluoride is easy to dissolve and the metal is difficult to dissolve, the same can be applied.

あるいは、セラミック配線基板1を作製する際に、貫通導体6用の導体ペーストをセラミックグリーンシートより焼結収縮が小さい組成、あるいはセラミックグリーンシートより低い温度で焼結収縮してセラミックグリーンシートが焼結収縮するときには収縮しないような組成の導体ペーストを用いて焼成することにより、貫通導体6が突出したセラミック配線基板1を作製することができる。さらに、セラミック絶縁層8がガラスセラミックスから成る場合であれば、セラミックグリーンシートが焼結する温度では焼結収縮しない、アルミナ等を主成分とする拘束グリーンシートを積層体の両面に積層して焼成すると、拘束グリーンシートによりセラミックグリーンシートは積層面方向の焼結収縮が抑えられ、厚み方向により収縮しやすくなるので、貫通導体6を突出させるのがより容易になるとともに、平面方向の収縮が小さく収縮ばらつきや寸法精度が良好なセラミック配線基板1が得られるので好ましい。   Alternatively, when the ceramic wiring board 1 is manufactured, the ceramic paste is sintered by shrinking the conductive paste for the through conductor 6 with a composition having a smaller sintering shrinkage than the ceramic green sheet or at a lower temperature than the ceramic green sheet. By firing using a conductor paste having a composition that does not shrink when shrinking, the ceramic wiring board 1 with the through conductors 6 protruding can be produced. Further, if the ceramic insulating layer 8 is made of glass ceramics, firing is performed by laminating a constrained green sheet mainly composed of alumina or the like on both sides of the laminate, which does not sinter and shrink at the temperature at which the ceramic green sheet is sintered. Then, the ceramic green sheet is restrained from sintering shrinkage in the direction of the laminated surface by the constraining green sheet, and is more likely to shrink in the thickness direction, so that it is easier to project the through conductor 6 and the shrinkage in the planar direction is small. This is preferable because a ceramic wiring board 1 with good shrinkage variation and dimensional accuracy can be obtained.

このような、貫通導体6の一部が最上層のセラミック絶縁層8から突出したセラミック配線基板1の上面に最下層の絶縁樹脂層2を形成するには、例えば、以下のようにすればよい。まず、予めワニス状のポリイミド樹脂を半硬化状態のフィルム状に成形し、それをセラミック配線基板1の上に載せて加熱プレスすることでポリイミド樹脂を硬化し、貫通導体6の上面まで絶縁樹脂層2に覆われた状態にする。そして、貫通導体6が露出するまで絶縁樹脂層2を研磨するとセラミック配線基板1内から最下層の絶縁樹脂層2の上面に至る貫通導体6となる。このときの研磨を機械研磨だけで行うと貫通導体6が機械研磨時の力で曲がり易いので、貫通導体6の上のポリイミド樹脂等の樹脂層の厚みが50μm程度になるまでの粗研磨は機械研磨で行い、その後はRIEを用いて絶縁樹脂層2表面全面をエッチングして平坦にすることが好ましい。特に、最下層の絶縁樹脂層2の上面から最下層の絶縁樹脂層2の上面の配線層3内に突出させる場合は、機械研磨により貫通導体6が露出するまで絶縁樹脂層2を研磨した場合であっても、その後はRIEを用いて絶縁樹脂層2の表面全面をエッチングすることで貫通導体6の変形や径の減少を防ぎつつ貫通導体6を最下層の絶縁樹脂層2の上面から突出させることができるので好ましい。   In order to form the lowermost insulating resin layer 2 on the upper surface of the ceramic wiring substrate 1 in which a part of the through conductor 6 protrudes from the uppermost ceramic insulating layer 8, for example, the following may be performed. . First, a varnish-like polyimide resin is formed into a semi-cured film in advance, and the polyimide resin is cured by placing it on the ceramic wiring substrate 1 and then heat-pressing. 2 covered. When the insulating resin layer 2 is polished until the through conductor 6 is exposed, the through conductor 6 extends from the ceramic wiring substrate 1 to the upper surface of the lowermost insulating resin layer 2. If the polishing at this time is performed only by mechanical polishing, the through conductor 6 is easily bent by the force during mechanical polishing. Therefore, rough polishing until the thickness of the resin layer such as polyimide resin on the through conductor 6 reaches about 50 μm is performed by mechanical polishing. It is preferable that the polishing is performed, and thereafter, the entire surface of the insulating resin layer 2 is etched and flattened using RIE. In particular, when the insulating resin layer 2 is polished from the upper surface of the lowermost insulating resin layer 2 into the wiring layer 3 on the upper surface of the lowermost insulating resin layer 2, the insulating resin layer 2 is polished until the through conductor 6 is exposed by mechanical polishing. Even then, the entire surface of the insulating resin layer 2 is etched using RIE, thereby preventing the through conductor 6 from being deformed or reducing its diameter, while protruding the through conductor 6 from the upper surface of the lowermost insulating resin layer 2. This is preferable.

貫通導体6は、上記のような製造方法および材質の場合には、その径が75μm〜200μm程度であれば、絶縁樹脂層2の熱膨張係数とセラミック配線基板1の熱膨張係数の差による熱応力により破断してしまう可能性が小さい。また、このとき、貫通導体6の最下層の絶縁樹脂層2とセラミック配線基板1との界面から最下層の絶縁樹脂層2の上面の配線層3までの長さ(=最下層の絶縁樹脂層2の厚み)が20μm〜50μm程度であり、貫通導体6の最下層の絶縁樹脂層2とセラミック配線基板1との界面からセラミック配線基板1内に位置する下端までの長さ(=図5に示す例では、セラミック配線基板1の最上層のセラミック絶縁層8の厚み)が100μm〜500μm程度であれば、熱応力により貫通導体6と配線層3との接続部や貫通導体6と内部配線5との接続部で破断してしまう可能性が小さい。   In the case of the manufacturing method and material as described above, if the diameter of the through conductor 6 is about 75 μm to 200 μm, the heat due to the difference between the thermal expansion coefficient of the insulating resin layer 2 and the thermal expansion coefficient of the ceramic wiring board 1 is obtained. The possibility of breakage due to stress is small. At this time, the length from the interface between the lowermost insulating resin layer 2 of the through conductor 6 and the ceramic wiring board 1 to the upper wiring layer 3 of the lowermost insulating resin layer 2 (= the lowermost insulating resin layer) 2) is about 20 μm to 50 μm, and the length from the interface between the insulating resin layer 2 as the lowermost layer of the through conductor 6 and the ceramic wiring board 1 to the lower end located in the ceramic wiring board 1 (= in FIG. 5) In the example shown, if the thickness of the uppermost ceramic insulating layer 8 of the ceramic wiring substrate 1 is about 100 μm to 500 μm, the connecting portion between the through conductor 6 and the wiring layer 3 and the through conductor 6 and the internal wiring 5 are caused by thermal stress. The possibility of breaking at the connecting portion is small.

本発明のプローブカードは、上記のような本発明の配線基板と、最上層の絶縁樹脂層2の上面の配線層3に接続されたプローブピンとを具備するものである。プローブピンは、例えば、以下のようにして作製され、本発明の配線基板に取り付けられる。まず、シリコンウエハの1面にエッチングにより複数のプローブピンの雌型を形成し、雌型を形成した面にめっき法によりニッケルから成る金属を被着させるとともに雌型をニッケルで埋め込み、埋め込まれたニッケル以外のウエハ上のニッケルをエッチング等の加工を施すことにより除去して、ニッケル製プローブピンが埋設されたシリコンウエハを作製する。このシリコンウエハに埋設されたニッケル製プローブピンを配線基板の最上層の絶縁樹脂層2の上面の配線層3にはんだ等の接合材で接合する。そして、シリコンウエハを水酸化カリウム水溶液で除去することによって、プローブカードが得られる。   The probe card of the present invention comprises the above-described wiring board of the present invention and probe pins connected to the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2. The probe pin is produced, for example, as follows and attached to the wiring board of the present invention. First, a female die of a plurality of probe pins is formed on one surface of a silicon wafer by etching, a metal made of nickel is deposited on the surface on which the female die is formed by plating, and the female die is embedded and embedded with nickel. Nickel on the wafer other than nickel is removed by performing a process such as etching to produce a silicon wafer in which nickel probe pins are embedded. Nickel probe pins embedded in the silicon wafer are bonded to the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2 of the wiring substrate by a bonding material such as solder. Then, the probe card is obtained by removing the silicon wafer with an aqueous potassium hydroxide solution.

本発明の電子装置は、上記のような本発明の配線基板と、最上層の絶縁樹脂層2の上面の配線層3に接続された電子部品とを具備するものである。電子部品は、例えばICチップ等の半導体素子や水晶振動子等の圧電振動子であり、チップコンデンサ等の受動素子も必要に応じて搭載される。このような電子部品の配線層3への接続は、はんだ付けや導電性接着剤による接着、およびワイヤボンディングにより行なわれる。   The electronic device of the present invention includes the above-described wiring board of the present invention and an electronic component connected to the wiring layer 3 on the upper surface of the uppermost insulating resin layer 2. The electronic component is, for example, a semiconductor element such as an IC chip or a piezoelectric vibrator such as a crystal vibrator, and a passive element such as a chip capacitor is also mounted as necessary. Such connection of the electronic component to the wiring layer 3 is performed by soldering, bonding with a conductive adhesive, and wire bonding.

1:セラミック配線基板
2:絶縁樹脂層
3:配線層
4:ビア導体
5:内部配線
6:貫通導体
7:外部配線
7a:セラミック配線基板の上面の外部配線
8:セラミック絶縁層
1: Ceramic wiring board 2: Insulating resin layer 3: Wiring layer 4: Via conductor 5: Internal wiring 6: Through conductor 7: External wiring 7a: External wiring on the upper surface of the ceramic wiring board 8: Ceramic insulating layer

Claims (4)

セラミック配線基板と、該セラミック配線基板の上面に積層された複数の絶縁樹脂層と、複数の該絶縁樹脂層それぞれの上面の配線層と、前記絶縁樹脂層の上下に位置する前記配線層間を接続するビア導体と、最下層の前記絶縁樹脂層の上面からセラミック配線基板内に至り、最下層の前記絶縁樹脂層の上面の前記配線層と前記セラミック配線基板の上面の外部配線とを接続する貫通導体とを具備することを特徴とする配線基板。 Connecting a ceramic wiring substrate, a plurality of insulating resin layers laminated on the upper surface of the ceramic wiring substrate, a wiring layer on each of the plurality of insulating resin layers, and the wiring layers positioned above and below the insulating resin layer A via conductor extending from the upper surface of the lowermost insulating resin layer into the ceramic wiring substrate and connecting the wiring layer on the upper surface of the lowermost insulating resin layer and the external wiring on the upper surface of the ceramic wiring substrate A wiring board comprising a conductor. 前記貫通導体は最下層の前記絶縁樹脂層の上面から最下層の前記絶縁樹脂層の上面の配線層内に突出していることを特徴とする請求項1記載の配線基板。 2. The wiring board according to claim 1, wherein the through conductor protrudes from the upper surface of the lowermost insulating resin layer into the wiring layer on the upper surface of the lowermost insulating resin layer. 請求項1または請求項2に記載の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続されたプローブピンとを具備することを特徴とするプローブカード。 A probe card comprising: the wiring board according to claim 1; and a probe pin connected to a wiring layer on an upper surface of the uppermost insulating resin layer. 請求項1または請求項2に記載の配線基板と、最上層の前記絶縁樹脂層の上面の配線層に接続された電子部品とを具備することを特徴とする電子装置。 An electronic device comprising: the wiring board according to claim 1; and an electronic component connected to a wiring layer on an upper surface of the uppermost insulating resin layer.
JP2009037344A 2009-02-20 2009-02-20 Wiring substrate, probe card, and electronic device Pending JP2010192784A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107390A (en) * 2012-11-27 2014-06-09 Kyocera Corp Wiring board and multilayer wiring board using the same
JP2015002227A (en) * 2013-06-14 2015-01-05 日本特殊陶業株式会社 Multilayer wiring board and method for manufacturing the same
JP2015185773A (en) * 2014-03-25 2015-10-22 新光電気工業株式会社 Wiring board and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107390A (en) * 2012-11-27 2014-06-09 Kyocera Corp Wiring board and multilayer wiring board using the same
JP2015002227A (en) * 2013-06-14 2015-01-05 日本特殊陶業株式会社 Multilayer wiring board and method for manufacturing the same
JP2015185773A (en) * 2014-03-25 2015-10-22 新光電気工業株式会社 Wiring board and manufacturing method of the same

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