JP2010087260A - Multilayer capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer capacitor which can inhibit the impedance from decreasing near a resonance frequency. <P>SOLUTION: The multilayer capacitor 1 comprises a dielectric matrix 10, a plurality of inner electrodes 12A, 12B, 14A, 14B, a pair of terminal electrodes 16A, 16B, and a pair of linking electrodes 18A, 18B. The first inner electrode 12A has a first region R1, located closer to a first terminal connection part 20A than a portion provided with a first linking connection part 22A, and a second region R2 located closer to an opposite side of the first terminal connection part 20A than the portion provided with the first linking connecting part 22A. The second inner electrode 12B has a third region R3, located closer to a second terminal connecting part 20A than a portion provided with a second linking connecting part 22A and a fourth region R4, located closer to an opposite side of the second terminal connection part 20A than the portion provided with the second linking connecting part 22A. The first region R1 has an area smaller than that of the fourth region R4, while the third region R3 has an area smaller than that of the second region R2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multilayer capacitor.

  2. Description of the Related Art Conventionally, there has been known a multilayer capacitor that can be applied to various applications by increasing equivalent series resistance (ESR) and suppressing voltage oscillation of a power source (for example, see Patent Document 1 below). The multilayer capacitor has a rectangular parallelepiped shape, and has a pair of main surfaces facing each other, first and second side surfaces facing each other, and third and fourth side surfaces facing each other, The first terminal electrode disposed on the first side surface, the second terminal electrode disposed on the second side surface, the first connection electrode disposed on the third side surface, and the fourth side surface And a second connecting electrode. The laminated body is formed by alternately laminating first to third internal electrodes with a dielectric layer interposed therebetween.

The first internal electrode extends so that one end portion is exposed on the first side surface and is connected to the first terminal electrode, and extends so that one end portion is exposed on the third side surface. And a connecting protrusion connected to the first connecting electrode (see FIG. 10 of Patent Document 1 below). The second internal electrode includes a terminal protruding portion connected to the second terminal electrode so that one end portion is exposed on the second side surface, and a second projecting portion extending to expose one end portion on the fourth side surface. The connecting protrusions connected to the two connecting electrodes are integrally provided (see the figure). The third internal electrode extends so that one end is exposed on the third side surface and is connected to the first connecting electrode, and extends so that one end is exposed on the fourth side surface. The connection protrusions connected to the second connection electrode are integrally provided (see the same figure). Therefore, the current flows in the order of the first terminal electrode, the first internal electrode, the first and second connection electrodes, and the third internal electrode, and the first internal electrode and the third internal electrode are connected to each other. It will function as the same polarity. As a result, an increase in the flow path of the current in the multilayer capacitor is brought about, and the ESR of the multilayer capacitor is increased accordingly. Thus, by increasing the ESR, the impedance can be increased, and the impedance fluctuation can be reduced over a wide frequency band centered on the resonance frequency.
JP 2003-168620 A

  However, in the conventional multilayer capacitor as in Patent Document 1, even if the ESR is increased and the resonance frequency is increased, the impedance may still decrease in the vicinity of the resonance point frequency (the broken line in FIG. 3). b).

  Therefore, an object of the present invention is to provide a multilayer capacitor capable of suppressing a decrease in impedance in the vicinity of a resonance frequency.

  The inventors of the present invention have intensively studied the cause of the impedance decreasing near the resonance frequency. As a result, the following knowledge was obtained.

  In the multilayer capacitor described in Patent Document 1, the first internal electrode integrally provided with the connecting protrusion connected to the first terminal electrode and the connection connected to the second terminal electrode are provided. The second internal electrode provided integrally with the protruding portion was adjacent to each other through the dielectric layer. That is, the first internal electrode and the second internal electrode having different polarities are adjacent to each other via the dielectric layer. For this reason, a capacitance is generated between the first internal electrode and the second internal electrode.

  By the way, the current flows in the order of the terminal protruding portion, the first internal electrode, and the connecting protruding portion in the first internal electrode, and in the second internal electrode, the connecting protruding portion and the second internal electrode. , Flows in the order of the terminal protrusion. Therefore, the resistance component of the multilayer capacitor is generated between the terminal protruding portion through which current flows, the first internal electrode, and the connecting protruding portion in the first internal electrode, and in the second internal electrode, the terminal Occurs between the projecting portion, the second internal electrode, and the connecting projecting portion. Therefore, in the equivalent circuit of the multilayer capacitor, the portion of the first internal electrode on the opposite side between the terminal protrusion and the connection protrusion, and the terminal protrusion of the second internal electrode. The capacitance (also referred to as parasitic capacitance) Cp generated between the connection protrusion and the connection projection is connected in parallel to the resistance component ESR of the multilayer capacitor (see FIG. 4). The inventors have found that the impedance near the resonance frequency decreases as the parasitic capacitance Cp increases, and the present invention has been completed based on this finding.

  That is, the multilayer capacitor according to the present invention includes an element body in which a plurality of dielectric layers are laminated, first and second terminal electrodes arranged on the outer surface of the element body, and an outer surface of the element body. First and second connection electrodes, and first and second internal electrodes arranged inside the element body in a state of being separated from each other in the stacking direction of the dielectric layers, The electrode is integrally provided with a first terminal connection portion connected to the first terminal electrode and a first connection connection portion connected to the first connection electrode. The internal electrode is integrally provided with a second terminal connection portion connected to the second terminal electrode and a second connection connection portion connected to the second connection electrode. The internal electrode includes a first terminal side region closer to the first terminal connection portion than the portion where the first connection connection portion is provided, and the first connection side. And a first opposite side region opposite to the first terminal connection portion with respect to the portion where the connection portion is provided, and the second internal electrode is provided with the second connection portion. The second terminal side region closer to the second terminal connection part than the part being provided, and the second terminal connection part opposite to the part where the second connection connection part is provided The first terminal side region and the second opposite side region overlap each other when viewed from the stacking direction of the dielectric layer, and the first opposite side region and the second opposite side region Of the first terminal side region is smaller than the area of the second opposite side region, and the terminal side region of the second terminal side region is smaller than the area of the second terminal side region. The area is smaller than the area of the first opposite region.

  In the multilayer capacitor according to the present invention, the first internal electrode includes a first terminal side region closer to the first terminal connection portion than the portion where the first connection connection portion is provided, The first connecting region has a first opposite region opposite to the first terminal connecting portion relative to the portion where the connecting connecting portion is provided, and the second internal electrode is connected to the second connecting connection. The second terminal-side region closer to the second terminal connection portion than the portion where the portion is provided, and the second terminal connection portion than the portion where the second connection portion is provided And a second opposite region on the opposite side. In the multilayer capacitor according to the present invention, the first terminal side region and the second opposite side region overlap each other when viewed from the lamination direction of the dielectric layer, and the first opposite side region and the second opposite side region The terminal side regions overlap each other when viewed from the stacking direction of the dielectric layers, the area of the first terminal side region is smaller than the area of the second opposite side region, and the area of the second terminal side region Is smaller than the area of the first opposite region. Therefore, when the current flows, the facing area between the first terminal side region and the second opposite side region where the resistance component ESR (see FIG. 4) of the multilayer capacitor is generated becomes small, and when the current flows, the multilayer capacitor Since the opposing area between the second terminal side region and the first opposite side region where the resistance component ESR (see FIG. 4) occurs is reduced, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor 4) becomes smaller. As a result, as indicated by a solid line a in FIG. 3, it is possible to suppress a decrease in impedance in the vicinity of the resonance frequency, and impedance fluctuation is suppressed over a wide band including the vicinity of the resonance frequency.

  Preferably, a plurality of openings are provided in the first and second terminal side regions, respectively.

  More preferably, the plurality of openings are arranged in a mesh shape.

  More preferably, the plurality of openings have a long hole shape, and the opening provided in the first terminal side region among the plurality of openings has a longitudinal direction in the first terminal side region and the first terminal region. The openings provided in the second terminal side region among the plurality of openings are arranged so as to extend in the direction in which the opposite side regions are arranged, and the longitudinal direction of the openings is the second terminal side region and the second It arrange | positions so that it may extend in the direction where the opposite area | region is located in a line.

  By the way, in order to reduce the opposing area between the first terminal side region and the second opposite side region and the opposing area between the second terminal side region and the first opposite side region, the first and second It is also conceivable that the terminal side region is, for example, a single thin line. However, in this case, current concentrates on one thin linear portion, and an equivalent series inductance (ESL) increases. The ESL is connected in series with the capacitance C in the equivalent circuit of the multilayer capacitor (see FIG. 4), and acts to prevent rapid charge / discharge of the capacitor. Will be suppressed. However, if a plurality of openings are provided in the first and second terminal-side regions so as to have a mesh shape (mesh shape) or a long hole shape (slit shape) as described above, the first and second regions are provided. Since the current flows in the terminal-side region, the ESL can be reduced. As a result, as indicated by a one-dot chain line c1 in FIG. 3, the impedance can be reduced over the entire high frequency band.

  Preferably, the dielectric layer includes third and fourth internal electrodes disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layers, and the third internal electrode includes a first connection electrode. A third connecting connection portion connected integrally with the fourth internal electrode is integrally provided with a fourth connecting connecting portion connected with the second connecting electrode; The third internal electrode is adjacent to the second internal electrode via the dielectric layer, and the fourth internal electrode is adjacent to the first internal electrode via the dielectric layer. The terminal-side region, the first opposite region, and the fourth internal electrode overlap each other when viewed from the stacking direction of the dielectric layers, and the second terminal-side region, the second opposite-side region, and the third internal electrode overlap each other. These internal electrodes overlap each other when viewed from the stacking direction of the dielectric layers. If it does in this way, an electrostatic capacitance will generate | occur | produce in the part which a 1st other side area | region and a 4th internal electrode overlap, and an electrostatic capacitance will occur in a part where a 2nd other side area | region and a 3rd internal electrode overlap. Will occur. Therefore, it is possible to increase the capacitance of the entire multilayer capacitor. As a result, as indicated by a two-dot chain line c2 in FIG. 3, it is possible to reduce the impedance over the entire low frequency band.

  Preferably, the dielectric layer includes third and fourth internal electrodes disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layers, and the third internal electrode includes a first connection electrode. A third connecting connection portion connected integrally with the fourth internal electrode is integrally provided with a fourth connecting connecting portion connected with the second connecting electrode; The third and fourth internal electrodes are located between the first internal electrode and the second internal electrode inside the element body, and the third internal electrode is connected to the first internal electrode via the dielectric layer. The fourth internal electrode is adjacent to the second internal electrode via the dielectric layer, and the first terminal side region, the first opposite side region, and the third internal electrode are adjacent to each other. The internal electrodes overlap each other when viewed from the stacking direction of the dielectric layers, and the second terminal side region, the second opposite side region, and the fourth electrode The part electrode, overlap each other when viewed from the stacking direction of the dielectric layer. In this case, the first internal electrode electrically connected to the first terminal electrode is not adjacent to the second and fourth internal electrodes having different polarities in the stacking direction, and the second terminal electrode The second internal electrode that is electrically connected is not adjacent to the first and third internal electrodes that have different polarities in the stacking direction. Therefore, due to the presence of the third internal electrode having the same polarity as the first internal electrode connected to the first terminal electrode, the first internal electrode is different from the fourth internal electrode having a different polarity in the stacking direction. Due to the presence of the fourth internal electrode having the same polarity as the second internal electrode connected to the second terminal electrode, the second internal electrode has a different polarity from the third internal electrode. It will not be adjacent to the internal electrode in the stacking direction. As a result, the parasitic capacitance can be further reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the multilayer capacitor which can suppress the fall of the impedance in the vicinity of the resonant frequency can be provided.

  A preferred embodiment of a multilayer capacitor 1 according to the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

  A configuration of the multilayer capacitor 1 according to the present embodiment will be described with reference to FIGS. 1 and 2. The multilayer capacitor 1 includes a rectangular parallelepiped dielectric body (element body) 10, internal electrodes 12A (first internal electrodes), 12B (second internal electrodes), 14A (third internal electrodes), 14B ( Fourth internal electrode), terminal electrodes 16A (first terminal electrodes), 16B (second terminal electrodes), connecting electrodes 18A (first connecting electrodes), 18B (second connecting electrodes) ).

  Dielectric body 10 has main surfaces 10a and 10b facing each other, side surfaces 10c and 10d facing each other, and side surfaces 10e and 10f facing each other. In the present embodiment, the main surface 10a or the main surface 10b is a mounting surface that faces the main surface of a circuit board (not shown).

  The side surfaces 10c and 10d extend so as to connect the main surfaces 10a and 10b and the side surfaces 10e and 10f. The side surfaces 10e and 10f extend so as to connect the main surfaces 10a and 10b and the side surfaces 10c and 10d. In the present embodiment, the length of the dielectric body 10 in the longitudinal direction can be set, for example, to about 1.0 mm, the width, for example, about 0.5 mm, and the thickness, for example, about 0.5 mm. Since dielectric body 10 is usually barrel-polished after firing, the ridge portion of dielectric body 10 has a curved surface shape having a predetermined curvature (not shown).

  As shown in FIG. 2, the dielectric body 10 is configured by laminating rectangular dielectric layers A <b> 10 to A <b> 18 in this order. That is, the upper surface of the dielectric layer A10 constitutes the main surface 10a of the dielectric element body 10, and the lower surface of the dielectric layer A18 constitutes the main surface 10b of the dielectric element body 10, and the main surfaces 10a, 10b The facing direction (hereinafter referred to as the facing direction) corresponds to the stacking direction (hereinafter referred to as the stacking direction) of the dielectric body 10 (dielectric layers A10 to A18) in the present embodiment.

  The dielectric layers A10 to A18 function as an insulator having electrical insulation. The dielectric layers A10 to A18 can be formed of, for example, a dielectric ceramic material obtained by adding a rare earth element to barium titanate or strontium titanate. The actual dielectric body 10 is integrated by firing so that the boundaries between the dielectric layers A10 to A18 cannot be visually recognized.

  A rectangular internal electrode 12A is formed on each surface of the dielectric layers A11 and A17. The internal electrode 12A extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 12A is integrally provided with a terminal connection portion 20A (first terminal connection portion) on the short side on the side surface 10c side. The terminal connecting portion 20A has the same width as the internal electrode 12A and is drawn out to the edge of the dielectric layers A11 and A17 on the side where the terminal electrode 16A is formed, and its end is exposed to the side surface 10c. The internal electrode 12A is integrally provided with a connecting portion 22A (first connecting portion) for connection at the center of the long side on the side surface 10e. The connecting portion 22A is drawn out to the edge of the dielectric layers A11 and A17 on the side where the connecting electrode 18A is formed with a sufficiently small width with respect to the internal electrode 12A, and its end is exposed to the side surface 10e. .

  The internal electrode 12A has a region R1 (first terminal side region) closer to the terminal connecting portion 20A than a portion where the connecting portion 22A is provided and a portion where the connecting portion 22A is provided. It has a region R2 (first opposite region) opposite to the terminal connection portion 20A. The region R1 is provided with a plurality of square openings 24A (16 in the present embodiment). These openings 24A are arranged so as to be 4 rows × 4 columns in the region R1, that is, in a mesh shape (mesh shape).

  A rectangular internal electrode 12B is formed on each surface of the dielectric layers A12 and A18. The internal electrode 12B extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 12B is integrally provided with a terminal connection portion 20B (second terminal connection portion) on the short side on the side surface 10d side. The terminal connection portion 20B has the same width as that of the internal electrode 12B and is drawn out to the edge of the dielectric layers A12 and A18 on the side where the terminal electrode 16B is formed, and its end portion is exposed to the side surface 10d. The internal electrode 12B is integrally provided with a connecting portion 22B (second connecting portion) for connection at the center of the long side on the side surface 10f side. The connecting portion 22B is drawn to the edge of the dielectric layers A12 and A18 on the side where the connecting electrode 18B is formed with a sufficiently small width with respect to the internal electrode 12B, and its end is exposed to the side surface 10f. .

  The internal electrode 12B has a region R3 (second terminal side region) closer to the terminal connecting portion 20A than a portion where the connecting portion 22A is provided, and a portion where the connecting portion 22A is provided. It has a region R4 (second opposite region) opposite to the terminal connection portion 20A. In the region R3, a plurality of square openings 24B (16 in the present embodiment) are provided. These openings 24B are arranged so as to be 4 rows × 4 columns in the region R3, that is, in a mesh shape (mesh shape).

  A rectangular internal electrode 14A is formed on each surface of the dielectric layers A13 and A15. The internal electrode 14A extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 14A is integrally provided with a connecting portion 26A (third connecting portion for connection) at the center of the long side on the side surface 10e side. The connecting portion 24A is drawn out to the edge of the dielectric layers A13 and A15 on the side where the connecting electrode 18A is formed with a sufficiently small width with respect to the internal electrode 14A, and its end is exposed to the side surface 10e. .

  A rectangular internal electrode 14B is formed on each surface of the dielectric layers A14 and A16. The internal electrode 14B extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 14B is integrally provided with a connecting portion 26B (fourth connecting portion) for connection at the center of the long side on the side surface 10f side. The connecting portion 24B is drawn out to the edge of the dielectric layers A14 and A16 on the side where the connecting electrode 18B is formed with a sufficiently small width with respect to the internal electrode 14B, and its end is exposed to the side surface 10f. .

  The internal electrodes 12A, 12B, 14A, and 14B are all disposed inside the dielectric body 10, and the internal electrodes 12A, 12B, 14A, 14B, 14A, 14B, and 12A are disposed via the dielectric layers A11 to A17. , 12B in this order. That is, the internal electrodes 12A, 12B, 14A, and 14B are arranged inside the dielectric body 10 in a state of being separated from each other by the thickness of the dielectric layers A11 to A18.

  The internal electrodes 12A, 12B, 14A, and 14B all overlap each other when viewed from the stacking direction (opposite direction of the main surfaces 10a and 10b). More specifically, the region R1 of the internal electrode 12A and the region R4 of the internal electrode 12B overlap each other when viewed from the stacking direction, and the region R2 of the internal electrode 12A and the region R3 of the internal electrode 12B are viewed from the stacking direction. Overlap each other. The regions R3 and R4 of the internal electrode 12B formed on the dielectric layer A12 and the internal electrode 14A formed on the dielectric layer A13 overlap each other when viewed from the stacking direction, and the dielectric The regions R1 and R2 of the internal electrode 12A formed on the layer A17 and the internal electrode 14B formed on the dielectric layer A16 overlap each other when viewed from the stacking direction. Therefore, the facing area of the internal electrodes 14A and 14B when viewed from the stacking direction, the distance between the internal electrodes 14A and 14B (that is, the thickness of the dielectric layers A13 to A15), and the dielectric layer when viewed from the stacking direction. The facing area between the region R4 of the internal electrode 12B formed on A12 and the internal electrode 14A formed on the dielectric layer A13 and the distance between the internal electrodes 12B and 14A (that is, the thickness of the dielectric layer A12) In addition, the area of the internal electrode 12A formed on the dielectric layer A17 when viewed from the stacking direction R2 and the facing area between the internal electrode 14B formed on the dielectric layer A16 and the internal electrode 12A, The capacitance of the multilayer capacitor 1 is defined by the interval of 14B (that is, the thickness of the dielectric layer A16).

  The internal electrodes 12A, 12B, 14A, 14B are made of a conductive material such as Ag or Ni, for example. The internal electrodes 12A, 12B, 14A, and 14B are configured as a sintered body of a conductive paste containing the conductive material.

  The terminal electrode 16A is formed so as to cover the side surface 10c of the dielectric body 10 and wrap around the main surfaces 10a, 10b and the side surfaces 10e, 10f adjacent to the side surface 10c. That is, the terminal electrode 16A is disposed on the side surface 10c and the main surfaces 10a and 10b and the side surfaces 10e and 10f near the side surface 10c. The terminal electrode 16A is physically and electrically connected to the terminal connection portion 20A whose end is exposed on the side surface 10c. As a result, the terminal electrode 16A and the internal electrode 12A are electrically connected.

  The terminal electrode 16B covers the side surface 10d of the dielectric element body 10 and is formed so as to go around the main surfaces 10a and 10b and the side surfaces 10e and 10f adjacent to the side surface 10d. In other words, the terminal electrode 16B is disposed on the side surface 10d and the main surfaces 10a and 10b and the side surfaces 10e and 10f near the side surface 10d. The terminal electrode 16B is physically and electrically connected to the terminal connection portion 20B whose end is exposed on the side surface 10d. Thereby, the terminal electrode 16B and the internal electrode 12B are electrically connected.

  The connecting electrode 18A has a rectangular shape and is formed so as to cover the side surface 10e of the dielectric body 10 and to wrap around the main surfaces 10a and 10b adjacent to the side surface 10e. That is, the connecting electrode 18A is disposed on the side surface 10e and the portion of the main surfaces 10a and 10b near the side surface 10e. The connection electrode 18A is physically and electrically connected to the connection portions 22A and 26A for connection whose end portions are exposed on the side surface 10e. As a result, the internal electrode 12A and the internal electrode 14A are electrically connected to each other via the coupling electrode 18A. That is, the internal electrode 12A and the internal electrode 14A have the same polarity.

  The connecting electrode 18B has a rectangular shape and is formed so as to cover the side surface 10f of the dielectric body 10 and to wrap around the main surfaces 10a and 10b adjacent to the side surface 10f. That is, the connecting electrode 18B is disposed on the side surface 10f and the portion of the main surfaces 10a and 10b that is closer to the side surface 10f. The connecting electrode 18B is physically and electrically connected to the connecting portions 22B and 26B whose ends are exposed on the side surface 10f. As a result, the internal electrode 12B and the internal electrode 14B are electrically connected to each other via the coupling electrode 18B. That is, the internal electrode 12B and the internal electrode 14B have the same polarity.

  The terminal electrodes 16A and 16B and the connecting electrodes 18A and 18B are formed by applying and baking a conductive paste containing conductive metal powder and glass frit, for example, on the outer surface of the dielectric body 10. If necessary, a plating layer may be formed on the baked terminal electrodes 16A and 16B and the connecting electrodes 18A and 18B.

  In the present embodiment as described above, the internal electrode 12A includes the region R1 closer to the terminal connection portion 20A than the portion where the connection portion 22A is provided and the portion where the connection portion 22A is provided. And the opposite side region R2 opposite to the terminal connection portion 20A, and the internal electrode 12B is closer to the terminal connection portion 20B than the portion where the connection portion 22B is provided. The region has a region R3 and a region R4 on the opposite side of the terminal connecting portion 20A from the portion where the connecting connecting portion 22B is provided. In the present embodiment, the region R1 and the region R4 overlap each other when viewed from the stacking direction, and the region R3 and the region R4 overlap each other when viewed from the stacking direction. Further, in the present embodiment, the regions R1 and R3 are provided with a plurality of openings 24A and 24B, respectively, whereby the area of the region R1 is smaller than the area of the region R4, and the area of the region R3 is the region. It is smaller than the area of R2. Therefore, when the current flows, the facing area between the region R1 and the region R4 where the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 is generated becomes small, and when the current flows, the resistance component ESR of the multilayer capacitor 1 (see FIG. 4). 4)), the parasitic area Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor 1 is reduced. As a result, it is possible to suppress a decrease in impedance near the resonance frequency, and as shown by a solid line a in FIG. 3, impedance fluctuation is suppressed over a wide band including the vicinity of the resonance frequency.

  By the way, in order to reduce the facing area between the region R1 and the region R4 and the facing area between the region R3 and the region R2, it is conceivable that the regions R1 and R3 are, for example, a single thin line. However, in this case, the current flows in a concentrated manner on a single linear portion, and ESL increases. The ESL is connected in series with the capacitance C in the equivalent circuit of the multilayer capacitor 1 (see FIG. 4), and acts to prevent rapid charge / discharge of the capacitor. Speeding up will be suppressed. However, as described above, if a plurality of openings 24A and 24B are provided in the respective regions R1 and R3 so as to have a mesh shape (mesh shape), currents are distributed and flow in the regions R1 and R3. Therefore, ESL can be reduced. As a result, as indicated by a one-dot chain line c1 in FIG. 3, the impedance can be reduced over the entire high frequency band.

  In the present embodiment, the internal electrode 12B is adjacent to the internal electrode 14A via the dielectric layer A12, and the internal electrode 12A is adjacent to the internal electrode A14B via the dielectric layer A16. The region R4 and the internal electrode 14A overlap each other when viewed from the stacking direction, and the region R2 and the internal electrode 14B overlap each other when viewed from the stacking direction. Therefore, a capacitance is generated at a portion where the region R4 and the internal electrode 14A overlap, and a capacitance is generated at a portion where the region R3 and the internal electrode 14B overlap. Accordingly, the capacitance of the multilayer capacitor 1 as a whole can be increased. As a result, as indicated by a two-dot chain line c2 in FIG. 3, it is possible to reduce the impedance over the entire low frequency band.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in the present embodiment, two sets of internal electrodes 12A and 12B are arranged inside the dielectric body 10, but as shown in FIGS. 5 and 6, one set is placed inside the dielectric body 10. The internal electrodes 12A and 12B may be arranged, or three or more sets of internal electrodes 12A and 12B may be arranged (not shown).

  In FIG. 5, the dielectric body 10 is configured by laminating dielectric layers A <b> 10 to A <b> 16 in this order, and the internal electrodes 12 </ b> A, 12 </ b> B, 14 </ b> A, 14 </ b> B are formed inside the dielectric body 10. The internal electrodes 12A, 12B, 14A, 14B, 14A, and 14B are stacked in this order via the dielectric layers A11 to A15. In FIG. 6, the dielectric body 10 is configured by laminating dielectric layers A10, A11, A14, A13, A16, A15, A12 in this order, and the internal electrodes 12A, 12B, 14A, 14B is laminated in the order of the internal electrodes 12A, 14B, 14A, 14B, 14A, and 12B through the dielectric layers A11, A14, A13, A16, and A15 in the dielectric body 10.

  In the present embodiment, the internal electrodes 14A and 14B are disposed between the internal electrode 12A and the internal electrode 12B. However, as shown in FIG. 5, the internal electrodes 12A and 12B are adjacent to each other in the stacking direction. May be.

  Further, as shown in FIG. 6, the internal electrodes 14A and 14B may be arranged between the pair of internal electrodes 12A and 12B.

  In the present embodiment, a plurality of square openings 24A are provided in the region R1 of the internal electrode 12A, and a plurality of square openings 24B are provided in the region R3 of the internal electrode 12B. 24A and 24B may have various shapes such as a polygonal shape (triangular shape, quadrangular shape, etc.), a circular shape, an elliptical shape, and a long hole shape. For example, as shown in FIG. 6, a plurality (four in FIG. 6) of rectangular (slit) openings 28A are provided in the region R1 of the internal electrode 12A, and the rectangular openings are formed in the region R3 of the internal electrode 12B. A plurality of 28B (four in FIG. 6) may be provided. Here, in FIG. 6, the opening 28A is provided in the region R1 so that the longitudinal direction (slit shape) of the opening 28A extends in the direction in which the regions R1 and R2 are arranged, and the longitudinal direction of the opening 28B is the region. An opening 28B is provided in the region R3 so as to extend in the direction in which R3 and R4 are arranged, and a plurality of openings 28A and 28B are arranged in the opposing direction of the side surfaces 10c and 10d. However, the present invention is not limited thereto, and if the area of the region R1 is smaller than the area of the region R4 and the area of the region R3 is smaller than the area of the region R2, an effect of suppressing a decrease in impedance near the resonance frequency can be obtained. It becomes.

  When the linear distance from the main surface 10a to the internal electrode 12A is different from the linear distance from the main surface 10b to the internal electrode 12B, the multilayer capacitor 1 is mounted on the circuit board using the main surface 10a as a mounting surface. The path through which the current flows is different between the case where the multilayer capacitor 1 is mounted on the circuit board with the main surface 10b as the mounting surface, and the high frequency characteristics may change depending on the mounting state of the multilayer capacitor 1 on the circuit board. It can happen. However, as shown in FIG. 6, if the linear distance from the main surface 10a to the internal electrode 12A and the linear distance from the main surface 10b to the internal electrode 12B are substantially the same, that is, the dielectric layer A10 It is preferable that the thickness and the thickness of the dielectric layer A12 are substantially equal because there is almost no possibility that the high-frequency characteristics are changed. Since the multilayer capacitor is an industrial product and an error occurs within a certain range, the “substantially the same” here includes the identity within the error range of the industrial product.

  In the present embodiment, the pair of internal electrodes 12A and 12B are adjacent in the stacking direction. However, as shown in FIG. 7, the internal electrode 14A is connected to the internal electrode 12A having the same polarity on both sides in the stacking direction. The internal electrodes 14B may be disposed adjacent to each other, and the internal electrodes 14B may be disposed adjacent to the internal electrodes 12B having the same polarity on both sides in the stacking direction. In this case, due to the presence of the internal electrode 14A having the same polarity as the internal electrode 12A connected to the terminal electrode 16A, the internal electrode 12A does not face the internal electrode 14B having a different polarity adjacently in the stacking direction. Because of the presence of the internal electrode 14B having the same polarity as the internal electrode 12B connected to the terminal electrode 16B, the internal electrode 12B does not face the internal electrode 14A having a different polarity adjacently in the stacking direction. As a result, the parasitic capacitance can be further reduced, which is preferable.

  In FIG. 7, the dielectric body 10 is configured by laminating dielectric layers A10, A19, A11, A20, A21, A12, A22, A13, A14 in this order, and the internal electrodes 12A, 12B, 14A, and 14B are internal electrodes 14A, 12A, 14A, 14B, 12B, 14B, and 14A through the dielectric layers A19, A11, A20, A21, A12, A22, and A13 inside the dielectric body 10, respectively. , 14B in this order.

  Further, the number of internal electrodes 14A and 14B and the number of dielectric layers may be appropriately set as desired.

FIG. 1 is a perspective view showing the multilayer capacitor in accordance with this embodiment. FIG. 2 is an exploded perspective view showing a dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 3 is a diagram illustrating impedance characteristics of the multilayer capacitor according to the present embodiment and the conventional multilayer capacitor. FIG. 4 is a diagram showing an equivalent circuit of the multilayer capacitor. FIG. 5 is an exploded perspective view showing another example (first example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 6 is an exploded perspective view showing another example (second example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 7 is an exploded perspective view showing another example (third example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 10 ... Dielectric body (element body), 12A ... Internal electrode (1st internal electrode), 12B ... Internal electrode (2nd internal electrode), 14A ... Internal electrode (3rd internal electrode) , 14B ... internal electrode (fourth internal electrode), 16A ... terminal electrode (first terminal electrode), 16B ... terminal electrode (second terminal electrode), 18A ... connection electrode (first connection electrode) ), 18B ... Connecting electrode (second connecting electrode), 20A ... Terminal connecting portion (first terminal connecting portion), 20B ... Terminal connecting portion (second terminal connecting portion), 22A ... Connection for connection (first connection for connection), 22B ... Connection for connection (second connection for connection), 24A, 24B ... Opening, 26A ... Connection for connection (third connection for connection) Part), 26B ... connection part for connection (fourth connection part for connection), R1 ... region (first terminal side region), R2 Area (first area opposite), R3 ... region (second terminal side region), R4 ... region (second region opposite).

Claims (6)

An element body in which a plurality of dielectric layers are laminated;
First and second terminal electrodes disposed on the outer surface of the element body;
First and second connection electrodes disposed on the outer surface of the element body;
A first internal electrode and a second internal electrode disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layer;
The first internal electrode is integrally formed with a first terminal connection portion connected to the first terminal electrode and a first connection connection portion connected to the first connection electrode. Provided in
The second internal electrode is integrally formed with a second terminal connection portion connected to the second terminal electrode and a second connection connection portion connected to the second connection electrode. Provided in
The first internal electrode includes a first terminal side region closer to the first terminal connection portion than a portion where the first connection connection portion is provided, and the first connection connection portion. And a first opposite side region opposite to the first terminal connection portion than a portion where the first terminal connection portion is provided,
The second internal electrode includes a second terminal side region closer to the second terminal connection portion than a portion where the second connection connection portion is provided, and the second connection connection portion. Having a second opposite region opposite to the second terminal connection portion than the portion provided with
The first terminal side region and the second opposite side region overlap each other when viewed from the stacking direction of the dielectric layer,
The first opposite side region and the second terminal side region overlap each other when viewed from the stacking direction of the dielectric layer,
The area of the first terminal side region is smaller than the area of the second opposite side region,
The multilayer capacitor characterized in that an area of the second terminal side region is smaller than an area of the first opposite side region.   The multilayer capacitor according to claim 1, wherein a plurality of openings are provided in each of the first and second terminal side regions.   The multilayer capacitor according to claim 2, wherein the plurality of openings are arranged in a mesh shape. The plurality of openings have a long hole shape,
Of the plurality of openings, the opening provided in the first terminal side region is arranged such that its longitudinal direction extends in a direction in which the first terminal side region and the first opposite region are arranged. And
Of the plurality of openings, the opening provided in the second terminal side region is arranged such that its longitudinal direction extends in a direction in which the second terminal side region and the second opposite region are arranged. The multilayer capacitor according to claim 2, wherein the multilayer capacitor is provided. A third and a fourth internal electrode disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layer;
The third internal electrode is integrally provided with a third connection for connection that is connected to the first connection electrode,
The fourth internal electrode is integrally provided with a fourth connecting connection portion connected to the second connecting electrode,
The third internal electrode is adjacent to the second internal electrode through the dielectric layer,
The fourth internal electrode is adjacent to the first internal electrode through the dielectric layer,
The first terminal side region and the first opposite region and the fourth internal electrode overlap each other when viewed from the stacking direction of the dielectric layer,
5. The second terminal side region, the second opposite side region, and the third internal electrode overlap each other when viewed from the stacking direction of the dielectric layers. The multilayer capacitor described in any one of the above. A third and a fourth internal electrode disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layer;
The third internal electrode is integrally provided with a third connection for connection that is connected to the first connection electrode,
The fourth internal electrode is integrally provided with a fourth connecting connection portion connected to the second connecting electrode,
The third and fourth internal electrodes are located between the first internal electrode and the second internal electrode inside the element body,
The third internal electrode is adjacent to the first internal electrode through the dielectric layer,
The fourth internal electrode is adjacent to the second internal electrode through the dielectric layer,
The first terminal-side region and the first opposite-side region and the third internal electrode overlap each other when viewed from the stacking direction of the dielectric layer,
The second terminal-side region, the second opposite-side region, and the fourth internal electrode overlap each other when viewed from the stacking direction of the dielectric layers. The multilayer capacitor described in any one of the above.

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