JP5077180B2 - Multilayer capacitor - Google Patents

Multilayer capacitor Download PDF

Info

Publication number
JP5077180B2
JP5077180B2 JP2008264125A JP2008264125A JP5077180B2 JP 5077180 B2 JP5077180 B2 JP 5077180B2 JP 2008264125 A JP2008264125 A JP 2008264125A JP 2008264125 A JP2008264125 A JP 2008264125A JP 5077180 B2 JP5077180 B2 JP 5077180B2
Authority
JP
Japan
Prior art keywords
internal electrode
electrode
connection
internal
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008264125A
Other languages
Japanese (ja)
Other versions
JP2010093193A (en
Inventor
正明 富樫
崇 青木
Original Assignee
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk株式会社 filed Critical Tdk株式会社
Priority to JP2008264125A priority Critical patent/JP5077180B2/en
Priority claimed from US12/497,970 external-priority patent/US8189321B2/en
Publication of JP2010093193A publication Critical patent/JP2010093193A/en
Application granted granted Critical
Publication of JP5077180B2 publication Critical patent/JP5077180B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a multilayer capacitor.

  2. Description of the Related Art Conventionally, there has been known a multilayer capacitor that can be applied to various applications by increasing equivalent series resistance (ESR) and suppressing voltage oscillation of a power source (for example, see Patent Document 1 below). The multilayer capacitor has a rectangular parallelepiped shape, and has a pair of main surfaces facing each other, first and second side surfaces facing each other, and third and fourth side surfaces facing each other, The first terminal electrode disposed on the first side surface, the second terminal electrode disposed on the second side surface, the first connection electrode disposed on the third side surface, and the fourth side surface And a second connecting electrode. The laminate is formed by alternately laminating first to fourth internal electrodes with a dielectric layer interposed therebetween.

The first internal electrode extends so that one end portion is exposed on the first side surface and is connected to the first terminal electrode, and extends so that one end portion is exposed on the third side surface. And a connecting protrusion connected to the first connecting electrode (see FIG. 10 of Patent Document 1 below). The second internal electrode includes a terminal protruding portion connected to the second terminal electrode so that one end portion is exposed on the second side surface, and an end portion extending so that the one end portion is exposed on the fourth side surface. The connecting protrusions connected to the two connecting electrodes are integrally provided (see the figure). The third internal electrode is integrally provided with a connecting protrusion that is connected to the first connecting electrode by extending so that one end is exposed on the third side surface (see the same drawing). The fourth internal electrode is integrally provided with a connecting protrusion that is connected to the second coupling electrode so as to be exposed at one end on the fourth side surface (see the same figure). Therefore, the current flows in the order of the first terminal electrode, the first internal electrode, the first connection electrode, and the third internal electrode, and the first internal electrode and the third internal electrode function as the same polarity. It will be. Further, the current flows in the order of the fourth internal electrode, the second connection electrode, the second internal electrode, and the second terminal electrode, and the second internal electrode and the fourth internal electrode function as the same polarity. It will be. As a result, an increase in the flow path of the current in the multilayer capacitor is brought about, and the ESR of the multilayer capacitor is increased accordingly. Thus, by increasing the ESR, the impedance can be increased, and the impedance fluctuation can be reduced over a wide frequency band centered on the resonance frequency.
JP 2003-168620 A

  However, in the conventional multilayer capacitor as in Patent Document 1, even if the ESR is increased to increase the resonance frequency, the impedance may still decrease in the vicinity of the resonance frequency (the broken line b in FIG. 3). reference).

  Therefore, an object of the present invention is to provide a multilayer capacitor capable of suppressing a decrease in impedance in the vicinity of a resonance frequency.

  The inventors of the present invention have intensively studied the cause of the impedance decreasing near the resonance frequency. As a result, the following knowledge was obtained.

  In the multilayer capacitor described in Patent Document 1, the first internal electrode integrally provided with the connecting protrusion connected to the first terminal electrode and the connection connected to the second terminal electrode are provided. The second internal electrode provided integrally with the protruding portion was adjacent to each other through the dielectric layer. That is, the first internal electrode and the second internal electrode having different polarities are adjacent to each other via the dielectric layer. For this reason, a capacitance is generated between the first internal electrode and the second internal electrode.

  By the way, the current flows in the order of the terminal protruding portion, the first internal electrode, and the connecting protruding portion in the first internal electrode, and in the second internal electrode, the connecting protruding portion and the second internal electrode. And the terminal protrusion. Therefore, the resistance component of the multilayer capacitor is generated between the terminal protruding portion through which current flows, the first internal electrode, and the connecting protruding portion in the first internal electrode, and in the second internal electrode, the terminal Occurs between the projecting portion, the second internal electrode and the connecting projecting portion. Therefore, in the equivalent circuit of the multilayer capacitor, the terminal projecting portion and the connection projecting portion of the second internal electrode, and the portion on the opposite side of the terminal projecting portion and the connecting projecting portion of the first internal electrode. Capacitance (also referred to as parasitic capacitance) Cp generated between the part and the part is connected in parallel to the resistance component ESR of the multilayer capacitor (see FIG. 4). The inventors have found that the impedance near the resonance frequency decreases as the parasitic capacitance Cp increases, and the present invention has been completed based on this finding.

  That is, the multilayer capacitor according to the present invention includes an element body in which a plurality of dielectric layers having at least first to third dielectric layers are laminated, and first and second elements disposed on the outer surface of the element body. Comprising a terminal electrode, first and second connecting electrodes disposed on the outer surface of the element body, and first to fourth inner electrodes disposed inside the element body. The internal electrode is disposed on the first dielectric layer in a state of being separated from each other, the second internal electrode is disposed on the second dielectric layer, and the third internal electrode is formed on the third dielectric layer. The first internal electrode is connected to the first terminal electrode, and the first connection connection is connected to the first connection electrode. And the second internal electrode connected to the second terminal connection portion connected to the second terminal electrode and the second connection electrode. A second connecting connection portion is integrally provided, and the third internal electrode is integrally provided with a third connecting connection portion connected to the first connecting electrode. The fourth internal connection electrode is integrally provided with a fourth connection portion that is connected to the second connection electrode, and the third internal electrode includes the first and first connection layers in the stacking direction of the plurality of dielectric layers. 4, the first and fourth internal electrodes and the third internal electrode overlap each other when viewed from the stacking direction of the plurality of dielectric layers.

  In the multilayer capacitor according to the present invention, the first internal electrode includes a first terminal connection portion connected to the first terminal electrode and a first connection connection portion connected to the first connection electrode. The third internal connection electrode is provided integrally with the third internal connection electrode connected to the first connection electrode, and the first internal electrode and the first internal electrode are of the same polarity. The third internal electrodes are adjacent to each other in the stacking direction of the plurality of dielectric layers and overlap each other when viewed from the stacking direction of the plurality of dielectric layers. Therefore, the first internal electrode in which the resistance component ESR (see FIG. 4) of the multilayer capacitor is generated when a current flows is not adjacent to the opposite electrode on the side adjacent to the third internal electrode. The parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. As a result, as shown by a solid line in FIG. 3, it is possible to suppress a decrease in impedance in the vicinity of the resonance frequency, and to suppress a variation in impedance over a wide band including the vicinity of the resonance frequency.

  Moreover, in the multilayer capacitor according to the present invention, the first connection for connection to the first internal electrode, the first terminal connection connected to the first terminal electrode, and the first connection electrode. Are integrally provided, and the fourth internal electrode is integrally provided with a fourth connection portion connected to the second connection electrode, and the first and fourth internal electrodes are Arranged in the first dielectric layer. Therefore, the first internal electrode and the fourth internal electrode having different polarities are both disposed on the same dielectric layer. As a result, since the number of dielectric layers constituting the element body is reduced, the multilayer capacitor can be miniaturized.

  Further, in the multilayer capacitor according to the present invention, the third internal connection is integrally provided with the third internal electrode, and the third internal connection is connected to the first internal connection electrode. A fourth connecting connection portion connected to the connecting electrode is integrally provided, and a third internal electrode and a fourth internal electrode having different polarities are laminated with a plurality of dielectric layers. They overlap each other when viewed from the direction. Therefore, the capacitance component C (see FIG. 4) of the multilayer capacitor is between the third internal electrode and the fourth internal electrode where the resistance component ESR (see FIG. 4) of the multilayer capacitor does not occur when current flows. Will occur. As a result, as described above, in combination with the fact that the first internal electrode and the fourth internal electrode having different polarities are arranged on the same dielectric layer, the size of the multilayer capacitor can be reduced. It is possible to increase the capacitance of the multilayer capacitor as a whole. As a result, as indicated by a two-dot chain line c2 in FIG. 3, the impedance can be lowered over the entire low frequency band.

  Preferably, a fifth internal electrode disposed inside the element body is provided, and the fifth internal electrode is integrally provided with a fifth connection portion connected to the first connection electrode. The fifth internal electrode is adjacent to the first internal electrode in the stacking direction of the plurality of dielectric layers, and the first internal electrode and the fifth internal electrode are stacked in the stacking direction of the plurality of dielectric layers. Viewed from above. In this way, the first internal electrode in which the resistance component ESR (see FIG. 4) of the multilayer capacitor when the current flows is adjacent to the opposite electrode on the side adjacent to the fifth internal electrode. As a result, the parasitic capacitance Cp (see FIG. 4) connected in parallel with the resistance component of the multilayer capacitor can be further reduced.

  More preferably, the second internal electrode and the fifth internal electrode are disposed on the second dielectric layer in a state of being separated from each other. If it does in this way, the 2nd internal electrode and the 5th internal electrode which are mutually different polarities will be arranged on the same dielectric layer. As a result, since the number of dielectric layers constituting the element body is reduced, the multilayer capacitor can be miniaturized.

  Preferably, the substrate includes fifth and sixth internal electrodes arranged inside the element body, the plurality of dielectric layers include a fourth dielectric layer, and the second internal electrode and the fifth internal electrode Is arranged on the second dielectric layer in a state of being separated from each other, the sixth internal electrode is arranged on the fourth dielectric layer, and the fifth internal electrode is connected to the first coupling layer. A fifth connecting connection portion connected to the electrode is integrally provided, and a sixth connecting connection portion connected to the second connecting electrode is integrally provided on the sixth internal electrode. The sixth internal electrode is adjacent to the second and fifth internal electrodes in the stacking direction of the plurality of dielectric layers, and the second and fifth internal electrodes and the sixth internal electrode include a plurality of The dielectric layers overlap each other when viewed from the stacking direction. In this way, the second internal electrode in which the resistance component ESR of the multilayer capacitor (see FIG. 4) occurs when a current flows is adjacent to the opposite electrode on the side adjacent to the sixth internal electrode. As a result, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. As a result, as shown by a solid line in FIG. 3, it is possible to suppress a decrease in impedance in the vicinity of the resonance frequency, and to suppress a variation in impedance over a wide band including the vicinity of the resonance frequency. In this case, the second internal electrode and the fifth internal electrode having different polarities are both disposed on the same dielectric layer. As a result, since the number of dielectric layers constituting the element body is reduced, the multilayer capacitor can be miniaturized. Further, in this way, when the current flows, the resistance component ESR (see FIG. 4) of the multilayer capacitor does not occur between the second internal electrode and the sixth internal electrode. (See FIG. 4). As a result, as described above, in combination with the fact that the second internal electrode and the fifth internal electrode having different polarities are both disposed on the same dielectric layer, the size of the multilayer capacitor can be reduced. It is possible to increase the capacitance of the multilayer capacitor as a whole. As a result, as indicated by a two-dot chain line c2 in FIG. 3, the impedance can be lowered over the entire low frequency band.

  More preferably, the device includes seventh and eighth internal electrodes disposed inside the element body, the plurality of dielectric layers include fifth and sixth dielectric layers, and the seventh internal electrode includes: The seventh internal electrode is disposed on the fifth dielectric layer, the eighth internal electrode is disposed on the sixth dielectric layer, and the seventh internal electrode is connected to the first coupling electrode. The connection part for connection is provided integrally, the eighth internal electrode is provided with the eighth connection part for connection connected to the second connection electrode, and the seventh internal electrode is The eighth internal electrode is adjacent to the second internal electrode in the stacking direction of the plurality of dielectric layers, and the eighth internal electrode is adjacent to the second internal electrode in the stacking direction of the plurality of dielectric layers. The internal electrode and the seventh internal electrode overlap each other when viewed from the stacking direction of the plurality of dielectric layers, and the second internal electrode and the eighth internal electrode They are overlap each other when viewed from the laminate direction of the plurality of dielectric layers. In this way, the first internal electrode in which the resistance component ESR (see FIG. 4) of the multilayer capacitor when the current flows is adjacent to the opposite electrode on the side adjacent to the seventh internal electrode. As a result, the parasitic capacitance Cp (see FIG. 4) connected in parallel with the resistance component of the multilayer capacitor can be further reduced. Further, in this case, the second internal electrode in which the resistance component ESR (see FIG. 4) of the multilayer capacitor is generated when a current flows is adjacent to the different polarity on the side adjacent to the eighth internal electrode. Since they do not face each other, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor can be further reduced.

  Preferably, the first internal electrode has a first terminal side region closer to the first terminal connection portion than the portion where the first connection connection portion is provided, and the second internal electrode is , Having a second terminal side region closer to the second terminal connection portion than the portion where the second connecting connection portion is provided, and the first and second terminal side regions have a plurality of Each opening is provided.

  More preferably, the plurality of openings are arranged in a mesh shape.

  By the way, in order to reduce the opposing area between the first internal electrode and its different polarity, and the opposing area between the second internal electrode and its different polarity, the first and second internal electrodes are made thin, for example. It is also conceivable to use one line. However, in this case, current concentrates on one thin linear portion, and an equivalent series inductance (ESL) increases. The ESL is connected in series with the capacitance C in the equivalent circuit of the multilayer capacitor (see FIG. 4), and acts to prevent rapid charge / discharge of the capacitor. Will be suppressed. However, as described above, when a plurality of openings are provided in the first and second internal electrodes so as to have a mesh shape (mesh shape), current flows in the first and second internal electrodes in a distributed manner. As a result, the ESL can be reduced. As a result, as indicated by a one-dot chain line c1 in FIG. 3, the impedance can be reduced over the entire high frequency band. In addition, since the plurality of openings are respectively provided in the first and second terminal side regions, the facing area between the first internal electrode and its different polarity when viewed from the stacking direction of the plurality of dielectric layers. , And the facing area between the second internal electrode and its different polarity when viewed from the stacking direction of the plurality of dielectric layers is small. Therefore, the first and second internal electrodes are not easily affected by magnetic fluxes from different poles, and the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. As a result, as indicated by a solid line a in FIG. 3, it is possible to suppress a decrease in impedance in the vicinity of the resonance frequency, and impedance fluctuation is suppressed over a wide band including the vicinity of the resonance frequency.

  ADVANTAGE OF THE INVENTION According to this invention, the multilayer capacitor which can suppress the fall of the impedance in the vicinity of the resonant frequency can be provided.

  A preferred embodiment of a multilayer capacitor 1 according to the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

  A configuration of the multilayer capacitor 1 according to the present embodiment will be described with reference to FIGS. 1 and 2. The multilayer capacitor 1 includes a rectangular parallelepiped dielectric body (element body) 10, internal electrodes 12A (second internal electrodes), 12B (first internal electrodes), and 14A (fourth internal electrodes, eighth electrodes). Internal electrode), 14B (fifth internal electrode, seventh internal electrode), 16A (sixth internal electrode), 16B (third internal electrode), and terminal electrode 18A (first terminal electrode), 18B (Second terminal electrode) and connecting electrodes 20A (first connecting electrodes) and 20B (second connecting electrodes).

  Dielectric body 10 has main surfaces 10a and 10b facing each other, side surfaces 10c and 10d facing each other, and side surfaces 10e and 10f facing each other. In the present embodiment, the main surface 10a or the main surface 10b is a mounting surface that faces the main surface of a circuit board (not shown).

  The side surfaces 10c and 10d extend so as to connect the main surfaces 10a and 10b and the side surfaces 10e and 10f. The side surfaces 10e and 10f extend so as to connect the main surfaces 10a and 10b and the side surfaces 10c and 10d. In the present embodiment, the length of the dielectric body 10 in the longitudinal direction can be set, for example, to about 1.0 mm, the width, for example, about 0.5 mm, and the thickness, for example, about 0.5 mm. Since dielectric body 10 is usually barrel-polished after firing, the ridge portion of dielectric body 10 has a curved surface shape having a predetermined curvature (not shown).

  As shown in FIG. 2, the dielectric body 10 is configured by laminating rectangular dielectric layers A <b> 10 to A <b> 18 in this order. That is, the upper surface of the dielectric layer A10 constitutes the main surface 10a of the dielectric element body 10, and the lower surface of the dielectric layer A18 constitutes the main surface 10b of the dielectric element body 10, and the main surfaces 10a, 10b The facing direction (hereinafter referred to as the facing direction) corresponds to the stacking direction (hereinafter referred to as the stacking direction) of the dielectric body 10 (dielectric layers A10 to A18) in the present embodiment.

  The dielectric layers A10 to A18 function as an insulator having electrical insulation. The dielectric layers A10 to A18 can be formed of, for example, a dielectric ceramic material obtained by adding a rare earth element to barium titanate or strontium titanate. The actual dielectric body 10 is integrated by firing so that the boundaries between the dielectric layers A10 to A18 cannot be visually recognized.

  On the respective surfaces of the dielectric layers A11 and A17, rectangular internal electrodes 12A and 14B are formed in a state of being separated from each other. The internal electrode 12A is disposed in a region near the side surface 10c of the dielectric layers A11 and A17 (in this embodiment, a region closer to the side surface 10c than the center in the longitudinal direction of the dielectric layers A11 and A17). The internal electrode 14B is disposed in a region near the side surface 10d of the dielectric layers A11 and A17 (in this embodiment, a region closer to the side surface 10d than the center in the longitudinal direction of the dielectric layers A11 and A17).

  The internal electrode 12A is integrally provided with a terminal connection portion 22A (second terminal connection portion) on the short side on the side surface 10c side. The terminal connection portion 22A has the same width as the internal electrode 12A and is drawn out to the edge of the dielectric layers A11 and A17 on the side where the terminal electrode 18A is formed, and its end portion is exposed to the side surface 10c. The internal electrode 12A is integrally provided with a connecting portion 24A (second connecting portion) at the corner on the side surface 10d side and the side surface 10e side. The connecting portion 24A is drawn out to the edge of the dielectric layers A11 and A17 on the side where the connecting electrode 20A is formed with a sufficiently small width with respect to the internal electrode 12A, and its end is exposed to the side surface 10e. .

  The internal electrode 14B is integrally provided with a connecting portion 26B (fifth connecting portion) at the corner on the side surface 10c side and the side surface 10f side. The connecting portion 26B is drawn out to the edge of the dielectric layers A11 and A17 on the side where the connecting electrode 20B is formed with a sufficiently small width with respect to the internal electrode 14B, and the end portion is exposed to the side surface 10f. .

  On the surfaces of the dielectric layers A12 and A18, rectangular internal electrodes 12B and 14A are formed in a state of being separated from each other. The internal electrode 12B is disposed in a region near the side surface 10d of the dielectric layers A12 and A18 (in this embodiment, a region closer to the side surface 10d than the center in the longitudinal direction of the dielectric layers A11 and A17), The internal electrode 14A is disposed in a region closer to the side surface 10c of the dielectric layers A12 and A18 (in this embodiment, a region closer to the side surface 10c than the center in the longitudinal direction of the dielectric layers A12 and A18).

  The internal electrode 12B is integrally provided with a terminal connection portion 22B (first terminal connection portion) on the short side on the side surface 10d side. The terminal connection portion 22B has the same width as the internal electrode 12B, and is drawn out to the edge of the dielectric layers A12 and A18 on the side where the terminal electrode 18B is formed, and the end portion is exposed to the side surface 10d. The internal electrode 12B is integrally provided with a connecting portion 24B (first connecting portion) at the corner on the side surface 10c side and the side surface 10f side. The connecting portion 24B is drawn to the edge of the dielectric layers A12 and A18 on the side where the connecting electrode 20B is formed with a sufficiently small width with respect to the internal electrode 12B, and the end portion is exposed to the side surface 10f. .

  The internal electrode 14A is integrally provided with a connecting portion 26A (fourth connecting portion) on the side surface 10d side and on the corner portion on the side surface 10e side. The connecting portion 26A is drawn out to the edge of the dielectric layers A12 and A18 on the side where the connecting electrode 20A is formed with a sufficiently small width with respect to the internal electrode 14A, and its end is exposed to the side surface 10e. .

  A rectangular internal electrode 16B is formed on each surface of the dielectric layers A13 and A15. The internal electrode 16B extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 16B is integrally provided with a connecting portion 28B (third connecting portion) for connection at the center of the long side on the side surface 10f side. The connection portion 28B is drawn to the edge of the dielectric layers A13 and A15 on the side where the connection electrode 20B is formed with a sufficiently small width with respect to the internal electrode 16B, and the end portion is exposed to the side surface 10f. .

  A rectangular internal electrode 16A is formed on each surface of the dielectric layers A14 and A16. The internal electrode 16A extends in the opposing direction of the side surfaces 10c and 10d. The internal electrode 16A is integrally provided with a connecting portion 28A (sixth connecting portion) at the center of the long side on the side surface 10e side. The connection portion 28A is drawn out to the edge of the dielectric layers A14 and A16 on the side where the connection electrode 20A is formed with a sufficiently small width with respect to the internal electrode 16A, and the end portion is exposed to the side surface 10e. .

  The internal electrodes 12A, 12B, 14A, 14B, 16A, and 16B are all disposed inside the dielectric body 10, and the internal electrodes 12A and 14B and the internal electrodes 12B and 14A are disposed via the dielectric layers A11 to A17. The internal electrode 16B, the internal electrode 16A, the internal electrode 16B, the internal electrode 16A, the internal electrodes 12A and 14B, and the internal electrodes 12B and 14A are stacked in this order. That is, the internal electrodes 12A, 12B, 14A, 14B, 16A, and 16B are separated from each other by the thickness of the dielectric layers A11 to A18 in the adjacent stacking direction (opposite direction of the main surfaces 10a and 10b). In this state, it is disposed inside the dielectric body 10.

  The internal electrodes 12A, 14A, 16A, and 16B all overlap each other when viewed from the stacking direction. More specifically, the internal electrode 12A, the internal electrode 14A, the region of the internal electrode 16A that is closer to the side surface 10c than the center in the longitudinal direction of the dielectric layer, and the center of the internal electrode 16B in the longitudinal direction of the dielectric layer. Also, the region on the side surface 10c side overlaps each other when viewed from the stacking direction.

  The internal electrodes 12B, 14B, 16A, and 16B all overlap each other when viewed from the stacking direction. More specifically, the internal electrode 12B, the internal electrode 14B, the region of the internal electrode 16A closer to the side surface 10d than the center in the longitudinal direction of the dielectric layer, and the center of the internal electrode 16B in the longitudinal direction of the dielectric layer. Also, the region on the side surface 10d side overlaps each other when viewed from the stacking direction.

  On the other hand, the internal electrode 12A and the internal electrode 12B do not overlap each other when viewed from the stacking direction. Further, the internal electrode 14A and the internal electrode 14B do not overlap each other when viewed from the stacking direction.

  Therefore, the facing area of the internal electrodes 16A and 16B when viewed from the stacking direction, the distance between the internal electrodes 16A and 16B (that is, the thickness of the dielectric layers A13 to A15), and the internal electrode 14A when viewed from the stacking direction. And the interval between the internal electrodes 14A and 16B (that is, the thickness of the dielectric layer A12), the opposing area between the internal electrode 14B and the internal electrode 16A when viewed from the stacking direction, and the internal electrode The capacitance of the multilayer capacitor 1 is defined by the distance between 14B and 16A (that is, the thickness of the dielectric layer A16).

  The internal electrodes 12A, 12B, 14A, 14B, 16A, and 16B are made of a conductive material such as Ag or Ni. The internal electrodes 12A, 12B, 14A, 14B, 16A, and 16B are configured as a sintered body of a conductive paste containing the conductive material.

  The terminal electrode 18A covers the side surface 10c of the dielectric element body 10 and is formed so as to go around the main surfaces 10a and 10b and the side surfaces 10e and 10f adjacent to the side surface 10c. That is, the terminal electrode 18A is disposed on the side surface 10c and the main surfaces 10a and 10b and the side surfaces 10e and 10f near the side surface 10c. The terminal electrode 18A is physically and electrically connected to the terminal connection portion 22A whose end is exposed on the side surface 10c. Thereby, the terminal electrode 18A and the internal electrode 12A are electrically connected.

  The terminal electrode 18B covers the side surface 10d of the dielectric element body 10 and is formed to wrap around the main surfaces 10a, 10b and the side surfaces 10e, 10f adjacent to the side surface 10d. In other words, the terminal electrode 18B is arranged on the side surface 10d and the main surfaces 10a and 10b and the side surfaces 10e and 10f near the side surface 10d. The terminal electrode 18B is physically and electrically connected to the terminal connection portion 22B whose end is exposed on the side surface 10d. Thereby, the terminal electrode 18B and the internal electrode 12B are electrically connected.

  The connecting electrode 20A has a rectangular shape and is formed so as to cover the side surface 10e of the dielectric element body 10 and wrap around the main surfaces 10a and 10b adjacent to the side surface 10e. That is, the connecting electrode 20A is disposed on the side surface 10e and the portion of the main surfaces 10a and 10b near the side surface 10e. The connecting electrode 20A is physically and electrically connected to the connecting portions 24A, 26A, and 28A whose ends are exposed on the side surface 10e. Thereby, the internal electrode 12A, the internal electrode 14A, and the internal electrode 16A are electrically connected to each other through the connection electrode 20A. That is, the internal electrode 12A, the internal electrode 14A, and the internal electrode 16A have the same polarity.

  The connecting electrode 20B has a rectangular shape and is formed so as to cover the side surface 10f of the dielectric body 10 and to wrap around the main surfaces 10a and 10b adjacent to the side surface 10f. That is, the connecting electrode 20B is disposed on the side surface 10f and the main surface 10a, 10b near the side surface 10f. The connection electrode 20B is physically and electrically connected to the connection portions 24B, 26B, and 28B whose ends are exposed on the side surface 10f. Thereby, the internal electrode 12B, the internal electrode 14B, and the internal electrode 16B are electrically connected to each other through the connection electrode 20B. That is, the internal electrode 12B, the internal electrode 14B, and the internal electrode 16B have the same polarity.

  The terminal electrodes 18A and 18B and the connecting electrodes 20A and 20B are formed by applying and baking a conductive paste containing conductive metal powder and glass frit, for example, on the outer surface of the dielectric body 10. If necessary, a plating layer may be formed on the baked terminal electrodes 18A and 18B and the coupling electrodes 20A and 20B.

  In the present embodiment as described above, the internal electrode 12A is integrally provided with the terminal connection portion 22A connected to the terminal electrode 18A and the connection portion 24A connected to the connection electrode 20A. 16A is integrally provided with a connecting portion 28A for connecting to the connecting electrode 20A, and the internal electrode 12A and the internal electrode 16A having the same polarity are adjacent to each other via the dielectric layer A16. And overlap each other when viewed from the stacking direction of the plurality of dielectric layers. Therefore, the internal electrode 12A in which the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 when the current flows is different from the internal electrode 16A on the dielectric layer A16 on the side adjacent to the internal electrode 16A (on the dielectric layer A15). In this case, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. The internal electrode 12B is integrally provided with a terminal connection portion 22B connected to the terminal electrode 18B and a connection connection portion 24B connected to the connection electrode 20B, and the internal electrode 16B is connected to the connection electrode 20B. The connecting connection portion 28B to be connected is integrally provided, and the internal electrode 12B and the internal electrode 16B having the same polarity are adjacent to each other via the dielectric layer A12, and a plurality of dielectric layers As seen from the stacking direction, the two layers overlap each other. Therefore, the internal electrode 12B that generates the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 when a current flows is on the side adjacent to the internal electrode 16A on the dielectric layer A16 (on the dielectric layer A14). In this case, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. Further, the connection electrode 26A connected to the connection electrode 20A is integrally provided on the internal electrode 14A, and the internal electrode 12A and the internal electrode 14A having the same polarity are connected to each other via the dielectric layer A17. Are adjacent to each other and overlap each other when viewed from the stacking direction of the plurality of dielectric layers. Therefore, the internal electrode 12A in which the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 when a current flows is adjacent to the opposite electrode on the side adjacent to the internal electrode 14A on the dielectric layer A18. As a result, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. In addition, the connection electrode 26B connected to the connection electrode 20B is integrally provided on the internal electrode 14B, and the internal electrode 12B and the internal electrode 14B having the same polarity are connected to each other via the dielectric layer A11. Are adjacent to each other and overlap each other when viewed from the stacking direction of the plurality of dielectric layers. Therefore, the internal electrode 12B that generates the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 when a current flows is adjacent to the opposite electrode on the side adjacent to the internal electrode 14B on the dielectric layer A11. As a result, the parasitic capacitance Cp (see FIG. 4) connected in parallel to the resistance component of the multilayer capacitor is reduced. As a result, as shown by a solid line in FIG. 3, it is possible to suppress a decrease in impedance in the vicinity of the resonance frequency, and to suppress a variation in impedance over a wide band including the vicinity of the resonance frequency.

  In the present embodiment, the internal electrode 12A is integrally provided with a terminal connection portion 22A connected to the terminal electrode 18A and a connection portion 24A connected to the connection electrode 20A. The connecting connection portion 26B connected to the connecting electrode 20B is integrally provided, and the internal electrodes 12A and 14B are disposed on the dielectric layers A11 and A17, respectively. The internal electrode 12B is integrally provided with a terminal connection portion 22B connected to the terminal electrode 18B and a connection connection portion 24B connected to the connection electrode 20B, and the internal electrode 14A is connected to the connection electrode 20A. The connecting connection portion 26A to be connected is integrally provided, and the internal electrodes 12B and 14A are disposed on the dielectric layers A12 and A18, respectively. Therefore, the internal electrode 12A and the internal electrode 14B having different polarities are both arranged on the same dielectric layer, and the internal electrode 12B and the internal electrode 14A having different polarities are both arranged on the same dielectric layer. Will be. As a result, since the number of dielectric layers constituting the element body is reduced, the multilayer capacitor 1 can be miniaturized.

  In the present embodiment, the connecting electrode 26A connected to the connecting electrode 20A is integrally provided on the internal electrode 14A, and the connecting electrode connected to the connecting electrode 20B is connected to the internal electrode 16B. 28B is integrally provided, and the internal electrode 14A and the internal electrode 16B having different polarities overlap each other when viewed from the stacking direction of the plurality of dielectric layers. The internal electrode 14B is integrally provided with a connection portion 26B for connection to the connection electrode 20B, and the internal electrode 16A is integrally provided with a connection portion 28A for connection to the connection electrode 20A. The internal electrodes 14B and the internal electrodes 16A having different polarities overlap each other when viewed from the stacking direction of the plurality of dielectric layers. Therefore, when the current flows, the resistance component ESR (see FIG. 4) of the multilayer capacitor 1 does not occur, and the capacitance component C (see FIG. 4) of the multilayer capacitor 1 occurs between the internal electrode 14A and the internal electrode 16B. A capacitance component C (see FIG. 4) of the multilayer capacitor 1 is generated between the electrode 14B and the internal electrode 16A. As a result, as described above, the internal electrode 14A and the internal electrode 16B having different polarities are arranged on the same dielectric layer A12, and the internal electrode 14B and the internal electrode 16A having different polarities are arranged. Together with the fact that both are disposed on the same dielectric layer A17, it is possible to increase the overall capacitance of the multilayer capacitor 1 while reducing the size of the multilayer capacitor 1. As a result, as indicated by a two-dot chain line c2 in FIG. 3, the impedance can be lowered over the entire low frequency band.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in this embodiment, two sets of internal electrodes 12A and 14B positioned on the same dielectric layer and two internal electrodes 12B and 14A positioned on the same dielectric layer are arranged inside the dielectric body 10. However, as shown in FIGS. 5 and 6, a set of internal electrodes 12A and 12B may be disposed inside the dielectric body 10, and three or more sets of internal electrodes 12A, 12B, 12B may be arranged (not shown).

  Further, as shown in FIG. 6, the internal electrodes 16A and 16B may be disposed between the pair of internal electrodes 12A and 14B and the internal electrodes 12B and 14A.

  In FIG. 5, the dielectric body 10 is configured by laminating dielectric layers A10 to A16 in this order, and the internal electrodes 12A, 12B, 14A, 14B, 16A, and 16B are formed of dielectric bodies. In the body 10, the internal electrodes 12A and 14B, the internal electrodes 12B and 14A, the internal electrode 16B, the internal electrode 16A, the internal electrode 16B, and the internal electrode 16A are stacked in this order via the dielectric layers A11 to A15. In FIG. 6, the dielectric body 10 is configured by laminating dielectric layers A10, A11, A14, A13, A16, A15, A12 in this order, and the internal electrodes 12A, 12B, 14A, 14B, 16A, 16B are internal electrodes 12A, 14B, internal electrodes 16A, internal electrodes 16B, internal electrodes 16A, internals through dielectric layers A11, A14, A13, A16, A15 inside the dielectric body 10. The electrode 16B and the internal electrodes 12B and 14A are stacked in this order.

  When the linear distance from the main surface 10a to the internal electrode 12A is different from the linear distance from the main surface 10b to the internal electrode 12B, the multilayer capacitor 1 is mounted on the circuit board using the main surface 10a as a mounting surface. The path through which the current flows is different between the case where the multilayer capacitor 1 is mounted on the circuit board with the main surface 10b as the mounting surface, and the high frequency characteristics may change depending on the mounting state of the multilayer capacitor 1 on the circuit board. It can happen. However, as shown in FIG. 6, if the linear distance from the main surface 10a to the internal electrode 12A and the linear distance from the main surface 10b to the internal electrode 12B are substantially the same, that is, the dielectric layer A10 It is preferable that the thickness and the thickness of the dielectric layer A12 are substantially equal because there is almost no possibility that the high-frequency characteristics are changed. Since the multilayer capacitor is an industrial product and an error occurs within a certain range, the “substantially the same” here includes the identity within the error range of the industrial product.

  For example, as shown in FIG. 7, the internal electrodes 12A, 12B, 14A, and 14B can be changed to various shapes.

  In FIG. 7, the internal electrode 12A has a rectangular shape, is a region closer to the side surface 10c than the center in the longitudinal direction of the dielectric layers A11 and A17, and from the center in the short direction of the dielectrics A11 and A17. Are also arranged in the region on the side surface 10e side. The internal electrode 12B has a rectangular shape, is a region closer to the side surface 10d than the center in the longitudinal direction of the dielectric layers A12, A18, and a region closer to the side surface 10f than the center in the short direction of the dielectrics A12, A18. Respectively. The internal electrode 14A has an L shape, and is a region closer to the side surface 10c than the center in the longitudinal direction of the dielectric layers A12 and A18 and a region closer to the side surface 10e than the center in the short direction of the dielectrics A12 and A18. Are arranged respectively. The internal electrode 14B has an L shape and is a region closer to the side surface 10d than the center in the longitudinal direction of the dielectric layers A11 and A17 and a region closer to the side surface 10f than the center in the short direction of the dielectrics A11 and A17. Are arranged respectively.

  A portion of the internal electrode 14A located in the region on the side surface 10d side from the center in the longitudinal direction of the dielectric layers A12, A18 and in the region on the side surface 10e side from the center in the short direction of the dielectric layers A12, A18; What is the portion of the internal electrode 14B located in the region on the side surface 10d side from the center in the longitudinal direction of the dielectric layers A11, A17 and in the region on the side surface 10e side from the center in the short direction of the dielectric layers A11, A17? They overlap each other when viewed from the stacking direction. A portion of the internal electrode 14A located in the region on the side surface 10c side from the center in the longitudinal direction of the dielectric layers A12, A18 and in the region on the side surface 10f side from the center in the short direction of the dielectric layers A12, A18; What is the portion of the internal electrode 14B located in the region on the side surface 10c side from the center in the longitudinal direction of the dielectric layers A11 and A17 and in the region on the side surface 10f side from the center in the short direction of the dielectric layers A11 and A17? They overlap each other when viewed from the stacking direction. Therefore, when the internal electrodes 12A, 12B, 14A, and 14B have the shape shown in FIG. 7, a capacitance component of the multilayer capacitor 1 is generated between the internal electrode 14A and the internal electrode 14B. As a result, the overall capacitance of the multilayer capacitor 1 can be further increased.

  Further, as shown in FIG. 8, the internal electrode 12A may be provided with a plurality of square openings 30A, and the internal electrode 12B may be provided with a plurality of square openings 30B. The openings 30A and 30B are arranged so as to be 4 rows × 4 columns in the internal electrodes 12A and 12B, that is, in a mesh shape (mesh shape). The openings 30A and 30B may have various shapes such as a polygonal shape (triangular shape, quadrangular shape, etc.), a circular shape, an elliptical shape, and a long hole shape.

  Further, the number of internal electrodes 16A and 16B and the number of dielectric layers may be appropriately set as desired.

FIG. 1 is a perspective view showing the multilayer capacitor in accordance with this embodiment. FIG. 2 is an exploded perspective view showing a dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 3 is a diagram illustrating impedance characteristics of the multilayer capacitor according to the present embodiment and the conventional multilayer capacitor. FIG. 4 is a diagram showing an equivalent circuit of the multilayer capacitor. FIG. 5 is an exploded perspective view showing another example (first example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 6 is an exploded perspective view showing another example (second example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 7 is an exploded perspective view showing another example (third example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 8 is an exploded perspective view showing another example (fourth example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 10 ... Dielectric body (element body), 12A ... Internal electrode (2nd internal electrode), 12B ... Internal electrode (1st internal electrode), 14A ... Internal electrode (4th internal electrode) , Eighth internal electrode), 14B ... internal electrode (fifth internal electrode, seventh internal electrode), 16A ... internal electrode (sixth internal electrode), 16B ... internal electrode (third internal electrode), 18A ... Terminal electrode (first terminal electrode), 18B ... Terminal electrode (second terminal electrode), 20A ... Connection electrode (first connection electrode), 20B ... Connection electrode (second connection electrode) ), 22A... Terminal connection (second terminal connection), 22B... Terminal connection (first terminal connection), 24A... Connection (second connection). 24B ... connection for connection (first connection for connection), 26A ... connection for connection (fourth connection for connection), 6B: Connection for connection (fifth connection for connection), 28A: Connection for connection (sixth connection for connection), 28B ... Connection for connection (third connection for connection), 30A, 30B ... Opening.

Claims (13)

  1. An element body in which a plurality of dielectric layers having at least first to third dielectric layers are stacked;
    First and second terminal electrodes disposed on the outer surface of the element body;
    First and second connection electrodes disposed on the outer surface of the element body;
    Comprising first to fourth internal electrodes disposed inside the element body;
    The first and fourth internal electrodes are disposed on the first dielectric layer in a state of being separated from each other,
    The second internal electrode is disposed on the second dielectric layer;
    The third internal electrode is disposed on the third dielectric layer;
    The first internal electrode is integrally formed with a first terminal connection portion connected to the first terminal electrode and a first connection connection portion connected to the first connection electrode. Provided in
    The second internal electrode is integrally formed with a second terminal connection portion connected to the second terminal electrode and a second connection connection portion connected to the second connection electrode. Provided in
    The third internal electrode is integrally provided with a third connection for connection that is connected to the first connection electrode,
    The fourth internal electrode is integrally provided with a fourth connecting connection portion connected to the second connecting electrode,
    Wherein the first and fourth inner electrode and the third internal electrodes, with which adjacent in the stacking direction of the plurality of dielectric layers, which overlap each other when viewed from the laminating direction,
    The multilayer capacitor, wherein the first internal electrode and the second internal electrode are adjacent to each other in the stacking direction and do not overlap each other when viewed from the stacking direction .
  2. A fifth internal electrode disposed inside the element body;
    The fifth internal electrode is integrally provided with a fifth connecting portion connected to the first connecting electrode,
    It said fifth internal electrodes are adjacent to the said first internal electrodes before miracle layer direction,
    Wherein the first internal electrode and the fifth internal electrodes before is characterized in that overlap each other when viewed from miracle layer direction, the multilayer capacitor of claim 1.
  3.   The multilayer capacitor according to claim 2, wherein the second internal electrode and the fifth internal electrode are disposed on the second dielectric layer in a state of being separated from each other.
  4. The first internal electrode has a first terminal side region closer to the first terminal connection portion than a portion where the first connection connection portion is provided,
    The second internal electrode has a second terminal side region closer to the second terminal connection portion than a portion where the second connecting connection portion is provided,
    Wherein the first and second terminal-side region, wherein a plurality of openings are provided, a multilayer capacitor according to any one of claims 1-3.
  5. The multilayer capacitor according to claim 4 , wherein the plurality of openings are arranged in a mesh shape.
  6.   Comprising sixth to ninth internal electrodes arranged inside the element body;
      The plurality of dielectric layers have fourth to sixth dielectric layers,
      The sixth and ninth internal electrodes are disposed on the fifth dielectric layer in a state of being separated from each other,
      The sixth internal electrode is disposed on the sixth dielectric layer;
      The eighth internal electrode is disposed on the fourth dielectric layer;
      The sixth internal electrode is integrally formed with a third terminal connecting portion connected to the second terminal electrode and a sixth connecting connecting portion connected to the second connecting electrode. Provided in
      The seventh internal electrode is integrally provided with a fourth terminal connection portion connected to the first terminal electrode and a seventh connection portion connected to the first connection electrode. Provided,
      The eighth internal electrode is integrally provided with an eighth connection portion connected to the second connection electrode,
      The ninth internal electrode is integrally provided with a ninth connection portion connected to the first connection electrode,
      The sixth and ninth internal electrodes and the eighth internal electrode are adjacent to each other in the stacking direction and overlap each other when viewed from the stacking direction,
      The sixth internal electrode and the seventh internal electrode are adjacent to each other in the stacking direction and do not overlap each other when viewed from the stacking direction. The multilayer capacitor described in one item.
  7.   A tenth internal electrode disposed inside the element body;
      The tenth internal electrode is integrally provided with a tenth connecting portion connected to the second connecting electrode,
      The tenth internal electrode is adjacent to the sixth internal electrode in the stacking direction;
      The multilayer capacitor according to claim 6, wherein the sixth internal electrode and the tenth internal electrode overlap each other when viewed from the multilayer direction.
  8.   The multilayer capacitor according to claim 7, wherein the seventh internal electrode and the tenth internal electrode are disposed on the sixth dielectric layer in a state of being separated from each other.
  9.   The sixth internal electrode has a third terminal side region closer to the second terminal connection portion than a portion where the second connection connection portion is provided,
      The seventh internal electrode has a fourth terminal side region closer to the first terminal connection portion than a portion where the first connection connection portion is provided,
      The multilayer capacitor according to claim 6, wherein a plurality of openings are provided in each of the third and fourth terminal side regions.
  10.   The multilayer capacitor according to claim 9, wherein the plurality of openings are arranged in a mesh shape.
  11.   An element body in which a plurality of dielectric layers having at least first to fourth dielectric layers are stacked;
      First and second terminal electrodes disposed on the outer surface of the element body;
      First and second connection electrodes disposed on the outer surface of the element body;
      Comprising first to sixth internal electrodes disposed inside the element body;
      The first to fourth dielectric layers are arranged in this order in the stacking direction of the plurality of dielectric layers,
      The first and fourth internal electrodes are disposed on the first dielectric layer in a state of being separated from each other,
      The second and sixth internal electrodes are disposed on the fourth dielectric layer in a state of being separated from each other,
      The third internal electrode is disposed on the second dielectric layer;
      The fifth internal electrode is disposed on the third dielectric layer;
      The first internal electrode is integrally formed with a first terminal connection portion connected to the first terminal electrode and a first connection connection portion connected to the first connection electrode. Provided in
      The second internal electrode is integrally formed with a second terminal connection portion connected to the second terminal electrode and a second connection connection portion connected to the second connection electrode. Provided in
      The third internal electrode is integrally provided with a third connection for connection that is connected to the first connection electrode,
      The fourth internal electrode is integrally provided with a fourth connecting connection portion connected to the second connecting electrode,
      The fifth internal electrode is integrally provided with a fifth connecting portion connected to the second connecting electrode,
      The sixth internal electrode is integrally provided with a sixth connection portion connected to the first connection electrode,
      The first and fourth internal electrodes and the third internal electrode are adjacent to each other in the stacking direction of the plurality of dielectric layers and overlap each other when viewed from the stacking direction.
      The second and sixth internal electrodes and the fifth internal electrode are adjacent to each other in the stacking direction of the plurality of dielectric layers, and overlap each other when viewed from the stacking direction,
      The multilayer capacitor, wherein the first internal electrode and the second internal electrode do not overlap each other when viewed from the stacking direction.
  12.   The first internal electrode has a first terminal side region closer to the first terminal connection portion than a portion where the first connection connection portion is provided,
      The second internal electrode has a second terminal side region closer to the second terminal connection portion than a portion where the second connecting connection portion is provided,
      The multilayer capacitor according to claim 11, wherein a plurality of openings are respectively provided in the first and second terminal side regions.
  13.   The multilayer capacitor according to claim 12, wherein the plurality of openings are arranged in a mesh shape.
JP2008264125A 2008-10-10 2008-10-10 Multilayer capacitor Active JP5077180B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008264125A JP5077180B2 (en) 2008-10-10 2008-10-10 Multilayer capacitor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008264125A JP5077180B2 (en) 2008-10-10 2008-10-10 Multilayer capacitor
US12/497,970 US8189321B2 (en) 2008-09-30 2009-07-06 Multilayer capacitor
KR1020090092162A KR20100036982A (en) 2008-09-30 2009-09-29 Multilayer condensor
US13/447,668 US8659873B2 (en) 2008-09-30 2012-04-16 Multilayer capacitor

Publications (2)

Publication Number Publication Date
JP2010093193A JP2010093193A (en) 2010-04-22
JP5077180B2 true JP5077180B2 (en) 2012-11-21

Family

ID=42255617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008264125A Active JP5077180B2 (en) 2008-10-10 2008-10-10 Multilayer capacitor

Country Status (1)

Country Link
JP (1) JP5077180B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6137047B2 (en) * 2014-05-09 2017-05-31 株式会社村田製作所 Multilayer capacitor and method of using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3727575B2 (en) * 2001-12-03 2005-12-14 Tdk株式会社 Multilayer capacitor
JP3907599B2 (en) * 2003-03-07 2007-04-18 Tdk株式会社 Multilayer capacitor
JP2007043093A (en) * 2005-07-05 2007-02-15 Taiyo Yuden Co Ltd Laminated capacitor
JP4293560B2 (en) * 2006-07-12 2009-07-08 Tdk株式会社 Multilayer capacitor array

Also Published As

Publication number Publication date
JP2010093193A (en) 2010-04-22

Similar Documents

Publication Publication Date Title
US9111682B2 (en) Multilayer ceramic electronic component
KR101525645B1 (en) Multilayer ceramic capacitor
KR101412784B1 (en) Multilayer ceramic capacitor
US8488296B2 (en) Multilayer capacitor
US7019958B2 (en) Multilayer capacitor
US6661640B2 (en) Multilayer ceramic electronic device
JP5420619B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
US20150014037A1 (en) Multilayer ceramic capacitor and board for mounting the same
KR101952860B1 (en) Multi-layered ceramic capacitor and board for mounting the same
US6922329B2 (en) Multilayer capacitor
US7310217B2 (en) Monolithic capacitor and mounting structure thereof
KR101401636B1 (en) Multilayer condenser
US7199996B2 (en) Laminated capacitor
US7411776B2 (en) Multilayer capacitor array
US20110102969A1 (en) Multilayer capacitor, mounting structure thereof, and method of manufacturing same
US9431174B2 (en) Multilayer capacitor
JP5275393B2 (en) Multilayer ceramic capacitor
JP5038634B2 (en) Noise filter and noise filter mounting structure
US20080100988A1 (en) Multilayer capacitor
US7667950B2 (en) Multilayer capacitor and electronic device
KR101971912B1 (en) Multi-Layered Ceramic Electronic Component and Manufacturing Method of the Same
US7251115B2 (en) Multilayer capacitor
JP2006186353A (en) Stacked capacitor and printed circuit board incorporated therewith
JP4450084B2 (en) Multilayer capacitor and multilayer capacitor mounting structure
KR20080072578A (en) Multilayer capacitor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110523

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120626

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120712

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120731

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120813

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150907

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150