JP5131263B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor.

  2. Description of the Related Art Conventionally, there is a multilayer capacitor including a multilayer body in which dielectric layers and internal electrodes are alternately stacked, and an external electrode and a terminal conductor that are electrically insulated from each other on the side surface of the multilayer body. For example, in the multilayer capacitor described in Patent Document 1 below, four types of internal electrodes are provided, of which two types of internal electrodes are an electrode portion that forms a capacitance, and this electrode portion and a terminal. And a lead conductor connected to the conductor. The other two types of internal electrodes have a lead conductor connected to the terminal conductor and a lead conductor connected to the external electrode.

JP 2003-168621 A

  Such a multilayer capacitor is used, for example, as a decoupling capacitor in an IC. In the current situation where the speed and voltage of ICs are increasing, it is required to improve the ESR (equivalent series resistance) in the multilayer capacitor. Therefore, it is conceivable to reduce the width of the lead conductor of a predetermined internal electrode to be smaller than the width of the lead conductor of another internal electrode, thereby forming a current path throttle portion to achieve high ESR.

  On the other hand, when the width of the lead conductor of a predetermined internal electrode is made smaller than the width of the lead conductor of another internal electrode as described above, the ESR of the multilayer capacitor can be increased, but the lead conductor and the terminal having a narrow width are provided. The contact area with the electrode will decrease. This contributes to poor conduction of the multilayer capacitor. Therefore, a technique for suppressing the occurrence of poor conduction while improving ESR is desired.

  Accordingly, an object of the present invention is to provide a multilayer capacitor capable of suppressing the occurrence of poor conduction while improving ESR.

  The multilayer capacitor in accordance with the present invention includes an element body in which a plurality of dielectric layers are laminated, first and second terminal electrodes disposed on the outer surface of the element body, and first elements disposed on the outer surface of the element body. The first and second connection electrodes and the first and second ESR control electrodes disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layers are spaced apart from each other and adjacent to each other in the stacking direction. The first and second internal electrodes disposed inside the element body and the first and second dummy electrodes disposed inside the element body, and the first ESR control electrode includes: The first terminal connecting conductor connected to the first terminal electrode and the first connecting connecting conductor connected to the first connecting electrode are integrally provided, and the second ESR control electrode is connected to the first ESR control electrode. Is connected to the second terminal connection conductor connected to the second terminal electrode and to the second connection electrode. A second connection connecting conductor is integrally provided, and the first internal electrode is integrally provided with a third connection connecting conductor connected to the second connection electrode. The internal connection electrode is integrally provided with a fourth connection connecting conductor connected to the first connection electrode, and the first and second dummy electrodes are connected to the first and second ESR control electrodes. Are arranged on different planes, and the first dummy electrode is connected to the first terminal electrode, and the second dummy electrode is connected to the second terminal electrode.

  In the multilayer capacitor according to the present invention, the first internal electrode is connected only to the first connection electrode, the second internal electrode is connected only to the second connection electrode, and the first ESR control electrode is connected to the first connection electrode. The first connection electrode and the first terminal electrode are connected to each other, and the second ESR control electrode is connected to the second connection electrode and the second terminal electrode, respectively. Accordingly, since the connecting electrode in which the internal electrodes are connected in parallel is connected in series to the terminal electrode, it is possible to achieve higher ESR than in the case where the internal electrode is connected in parallel to the terminal electrode as in the prior art. It becomes possible.

  In the multilayer capacitor according to the present invention, the first dummy electrode connected to the first terminal electrode and the second terminal electrode are connected to a different surface from the first and second ESR control electrodes. A second dummy electrode is disposed. Therefore, as compared with the case where only the first terminal connecting conductor is connected to the first terminal electrode and the second terminal connecting conductor is connected only to the second terminal electrode, the electrode is in contact with the terminal electrode. The contact area of the part increases. As a result, sufficient adhesion between the terminal electrode and the terminal connection conductor can be ensured, so that occurrence of poor conduction can be suppressed.

  By the way, if the dummy electrode is located on the same plane as the ESR control electrode, when printing blur or manufacturing error occurs when the dummy electrode is formed, the dummy electrode is connected to the terminal connection conductor, and the ESR is It may occur that the ESR control electrode is connected to a terminal electrode having a different polarity via a dummy electrode, and the function as a multilayer capacitor may be lost.

  However, in the multilayer capacitor according to the present invention, the first and second dummy electrodes are located on a different surface from the first and second ESR control electrodes. Therefore, even if printing bleeding or manufacturing errors occur when forming the dummy electrode, it is possible to prevent the dummy electrode and the terminal connection conductor from being connected, and it is possible to avoid the occurrence of a decrease in ESR. Become. In addition, when a dummy electrode is formed, printing bleeding, manufacturing errors, etc. occur, and even if the dummy electrode and the internal electrode are connected, the capacitance is only slightly reduced, so the entire multilayer capacitor The function of will not be lost.

  Furthermore, in the multilayer capacitor in accordance with the present invention, the first dummy electrode located on a different surface from the first and second ESR control electrodes is connected to the first terminal electrode, and the first and second ESR A second dummy electrode located on a different surface from the control electrode is connected to the second terminal electrode. For this reason, when only the internal electrodes are laminated, the generation of a step in the dielectric layer caused by the thickness of the internal electrodes can be suppressed by the dummy electrodes. That is, the dummy electrode functions as a step absorbing member for the dielectric layer. Therefore, it becomes possible to prevent the deformation of the element body.

  Preferably, the first dummy electrode is disposed on the same plane as the first internal electrode, and the second dummy electrode is disposed on the same plane as the second internal electrode, and the first dummy electrode and the first dummy electrode The terminal connection conductors do not overlap with each other when viewed from the stacking direction, and the second dummy electrode and the second terminal connection conductor do not overlap with each other when viewed from the stacking direction. If it does in this way, when the dielectric green sheet used as a dielectric material layer is laminated | stacked and crimped | bonded, dielectric green sheets will become easy to adhere | attach each other and generation | occurrence | production of an unnecessary level | step difference can be prevented.

  Preferably, the first ESR control electrode is disposed inside the element body adjacent to the first internal electrode in the stacking direction, and the second ESR control electrode is the second ESR control electrode in the stacking direction. The internal electrode is disposed inside the element body in a state adjacent to each other. In this way, it is possible to further prevent the occurrence of unnecessary steps.

  Preferably, the connection width between the first dummy electrode and the first terminal electrode is set to be equal to or greater than the width of the first terminal connection conductor, and the connection width between the second dummy electrode and the second terminal electrode is The width is set to be equal to or larger than the width of the second terminal connection conductor. Preferably, the connection width between the first dummy electrode and the first terminal electrode is set to be equal to or larger than the width of the third or fourth connection connecting conductor, and the second dummy electrode and the second terminal electrode are set. Is set to be equal to or larger than the width of the third or fourth connecting connecting conductor. If it does in this way, the contact area of the electrode part which touches a terminal electrode will become still larger. Therefore, the adhesiveness between the terminal electrode and the terminal connection conductor becomes more sufficient, and the occurrence of poor conduction can be more reliably suppressed.

  Preferably, the semiconductor device further includes third and fourth dummy electrodes arranged inside the element body, the third dummy electrode is connected to the first terminal electrode, and the fourth dummy electrode is the second terminal. The first and third dummy electrodes and the first terminal connection conductor are connected to the electrode and do not overlap each other when viewed from the stacking direction, and the second and fourth dummy electrodes and the second terminal connection The conductors do not overlap with each other when viewed from the stacking direction, and the first terminal connection conductor is located between the first dummy electrode and the third dummy electrode when viewed from the stacking direction, The second terminal connection conductor is located between the second dummy electrode and the fourth dummy electrode as viewed from the stacking direction. If it does in this way, when the dielectric green sheet used as a dielectric material layer is laminated | stacked and crimped | bonded, dielectric green sheets will become easy to adhere | attach each other and generation | occurrence | production of an unnecessary level | step difference can be prevented.

  More preferably, the separation width between the first dummy electrode and the third dummy electrode is set to be larger than the width of the first terminal connection conductor, and the second dummy electrode and the fourth dummy electrode are set. Is set to be larger than the width of the second terminal connection conductor. In this case, when the dielectric green sheets to be the dielectric layers are stacked and pressure-bonded, the first and third dummy electrodes and the first terminal connection conductor do not overlap each other when viewed from the stacking direction. As described above (when the dielectric green sheets are laminated) (so that the second and fourth dummy electrodes and the second terminal connection conductor do not overlap each other when viewed from the lamination direction) It is possible to prevent the occurrence of a step difference.

  More preferably, the first and third dummy electrodes are arranged on the same plane as the first internal electrode, and the second and fourth dummy electrodes are arranged on the same plane as the second internal electrode. The ESR control electrode is disposed inside the element body adjacent to the first internal electrode in the stacking direction, and the second ESR control electrode is adjacent to the second internal electrode in the stacking direction. Arranged inside the element body in a combined state. In this way, it is possible to further prevent the occurrence of unnecessary steps.

  More preferably, the sum of the connection width between the first dummy electrode and the first terminal electrode and the connection width between the third dummy electrode and the first terminal electrode is greater than or equal to the width of the first terminal connection conductor. The sum of the connection width between the second dummy electrode and the second terminal electrode and the connection width between the fourth dummy electrode and the second terminal electrode is set to be equal to or greater than the width of the second terminal connection conductor. Has been. More preferably, the total of the connection width between the first dummy electrode and the first terminal electrode and the connection width between the third dummy electrode and the first terminal electrode is the width of the first connection conductor. The sum of the connection width between the second dummy electrode and the second terminal electrode and the connection width between the fourth dummy electrode and the second terminal electrode is equal to or greater than the width of the second connection conductor. Is set to If it does in this way, the contact area of the electrode part which touches a terminal electrode will become still larger. Therefore, the adhesiveness between the terminal electrode and the terminal connection conductor becomes more sufficient, and the occurrence of poor conduction can be more reliably suppressed.

  More preferably, it further includes first and second sub dummy electrodes disposed inside the element body, and the first sub dummy electrode is spaced apart from the first internal electrode and the first dummy electrode, The second sub dummy electrode is disposed on the same plane as the second internal electrode in a state of being separated from the second internal electrode and the second dummy electrode, and is disposed on the same plane as the first internal dummy electrode. The electrode is connected to the first connection electrode, and the second sub-dummy electrode is connected to the second connection electrode. In this way, the first connection electrode is connected only with the first and fourth connection connection conductors, and the second connection electrode is connected only with the second and third connection connection conductors. Compared with the case where it carries out, the contact area of the electrode part which touches the electrode for connection becomes large. Therefore, sufficient adhesion between the connecting electrode and the connecting conductor can be ensured. Further, the generation of a step in the dielectric layer caused by the thickness of the internal electrode can be suppressed by the sub dummy electrode. That is, the sub dummy electrode also functions as a step absorbing member for the dielectric layer. Therefore, it becomes possible to prevent the deformation of the element body.

  According to the present invention, it is possible to provide a multilayer capacitor capable of suppressing the occurrence of poor conduction while improving ESR.

FIG. 1 is a perspective view showing the multilayer capacitor in accordance with this embodiment. FIG. 2 is an exploded perspective view showing a dielectric body constituting the multilayer capacitor in accordance with the present embodiment. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is a diagram showing the ESR control electrode that constitutes the multilayer capacitor in accordance with the present embodiment. FIG. 5 is a diagram showing internal electrodes constituting the multilayer capacitor according to the present embodiment. FIG. 6 is an exploded perspective view showing another example (first example) of the dielectric body constituting the multilayer capacitor in accordance with the present embodiment. FIG. 7 is a view showing another example (first example) of internal electrodes constituting the multilayer capacitor in accordance with this embodiment. FIG. 8 is a view showing another example (second example) of the internal electrodes constituting the multilayer capacitor in accordance with this embodiment. FIG. 9 is a view showing another example (third example) of the internal electrodes constituting the multilayer capacitor in accordance with this embodiment.

  A preferred embodiment of a multilayer capacitor 1 according to the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

  With reference to FIGS. 1-5, the structure of the multilayer capacitor 1 which concerns on this embodiment is demonstrated. The multilayer capacitor 1 includes a rectangular parallelepiped dielectric body (element body) 10, ESR control electrodes 12A (first ESR control electrodes), 12B (second ESR control electrodes), and internal electrodes 14A (first electrodes). Internal electrodes), 14B (second internal electrodes), dummy electrodes 16A (first dummy electrodes), 16B (second dummy electrodes), terminal electrodes 18A (first terminal electrodes), 18B (second Terminal electrode), a connecting electrode 20A (first connecting electrode), and 20B (second connecting electrode).

  As shown in FIG. 1, the dielectric body 10 has side surfaces 10a and 10b facing each other, side surfaces 10c and 10d facing each other, and side surfaces 10e and 10f facing each other. The side surfaces 10c and 10d extend so as to connect the side surfaces 10a and 10b and the side surfaces 10e and 10f. The side surfaces 10e and 10f extend so as to connect the side surfaces 10a and 10b and the side surfaces 10c and 10d. In the present embodiment, the length of the dielectric body 10 in the longitudinal direction can be set to about 1.6 mm, the width can be set to about 0.8 mm, and the thickness can be set to about 0.8 mm, for example. Since the dielectric body 10 is usually barrel-polished after firing, the ridges of the dielectric body 10 have a curved surface shape having a predetermined curvature.

  In the present embodiment, the side surface 10 f is a mounting surface that faces the main surface of the circuit board 100. The circuit board 100 has an anode land pattern 102A and a cathode land pattern 102B. The anode land pattern 102A and the cathode land pattern 102B are formed, for example, in a strip shape along the width direction of the terminal electrode 18A and the terminal electrode 18B, and are connected to predetermined circuit wiring.

  The terminal electrode 18A is bonded to the anode land pattern 102A, and the terminal electrode 18B is bonded to the cathode land pattern 102B. The connecting electrode 20A and the connecting electrode 20B are not joined to either the anode land pattern 102A or the cathode land pattern 102B. That is, in the multilayer capacitor 1, only the terminal electrode 18 </ b> A and the terminal electrode 18 </ b> B are bonded to the circuit board 100.

  As shown in FIG. 2, the dielectric body 10 is configured by laminating rectangular dielectric layers A <b> 10 to A <b> 18 in this order. That is, the upper surface of the dielectric layer A10 constitutes the side surface 10e of the dielectric element body 10, and the lower surface of the dielectric layer A18 constitutes the main surface 10f of the dielectric element body 10, and the opposing direction of the side surfaces 10e and 10f (Hereinafter referred to as the facing direction) corresponds to the stacking direction (hereinafter referred to as the stacking direction) of the dielectric body 10 (dielectric layers A10 to A18) in the present embodiment.

  The dielectric layers A10 to A18 function as an insulator having electrical insulation. The dielectric layers A10 to A18 can be formed of, for example, a dielectric ceramic material obtained by adding a rare earth element to barium titanate or strontium titanate. The actual dielectric body 10 is integrated by firing so that the boundaries between the dielectric layers A10 to A18 cannot be visually recognized.

  As shown in FIGS. 2 and 4A, a rectangular ESR control electrode 12A is formed on the surface of the dielectric layer A11. The ESR control electrode 12A is located in a region near the side surface 10b in the dielectric layer A11. The ESR control electrode 12A is integrally provided with a terminal connection conductor 22A (first terminal connection conductor) at the side edge on the side surface 10a. The terminal connection conductor 22A is drawn out to the edge of the dielectric layer A11 on the side where the terminal electrode 18A is formed, and its end is exposed to the side surface 10a. The ESR control electrode 12A is integrally provided with a connecting conductor 24A (first connecting conductor) on the side edge on the side surface 10c. The connecting conductor for connection 24A is drawn out to the edge of the dielectric layer A11 on the side where the connecting electrode 20A is formed, and its end is exposed to the side surface 10c.

  As shown in FIGS. 2 and 4B, a rectangular ESR control electrode 12B is formed on the surface of the dielectric layer A18. The ESR control electrode 12B is located in a region near the side surface 10a in the dielectric layer A18. The ESR control electrode 12B is integrally provided with a terminal connection conductor 22B (second terminal connection conductor) on the side edge on the side surface 10b side. The terminal connection conductor 22B is drawn out to the edge of the dielectric layer A18 on the side where the terminal electrode 18B is formed, and its end is exposed to the side surface 10b. The ESR control electrode 12B is integrally provided with a connecting conductor 24B (second connecting conductor) on the side edge on the side surface 10d. The connecting conductor for connection 24B is drawn out to the edge of the dielectric layer A18 on the side where the connecting electrode 20B is formed, and its end is exposed to the side surface 10d.

  A rectangular internal electrode 14B is formed on the surface of each of the dielectric layers A12, A14, and A16, as shown in FIGS. The internal electrode 14B is located substantially at the center of the dielectric layers A12, A14, A16. The internal electrode 14B is integrally provided with a connecting connecting conductor 26B (fourth connecting connecting conductor) at the center of the side edge on the side surface 10d side. The connecting conductor for connection 26B is drawn out to the edge of the dielectric layers A12, A14, A16 on the side where the connecting electrode 20B is formed, and its end is exposed to the side surface 10d.

  As shown in FIGS. 2 and 5B, rectangular internal electrodes 14A are formed on the surfaces of the dielectric layers A13, A15, and A17. The internal electrode 14A is located substantially at the center of the dielectric layers A13, A15, A17. The internal electrode 14A is integrally provided with a connecting connecting conductor 26A (third connecting connecting conductor) at the center of the side edge on the side surface 10c side. The connecting conductor for connection 26A is drawn out to the edge of the dielectric layers A13, A15, A17 on the side where the connecting electrode 20A is formed, and its end is exposed to the side surface 10c.

  Rectangular dummy electrodes 16A and 16B are formed on the respective surfaces of the dielectric layers A12 to A17. The dummy electrode 16A is located on the side surface 10a side, and the dummy electrode 16B is located on the side surface 10b side. The dummy electrode 16A is drawn out to the edge of the dielectric layers AA12 to A17 on the side where the terminal electrode 18A is formed, and its end is exposed to the side surface 10a. The dummy electrode 16B is drawn out to the edge of the dielectric layers A12 to A17 on the side where the terminal electrode 18B is formed, and its end is exposed to the side surface 10b.

  As shown in FIG. 2, the ESR control electrodes 12A and 12B and the internal electrodes 14A and 14B are disposed inside the dielectric body 10, and are stacked via dielectric layers A11 to A17. That is, the ESR control electrodes 12A and 12B and the internal electrodes 14A and 14B that are adjacent in the stacking direction are arranged inside the dielectric element body 10 while being separated from each other by the thickness of the dielectric layers A11 to A17. .

  The ESR control electrode 12A and the internal electrodes 14A and 14B overlap each other when viewed from the stacking direction. More specifically, the ESR control electrode 12A and the region on the side surface 10b side from the center in the longitudinal direction of the dielectric layer (hereinafter referred to as “longitudinal direction”) of the internal electrodes 14A and 14B are both from the stacking direction. They overlap each other.

  The ESR control electrode 12B and the internal electrodes 14A and 14B overlap each other when viewed from the stacking direction. More specifically, the ESR control electrode 12B and the region of the internal electrodes 14A and 14B that are closer to the side surface 10a than the center in the longitudinal direction overlap each other when viewed from the stacking direction.

  The internal electrodes 14A and 14B are overlapped with each other as viewed from the stacking direction. Accordingly, the facing area of the internal electrodes 14A and 14B when viewed from the stacking direction and the interval between the adjacent internal electrodes 14A and 14B in the stacking direction (that is, the thickness of the dielectric layers A12 to A16) are Mainly contributes to capacitance.

  The ESR control electrodes 12A and 12B, the internal electrodes 14A and 14B, and the dummy electrodes 16A and 16B are made of a conductive material such as Ag or Ni, for example. The ESR control electrodes 12A and 12B, the internal electrodes 14A and 14B, and the dummy electrodes 16A and 16B are configured as a sintered body of a conductive paste containing the conductive material.

  As shown in FIGS. 1 and 3, the terminal electrode 18A is formed so as to cover the side surface 10a of the dielectric element body 10 and wrap around the side surfaces 10c, 10d, 10e, and 10f adjacent to the side surface 10a. That is, the terminal electrode 18A is disposed on the side surface 10a and the portion of the side surfaces 10c, 10d, 10e, and 10f that is closer to the side surface 10a. The terminal electrode 18A is physically and electrically connected to the dummy electrode 16A and the terminal connection conductor 22A whose end portions are exposed on the side surface 10a. As a result, the terminal electrode 18A and the ESR control electrode 12A are electrically connected.

  The terminal electrode 18B covers the side surface 10b of the dielectric element body 10 and is formed so as to wrap around the side surfaces 10c, 10d, 10e, and 10f adjacent to the side surface 10b. That is, the terminal electrode 18B is disposed on the side surface 10b and the portion of the side surfaces 10c, 10d, 10e, and 10f that is closer to the side surface 10b. The terminal electrode 18B is physically and electrically connected to the dummy electrode 16B and the terminal connection conductor 22B whose ends are exposed on the side surface 10b. As a result, the terminal electrode 18B and the ESR control electrode 12B are electrically connected.

  The connecting electrode 20A has a rectangular shape, and is formed so as to cover the side surface 10c of the dielectric body 10 and wrap around the side surfaces 10e and 10f adjacent to the side surface 10c. That is, the connecting electrode 20A is disposed on the side surface 10c and the portion of the side surfaces 10e and 10f near the side surface 10c. The connecting electrode 20A is physically and electrically connected to the connecting connecting conductors 24A and 26A whose ends are exposed on the side surface 10c. As a result, the ESR control electrode 12A and the internal electrode 14A are electrically connected to each other via the connection electrode 20A. That is, the ESR control electrode 12A and the internal electrode 14A have the same polarity.

  The connection electrode 20B has a rectangular shape, and is formed so as to cover the side surface 10d of the dielectric body 10 and wrap around the side surfaces 10e and 10f adjacent to the side surface 10d. That is, the connecting electrode 20B is disposed on the side surface 10d and the portion of the side surfaces 10e and 10f near the side surface 10d. The connection electrode 20B is physically and electrically connected to the connection conductors 24B and 26B whose ends are exposed on the side surface 10d. Thereby, the ESR control electrode 12B and the internal electrode 14B are electrically connected to each other via the connection electrode 20B. That is, the ESR control electrode 12B and the internal electrode 14B have the same polarity.

  The terminal electrodes 18A and 18B and the connecting electrodes 20A and 20B are formed by applying and baking a conductive paste containing conductive metal powder and glass frit, for example, on the outer surface of the dielectric body 10. If necessary, a plating layer may be formed on the baked terminal electrodes 18A and 18B and the coupling electrodes 20A and 20B.

  Here, the ESR control electrodes 12A and 12B and the dummy electrodes 16A and 16B will be described in more detail with reference to FIGS.

  As shown in FIG. 4, in this embodiment, the width W1 of the terminal connection conductors 22A and 22B in the short direction of the dielectric layer (hereinafter referred to as “short direction”) is the ESR control in the short direction. The width is set smaller than the width Wa of the electrodes 12A and 12B. Specifically, the width W1 is set to about 0.1 to 0.9 times the width Wa.

  As shown in FIG. 5, in the present embodiment, the width W2 of the connecting connecting conductors 26A and 26B in the longitudinal direction is set smaller than the width Wb of the internal electrodes 14A and 14B in the longitudinal direction. Specifically, the width W2 is set to about 0.5 times or less of the width Wb.

  In the present embodiment, the width W3 of the dummy electrodes 16A and 16B in the short direction is equal to or greater than the width W1 or the width W2 (in FIG. 5, approximately the same as the width Wa of the internal electrodes 14A and 14B in the short direction) Is set). Specifically, the width W3 is set to about 1 to 8 times the width W1 or the width W2.

  In the present embodiment as described above, the internal electrode 14A is connected only to the connecting electrode 20A, the internal electrode 14B is connected only to the connecting electrode 20B, and the ESR control electrode 12A is connected to the connecting electrode 20A and the terminal electrode 18A. The ESR control electrodes 12B are connected to the connection electrode 20B and the terminal electrode 18A, respectively. Therefore, since the connecting electrodes 20A and 20B, in which the internal electrodes 14A and 14B are connected in parallel, are connected in series to the terminal electrodes 18A and 18B, compared to the case where the internal electrodes are connected in parallel to the terminal electrodes as in the prior art. Therefore, it is possible to achieve high ESR.

  In the present embodiment, the dummy electrode 16A connected to the terminal electrode 18A and the dummy electrode 16B connected to the terminal electrode 18B are disposed on a different surface from the ESR control electrodes 12A and 12B. Accordingly, the contact area of the electrode portion in contact with the terminal electrodes 18A and 18B is compared with the case where the terminal electrode 18A is connected only with the terminal connection conductor 22A and the connection with the terminal electrode 18B is performed only with the terminal connection conductor 22B. Becomes larger. As a result, sufficient adhesion between the terminal electrodes 18A and 18B and the terminal connection conductors 22A and 22B can be ensured, so that the occurrence of poor conduction can be suppressed. Ensuring adhesion by the dummy electrodes 16A and 16B is particularly effective when the number of ESR control electrodes 12A and 12B is small as in this embodiment.

  By the way, if the dummy electrodes 16A and 16B are located on the same plane as the ESR control electrodes 12A and 12B, the dummy electrodes 16A and 16B may be used when printing blur or manufacturing error occurs when forming the dummy electrodes 16A and 16B. May be connected to the terminal connection conductors 12A and 12B, and the ESR may be reduced, or the ESR control electrodes 12A and 12B may be connected to the terminal electrodes of different polarity via the dummy electrodes 16A and 16B. The function as the capacitor 1 may be lost.

  However, in the present embodiment, the dummy electrodes 16A and 16B are located on a different surface from the ESR control electrodes 12A and 12B. Therefore, even if printing bleeding or manufacturing error occurs when forming the dummy electrodes 16A and 16B, it is possible to prevent the dummy electrodes 16A and 16B from being connected to the terminal connection conductors 22A and 22B, thereby reducing ESR. Can be avoided. Further, when the dummy electrodes 16A and 16B are formed, printing blur, manufacturing error, and the like occur, and even when the dummy electrodes 16A and 16B are connected to the internal electrodes 14A and 14B, the capacitance is slightly reduced. Therefore, the function of the multilayer capacitor 1 as a whole is not lost.

  Furthermore, in this embodiment, the dummy electrode 16A is connected to the terminal electrode 18A, and the dummy electrode 16B is connected to the terminal electrode 18B. For this reason, when only the internal electrodes 14A and 14B are stacked, the generation of a step in the dielectric layer caused by the thickness of the internal electrodes 14A and 14B can be suppressed by the dummy electrodes 16A and 16B. That is, the dummy electrodes 16A and 16B function as a step absorbing member for the dielectric layer. Therefore, deformation of the dielectric body 10 can be prevented.

  Furthermore, in the present embodiment, the width W3 is set to be equal to or greater than the width W1 or the width W2. Therefore, the contact area of the electrode portion in contact with the terminal electrodes 18A and 18B is further increased. Accordingly, the adhesion between the terminal electrode 18A (18B) and the terminal connection conductor 22A (22B) becomes more sufficient, and the occurrence of poor conduction can be more reliably suppressed.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, if the width W3 is set to be equal to or greater than the width W1 or the width W2, the dummy electrode 16A and the terminal connection conductor 22A do not overlap each other when viewed from the stacking direction, and the dummy electrode 16B and the terminal connection The connection conductor 22B may not overlap each other when viewed from the stacking direction. If it does in this way, when the dielectric green sheet used as a dielectric material layer is laminated | stacked and crimped | bonded, dielectric green sheets will become easy to adhere | attach each other and generation | occurrence | production of an unnecessary level | step difference can be prevented.

  Further, when the dummy electrode 16A and the terminal connection conductor 22A do not overlap each other when viewed from the stacking direction, and the dummy electrode 16B and the terminal connection conductor 22B do not overlap each other when viewed from the stacking direction, the ESR control electrode 12A (terminal connection conductor 22A) and internal electrode 14B (dummy electrode 16A) are arranged inside dielectric body 10 in a state of being adjacent to each other in the stacking direction, and ESR control electrode 12B (terminal connection conductor) 22B) and the internal electrode 14A (dummy electrode 16B) are preferably disposed inside the dielectric body 10 in a state of being adjacent to each other in the stacking direction. In this way, it is possible to further prevent the occurrence of unnecessary steps.

Further, as shown in FIGS. 6 and 7, the number of dummy electrodes may be increased. Specifically, rectangular dummy electrodes 16A ₁ and 16A ₂ are formed on the surface of the dielectric layer A12 instead of the dummy electrodes 16A. The dummy electrodes 16A ₁ and 16A ₂ are both located on the side surface 10a side. The dummy electrodes 16A ₁ and 16A ₂ are both drawn out to the edge of the dielectric layer A12 on the side where the terminal electrode 18A is formed, and the ends thereof are exposed to the side surface 10a.

In addition, rectangular dummy electrodes 16B ₁ and 16B ₂ are formed on the surface of the dielectric layer A17 instead of the dummy electrodes 16B. The dummy electrodes 16B ₁ and 16B ₂ are both located on the side surface 10b side. The dummy electrodes 16B ₁ and 16B ₂ are both drawn out to the edge of the dielectric layer A17 on the side where the terminal electrode 18B is formed, and the ends thereof are exposed to the side surface 10b.

The sum (W3a + W3b) of the width W3a of the dummy electrodes 16A ₁ and 16B _{1 in} the short direction and the width W3b of the dummy electrodes 16A ₂ and 16B ₂ in the short direction is set to be equal to or greater than the width W1 or the width W2. Has been. Specifically, the widths W3a and W3b are set to about 0.5 to 3.5 times the width W1 or the width W2, respectively. In this way, the adhesion between the terminal electrode 18A (18B) and the terminal connection conductor 22A (22B) becomes more sufficient, and the occurrence of poor conduction can be more reliably suppressed. The widths of the dummy electrodes 16A ₁ , 16A ₂ , 16B ₁ , 16B ₂ may all be the same or may be all different.

The linear distance W4 between the dummy electrode 16A ₁ (16B ₁ ) and the dummy electrode 16A ₂ (16B ₂ ) is set to be equal to or greater than the width W1. Specifically, the width W4 is set to about 1 to 7 times the width W1. Also, the terminal connecting conductor 22A is located between the dummy electrode 16A ₁ and the dummy electrodes 16A ₂ viewed from the lamination direction, the terminal connecting conductor 22B, the second dummy electrode 16B when viewed from the laminating direction It is located between ₁ and the dummy electrode 16B _2.

  Further, as shown in FIGS. 8 and 9, a sub dummy electrode 28A connected only to the connecting electrode 20A or a sub dummy electrode 28B connected only to the connecting electrode 20B may be provided. In this way, when only the internal electrodes 14A and 14B are stacked, the sub dummy electrodes 28A and 28B can suppress the occurrence of a step in the dielectric layer caused by the thickness of the internal electrodes 14A and 14B. . That is, the sub dummy electrodes 28A and 28B function as a step absorbing member for the dielectric layer. Therefore, deformation of the dielectric body 10 can be prevented.

DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 10 ... Dielectric body (element body), 12A ... ESR control electrode (first ESR control electrode), 12B ... ESR control electrode (second ESR control electrode), 14A ... Internal electrode (first 1 internal electrode), 14B ... internal electrode (second internal electrode), 16A, 16A ₁ ... dummy electrode (first dummy electrode), 16A ₂ ... dummy electrode (third dummy electrode), 16B, 16B ₁ ... dummy electrode (second dummy electrode), 16B ₂ ... dummy electrode (fourth dummy electrode), 18A ... terminal electrode (first terminal electrode), 18B ... terminal electrode (second terminal electrode), 20A ... Connecting electrode (first connecting electrode), 20B ... Connecting electrode (second connecting electrode), 22A ... Terminal connecting conductor (first terminal connecting conductor), 22B ... Terminal connecting conductor (first 2 terminal connection conductor), 24A, for connection Connecting conductor (first connecting connecting conductor), 24B... Connecting connecting conductor (second connecting connecting conductor), 26A... Connecting connecting conductor (fourth connecting connecting conductor), 26B. (Third connection connecting conductor), 28A, 28B... Sub dummy electrode, A10 to A20.

Claims (6)

An element body in which a plurality of dielectric layers are laminated;
First and second terminal electrodes disposed on the outer surface of the element body;
First and second connection electrodes disposed on the outer surface of the element body;
First and second ESR control electrodes disposed inside the element body in a state of being separated from each other in the stacking direction of the dielectric layers;
A plurality of first and second internal electrodes respectively disposed in the element body while being separated from each other and adjacent to each other in the stacking direction;
First to fourth dummy electrodes disposed inside the element body;
The first ESR control electrode is integrally formed with a first terminal connection conductor connected to the first terminal electrode and a first connection connection conductor connected to the first connection electrode. Provided,
The second ESR control electrode is integrally formed with a second terminal connection conductor connected to the second terminal electrode and a second connection connection conductor connected to the second connection electrode. Provided,
The first internal electrode is integrally provided with a third connection connecting conductor connected to the second connection electrode,
The second internal electrode is integrally provided with a fourth connecting connection conductor connected to the first connecting electrode,
The first and second dummy electrodes are disposed on a different surface from the first and second ESR control electrodes,
The first dummy electrode is connected to the first terminal electrode;
The second dummy electrode is connected to the second terminal electrode ;
The third dummy electrode is connected to the first terminal electrode;
The fourth dummy electrode is connected to the second terminal electrode;
The first and third dummy electrodes and the first terminal connection conductor do not overlap each other when viewed from the stacking direction,
The second and fourth dummy electrodes and the second terminal connection conductor do not overlap each other when viewed from the stacking direction,
The first terminal connection conductor is located between the first dummy electrode and the third dummy electrode when viewed from the stacking direction,
The multilayer capacitor, wherein the second terminal connection conductor is located between the second dummy electrode and the fourth dummy electrode when viewed from the lamination direction . The separation width between the first dummy electrode and the third dummy electrode is set to be larger than the width of the first terminal connection conductor,
Wherein the second dummy electrode spaced width of the fourth dummy electrode is characterized in that it is set to be greater than the width of the second terminal connecting conductor according to claim 1 Multilayer capacitor. The first and third dummy electrodes are disposed on the same plane as the first internal electrode,
The second and fourth dummy electrodes are disposed on the same plane as the second internal electrode,
The first ESR control electrode is disposed inside the element body in a state adjacent to the first internal electrode in the stacking direction,
The said 2nd ESR control electrode is arrange | positioned inside the said element | base_body in the state adjacent to the said 2nd internal electrode in the said lamination direction, The Claim 1 or 2 characterized by the above-mentioned. Multilayer capacitor. The sum of the connection width between the first dummy electrode and the first terminal electrode and the connection width between the third dummy electrode and the first terminal electrode is equal to or greater than the width of the first terminal connection conductor. Set to
The sum of the connection width between the second dummy electrode and the second terminal electrode and the connection width between the fourth dummy electrode and the second terminal electrode is equal to or greater than the width of the second terminal connection conductor. The multilayer capacitor according to claim 1 , wherein the multilayer capacitor is set as follows. The total of the connection width between the first dummy electrode and the first terminal electrode and the connection width between the third dummy electrode and the first terminal electrode is the third or fourth connection conductor for connection. Is set to a width greater than
The sum of the connection width between the second dummy electrode and the second terminal electrode and the connection width between the fourth dummy electrode and the second terminal electrode is the third or fourth connection conductor for connection. The multilayer capacitor according to claim 1 , wherein the multilayer capacitor is set to be equal to or greater than the width of the multilayer capacitor. And further comprising first and second sub-dummy electrodes disposed inside the element body,
The first sub-dummy electrode is disposed on the same plane as the first internal electrode in a state of being separated from the first internal electrode and the first dummy electrode,
The second sub dummy electrode is disposed on the same plane as the second internal electrode in a state of being separated from the second internal electrode and the second dummy electrode,
The first sub-dummy electrode is connected to the first connecting electrode;
Said second Sabudami electrode, the second is connected to the connection electrode, characterized in that has, the multilayer capacitor according to any one of claims 1-5.

Images