JP2010056169A - 薄膜トランジスタ及びこれを用いた表示装置 - Google Patents
薄膜トランジスタ及びこれを用いた表示装置 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 144
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 description 21
- 239000010410 layer Substances 0.000 description 18
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/104—Materials and properties semiconductor poly-Si
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- Microelectronics & Electronic Packaging (AREA)
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- Computer Hardware Design (AREA)
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- Liquid Crystal (AREA)
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Abstract
【解決手段】 画素領域と周辺回路領域とを有する表示装置の周辺回路領域に形成される薄膜トランジスタである。チャネルを構成する多結晶シリコン薄膜13のゲート幅方向両端部において、ゲート電極15のゲート長が拡大され突出部15Aが形成されている。薄膜トランジスタのゲート長は2μm以下であり、ゲート幅は10μm以上である。突出部15Aの突出長は2μm以上であり、突出幅は0.5μm以上である。
【選択図】 図3
Description
通常構造の薄膜トランジスタにおいて、ハンプ特性のW長依存性を調べた。作製した薄膜トランジスタは、Nチャンネル薄膜トランジスタであり、L長=2μm、TOX=80nm、Vd=0.05Vである。前記薄膜トランジスタにおいて、BTS前後のI−V特性からハンプのシフトΔ1nAVth(電流値1.E−09におけるBTS前後の電圧値の差)を求め、W長と前記ハンプのシフトΔ1nAVthの関係を調べた。なお、印加したBTSは、Vg=12V、Vs=Vd=0V、温度=900℃、印加時間=2000秒である。
ゲート電極をH型構造とすることによりハンプが抑制できる理由を解明するため、ゲート電極をノーマル型、H型、H型(内側)とした場合について、それぞれ端部電流が流れる経路における抵抗値をシミュレーションにより算出した。なお、薄膜トランジスタのサイズは、W長=50μm、L長=2μm、TOX=80nm、LDD=1.25μmとし、(1)多結晶シリコン薄膜のドーパントは深さ方向に均一、(2)多結晶シリコン薄膜は埋め込み型、(3)全層テーパ加工なし、(4)ゲート電極、ソース電極、ドレイン電極はAl、(5)ソース電極及びドレイン電極はコンタクトホール上にしかない、(6)多結晶シリコン薄膜の端部に固定チャージ(厚さ10nm、幅1μm、濃度5×1017cm−3)がある、と仮定してシミュレーションを行った。
ノーマル型の薄膜トランジスタとH型の薄膜トランジスタについて、BTS前後のI−V特性を測定し、ハンプ特性の相違を調べた。なお、ノーマル型の薄膜トランジスタにおいては、W/L=50μm/2μm、TOX=50nmとした。H型の薄膜トランジスタにおいては、ゲート電極の突出部の突出長=8μm、突出幅=2.5μm、W/L=50μm/2μm、TOX=50nmとした。また、BTSは、Vg=12V、Vs=Vd=0V、温度=150℃、印加時間=2000秒とした。結果を図10(a)及び図10(b)に示す。なお、図10(a)はノーマル型の薄膜トランジスタのBTS前後のI−V特性を示すものであり、図10(b)はH型の薄膜トランジスタのBTS前後のI−V特性を示すものである。
先ず、H型の薄膜トランジスタにおいて、ゲート電極突出部の突出長を0μm(ノーマル型に相当)、2μm、5μm、8μmとし、それぞれについてBTS前後のI−V特性を測定し、ハンプのシフトΔ1nAVthを測定した。BTSは、Vg=12V、Vs=Vd=0V、温度=150℃、印加時間=2000秒である。
Claims (6)
- 画素領域と周辺回路領域とを有する表示装置の前記周辺回路領域に形成される薄膜トランジスタであって、
チャネルを構成する多結晶シリコン薄膜のゲート幅方向両端部において、ゲート電極のゲート長が拡大され突出部が形成されていることを特徴とする薄膜トランジスタ。 - ゲート長が2μm以下であり、ゲート幅が10μm以上であることを特徴とする請求項1記載の薄膜トランジスタ。
- 前記突出部の突出長が2μm以上であり、前記突出部の突出幅が0.5μm以上であることを特徴とする請求項2記載の薄膜トランジスタ。
- 前記突出部は、多結晶シリコン薄膜をチャネル方向に横切り、その両側に突出するように形成されていることを特徴とする請求項1から3のいずれか1項記載の薄膜トランジスタ。
- 前記突出部は、多結晶シリコン薄膜の端縁より内側に形成されていることを特徴とする請求項4記載の薄膜トランジスタ。
- 画素領域と周辺回路領域とを有し、それぞれに薄膜トランジスタが形成されてなる表示装置であって、
前記周辺回路領域に形成される薄膜トランジスタの少なくとも一部において、チャネルを構成する多結晶シリコン薄膜のゲート幅方向両端部におけるゲート電極のゲート長が拡大されて突出部が形成されていることを特徴とする表示装置。
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JP2008217278A JP2010056169A (ja) | 2008-08-26 | 2008-08-26 | 薄膜トランジスタ及びこれを用いた表示装置 |
US12/547,340 US8085355B2 (en) | 2008-08-26 | 2009-08-25 | Structure of thin film transistors and liquid crystal display device having the same |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08116063A (ja) * | 1994-10-14 | 1996-05-07 | Sharp Corp | 薄膜トランジスター及び液晶表示装置 |
JPH10270699A (ja) * | 1997-03-26 | 1998-10-09 | Seiko Epson Corp | 薄膜トランジスタ及びそれを用いた液晶表示装置及びcmos回路 |
JP2006128160A (ja) * | 2004-10-26 | 2006-05-18 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2007103910A (ja) * | 2005-09-30 | 2007-04-19 | Lg Philips Lcd Co Ltd | 液晶表示装置用アレイ基板及びその製造方法、液晶表示装置用薄膜トランジスタ及びその製造方法並びに液晶表示装置 |
JP2008021760A (ja) * | 2006-07-12 | 2008-01-31 | Hitachi Displays Ltd | 薄膜トランジスタおよび画像表示装置 |
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CN100502047C (zh) * | 1996-06-28 | 2009-06-17 | 精工爱普生株式会社 | 薄膜晶体管 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08116063A (ja) * | 1994-10-14 | 1996-05-07 | Sharp Corp | 薄膜トランジスター及び液晶表示装置 |
JPH10270699A (ja) * | 1997-03-26 | 1998-10-09 | Seiko Epson Corp | 薄膜トランジスタ及びそれを用いた液晶表示装置及びcmos回路 |
JP2006128160A (ja) * | 2004-10-26 | 2006-05-18 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2007103910A (ja) * | 2005-09-30 | 2007-04-19 | Lg Philips Lcd Co Ltd | 液晶表示装置用アレイ基板及びその製造方法、液晶表示装置用薄膜トランジスタ及びその製造方法並びに液晶表示装置 |
JP2008021760A (ja) * | 2006-07-12 | 2008-01-31 | Hitachi Displays Ltd | 薄膜トランジスタおよび画像表示装置 |
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