JP2009515377A - 高分解能および広ダイナミックレンジ積分器 - Google Patents
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- H04N25/57—Control of the dynamic range
- H04N25/571—Control of the dynamic range involving a non-linear response
- H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
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- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
- H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
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Abstract
Description
この発明は概してセンサ装置の分野に関し、より特定的には積分方法および装置に関する。
積分関数または積分は当該技術において周知である数学関数である。手短に言えば、積分とは範囲または範囲の総括として解釈され得る数学的対象である。信号が曲線としてプロットされるならば、その信号の積分はその曲線の中の範囲である。積分器とは自身の入力に存在する信号を積分し、自身の出力でその入力信号の積分されたものを発生する装置である。
値は、0から31または二値表記では00000から11111の範囲にわたる。バー320上には32の対応する目盛りがあり、その各々は特定のアナログ電圧値に対応する。
0の出力が利用可能な電源電圧よりも大きい値を有する必要が時にはあるかもしれないということを意味する。
この発明の一局面によれば、積分方法は、入力信号に結合される発振器によって与えられる応答を用いて、入力信号の積分された値を生成するステップを含む。この積分された信号は信号それ自体ではなく、発振器の応答を用いて生成されるので、入力電圧のより広いダイナミックレンジが積分器によってサポートされ得る。本発明の積分器は、センサの電源よりも大きい出力値を示し得る。なぜならば、発振器出力の飽和が起こり得ないからである。さらに、本発明の積分器は向上された分解能ですべての範囲の電圧を示し得る。その結果、量子化誤差は低減され、信号の強度レベルはよりしっかりと圧縮され得る。
本発明は、発振器の周波数応答を用いて入力信号を積分する積分方法および積分器を提供する。本発明は、信号の電圧と発振器出力の周波数との間に関係性が存在するということ、および発振器出力の位相が積分された信号値に相関され得るということを認識する。この関連性により、積分された出力値には高度の分解能が与えられ、これにより量子化誤差に関連する問題を解消する。さらに、積分器出力値は単純な電圧ではなく発振器の位相に基づくので、その結果の精度は改善され、そのため飽和が起こることはない。
式中、fdelta=fgain・Sin である。
ような回路と関連の波形が図8Aおよび図8Bに図示される。図8AのVCO出力は三角波の波形である。時間t=0、0.5TPおよびTPにおいて、VCO出力波形は、0、πおよび2πラジアンの変動に対応する、900、910および920の符号を付される状態に至る。
両端の電圧の増大はすぐにコンパレータ820の状態を変化させる。
ントを2で除算することによって与えられる。
式中、積分範囲は持続時間ΔTを超える。積分項を以下のように分解する。
=K+fgain・∫Sindt
式中、項Kは一定値fnomとΔT(積分時間)との関数であり、したがって周知である。fnom=0である特別な場合、K=0であり、かつΔθ=fgain・∫Sindtである。
fnom=0である特別な場合はK=0であり、∫Sindt=Δθ/fgainである。
器出力が変化する位相Δθは積分時間ΔTの間の入力制御信号の積分に比例し、この2つが比例する。最小限のΔθの値は最も小さな積分出力について発生する。しかし
fgain・∫Sindt=Δθ−K
である。
Claims (16)
- ある期間にわたって入力信号を積分するための方法であって、
前記入力信号に応答して生成される位相情報を用いて前記入力信号の積分された値を生成するステップを含む、方法。 - 前記位相情報は、前記入力信号を受取り、前記入力信号の値に応答して周波数が変動する出力波形を与えるよう結合される電圧制御発振器によって与えられる、請求項1に記載の積分方法。
- 前記生成するステップは、前記出力波形の変化する位相周期の合計を積算するステップを含む、請求項2に記載の方法。
- 前記生成するステップは、前記期間の終わりに前記出力波形の位相を同定し、前記出力波形の変化する周期の合計を積算するステップをさらに含み、前記積分された値は前記位相および周期の前記合計によって決定される、請求項1に記載の方法。
- 前記入力信号の強度に従って前記発振器の周波数を調整するステップをさらに含む、請求項2に記載の方法。
- 入力信号を受取るための入力と、
積分された信号を与えるための出力と、
前記入力に結合され、前記入力信号の値に従って出力波形応答を与えるよう動作可能な発振器と、
積分器の結果を与えるよう、前記発振器によって与えられる前記出力波形応答を処理するためのロジックとを含む、積分器。 - 前記応答を処理するための前記ロジックは、積分期間の間に出力波形の変化する位相を積算するためのロジックを含む、請求項6に記載の積分器。
- 前記変化する位相を決定するためのロジックは、前記積分期間の始まりと終わりでの前記出力波形の位相の差を同定するための前記ロジックを含む、請求項7に記載の積分器。
- 前記変化する位相を決定するための前記ロジックは、電圧−位相変換器を含む、請求項8に記載の積分器。
- 処理するための前記ロジックは、前記発振器によって与えられる前記出力波形信号の周期の合計を積算するための積算器をさらに含む、請求項6に記載の方法。
- 処理するための前記ロジックは、前記積分期間の終わりに前記出力波形の位相を決定するためのロジックをさらに含み、前記積分された値は前記位相および周期の前記合計に従って決定される、請求項10に記載の方法。
- 前記発振器は、前記入力信号の強度に従って前記発振器の周波数を調整するための入力を含む、請求項6に記載の積分器。
- 前記発振器は電圧制御発振器である、請求項6に記載の積分器。
- 前記発振器は電流制御発振器である、請求項6に記載の積分器。
- 入力信号を、前記入力信号の値に関係付けられる周波数を有する波形に変換するステップと、
前記波形の変化する位相の合計を積算して、前記信号の積分された値を生成するステップとを含む、積分方法。 - 入力信号を、前記入力信号の値に関係付けられる周波数を有する波形に変換するための手段と、
前記波形の変化する位相の合計を積算して、前記信号の積分された値を生成するための手段とを備える、積分器。
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US72789705P | 2005-10-18 | 2005-10-18 | |
PCT/US2006/036786 WO2007044191A2 (en) | 2005-09-21 | 2006-09-21 | High resolution and wide dynamic range integrator |
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JP2009515377A true JP2009515377A (ja) | 2009-04-09 |
JP2009515377A5 JP2009515377A5 (ja) | 2010-01-07 |
JP4537483B2 JP4537483B2 (ja) | 2010-09-01 |
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JP2008532372A Active JP5242399B2 (ja) | 2005-09-21 | 2006-09-21 | ゲインを制御した高ダイナミックレンジ感度センサ素子またはアレイのためのシステムおよび方法 |
JP2008532377A Expired - Fee Related JP5059767B2 (ja) | 2005-09-21 | 2006-09-21 | 高ダイナミックレンジ感度センサ素子またはアレイのためのシステムおよび方法 |
JP2008532376A Expired - Fee Related JP4699524B2 (ja) | 2005-09-21 | 2006-09-21 | 測光およびリアルタイムのレポート能力を有する画像センサ素子またはアレイのためのシステムおよび方法 |
JP2008532373A Expired - Fee Related JP4537483B2 (ja) | 2005-09-21 | 2006-09-21 | 高分解能および広ダイナミックレンジ積分器 |
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JP2008532377A Expired - Fee Related JP5059767B2 (ja) | 2005-09-21 | 2006-09-21 | 高ダイナミックレンジ感度センサ素子またはアレイのためのシステムおよび方法 |
JP2008532376A Expired - Fee Related JP4699524B2 (ja) | 2005-09-21 | 2006-09-21 | 測光およびリアルタイムのレポート能力を有する画像センサ素子またはアレイのためのシステムおよび方法 |
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JP (4) | JP5242399B2 (ja) |
KR (4) | KR101152859B1 (ja) |
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