JP2009259945A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title description 26
- 239000000758 substrate Substances 0.000 claims abstract description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 48
- 230000002093 peripheral effect Effects 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 10
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 7
- 230000001154 acute effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 37
- 229920005591 polysilicon Polymers 0.000 description 37
- 230000002159 abnormal effect Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- Semiconductor Memories (AREA)
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Abstract
【解決手段】半導体装置は、第1の界面膜53Aを介在させて、第1の導電膜からなる第1の下層電極51Aと、第2の導電膜からなる第1の上層電極52Aとが積層された第1の積層電極22を有するメモリセル12と、第2の導電膜からなるダイオード電極52Bと、ダイオード電極32と基板15との界面に形成されたシリコン酸化膜である第2の界面膜53Bとを有するダイオード13とを備えている。第1の界面膜53Aは、下層電極51Aと上層電極52Aとの電気的接続を維持する膜厚であり、第2の界面膜53Bは、基板15とダイオード電極52Bとの間におけるエピタキシャル成長を阻害する膜厚である。
【選択図】図1
Description
13 保護ダイオード
14 トランジスタ
15 半導体基板
20 ビット線拡散層
21 第1のゲート絶縁膜
22 第1のゲート電極
25 ビット線絶縁膜
26 シリコン酸化膜
31 絶縁膜
41 第2のゲート絶縁膜
42 第2のゲート電極
51 第1のポリシリコン膜
51A 下層電極
51B 下層ポリシリコン膜
51C 下層電極
52A 上層電極
52B ダイオード電極
52C 上層電極
53 シリコン酸化膜
53A 第1の界面膜
53B 第2の界面膜
53C 第3の界面膜
61 マスク絶縁膜
61A マスク酸化膜
61B マスク窒化膜
62 第1の開口部
Claims (9)
- 基板のメモリセル領域に形成され、シリコン酸化膜である第1の界面膜を介在させて、第1の導電膜からなる第1の下層電極と、第2の導電膜からなる第1の上層電極とが積層された第1の積層電極を有するメモリセルと、
前記基板のダイオード領域に形成され、前記第2の導電膜からなるダイオード電極と、前記ダイオード電極と前記基板との界面に形成された前記シリコン酸化膜である第2の界面膜とを有するダイオードとを備え、
前記第1の界面膜は、前記第1の下層電極と前記第1の上層電極との電気的接続を維持する膜厚であり、前記第2の界面膜は、前記基板と前記ダイオード電極との間においてエピタキシャル成長を阻害する膜厚であることを特徴とする半導体装置。 - 前記第1の界面膜と、前記第2の界面膜とは膜厚が等しいことを特徴とする請求項1に記載の半導体装置。
- 前記第1の界面膜及び第2の界面膜は、膜厚が0.7nm以上且つ1.3nm以下であることを特徴とする請求項1又は2のいずれか1項に記載の半導体装置。
- 前記基板の周辺回路領域に形成され、前記シリコン酸化膜である第3の界面膜を介在させて、前記第1の導電膜からなる第2の下層電極と、前記第2の導電膜からなる第2の上層電極とが積層された第2の積層電極を有する周辺トランジスタをさらに備えていることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 前記メモリセルは、
前記基板における隣接する前記第1の積層電極同士の間の領域に形成され、前記隣接する第1の積層電極によって共有されたビット線拡散層と、
前記ビット線拡散層の上に形成されたビット線絶縁膜とを有し、
前記ビット線絶縁膜は、前記第1の下層電極よりも高さが高く且つ前記第1の下層電極よりも上側の部分の幅は、下側の部分の幅よりも狭いことを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。 - 前記第1の下層電極の上部の角は鋭角な形状であることを特徴とする請求項1から5のいずれか1項に記載の半導体装置。
- 基板のメモリセル領域の上に第1の絶縁膜を形成する工程(a)と、
前記基板のダイオード領域の上に第2の絶縁膜を形成する工程(b)と、
前記第1の絶縁膜及び第2の絶縁膜の上に第1の導電膜を形成する工程(c)と、
前記メモリセル領域において、マスク絶縁膜を用いて前記第1の導電膜及び第1の絶縁膜を選択的に除去して、第1の開口部を形成すると共に、前記ダイオード領域において、前記マスク絶縁膜を用いて前記第1の導電膜及び第2の絶縁膜を選択的に除去して、前記基板を露出する第2の開口部を形成する工程(d)と、
前記メモリセル領域において、前記基板の前記第1の開口部から露出した領域にビット線拡散層を形成する工程(e)と、
前記第1の開口部を埋め込む埋め込みビット線絶縁膜を形成する工程(f)と、
前記メモリセル領域及びダイオード領域において、前記マスク絶縁膜を除去すると共に、前記第1の導電膜の上及び前記基板の前記第2の開口部から露出した領域の上にシリコン酸化膜を形成する工程(g)と、
前記メモリセル領域及びダイオード領域の上の全面に第2の導電膜を形成する工程(i)とを備え、
前記工程(g)では、前記マスク絶縁膜を除去した後、オゾン洗浄を行うことにより、前記シリコン酸化膜を形成することを特徴とする半導体装置の製造方法。 - 前記シリコン酸化膜のうち前記第1の導電膜の上の上に形成された部分と、前記基板の前記第2の開口部内から露出した領域の上に形成された部分とは、膜厚が同一であることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記シリコン酸化膜は、膜厚が0.7nm以上且つ1.3nm以下であることを特徴とする請求項7又は8に記載の半導体装置の製造方法。
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JP2008105642A JP5274878B2 (ja) | 2008-04-15 | 2008-04-15 | 半導体装置及びその製造方法 |
US12/369,283 US7834401B2 (en) | 2008-04-15 | 2009-02-11 | Semiconductor device and fabrication method for the same |
US12/899,164 US8076196B2 (en) | 2008-04-15 | 2010-10-06 | Semiconductor device and fabrication method for the same |
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US6757202B2 (en) | 2002-08-29 | 2004-06-29 | Micron Technology, Inc. | Bias sensing in DRAM sense amplifiers |
US7635773B2 (en) | 2008-04-28 | 2009-12-22 | Cydex Pharmaceuticals, Inc. | Sulfoalkyl ether cyclodextrin compositions |
DK2814849T3 (da) | 2012-02-15 | 2020-03-09 | Cydex Pharmaceuticals Inc | Fremgangsmåde til fremstilling af cyclodextrin-derivater |
CA2888822C (en) | 2012-10-22 | 2021-01-26 | Cydex Pharmaceuticals, Inc. | Alkylated cyclodextrin compositions and processes for preparing and using the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09115869A (ja) * | 1995-08-10 | 1997-05-02 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JPH11176954A (ja) * | 1997-12-05 | 1999-07-02 | Seiko Epson Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2000031436A (ja) * | 1998-07-09 | 2000-01-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2005310990A (ja) * | 2004-04-20 | 2005-11-04 | Renesas Technology Corp | 半導体装置の製造方法および半導体製造装置 |
WO2006117851A1 (ja) * | 2005-04-27 | 2006-11-09 | Spansion Llc | 半導体装置およびその製造方法 |
JP2007189204A (ja) * | 2005-12-13 | 2007-07-26 | Matsushita Electric Ind Co Ltd | 半導体記憶装置及びその製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57130461A (en) * | 1981-02-06 | 1982-08-12 | Hitachi Ltd | Semiconductor memory storage |
US5148255A (en) * | 1985-09-25 | 1992-09-15 | Hitachi, Ltd. | Semiconductor memory device |
US5324982A (en) * | 1985-09-25 | 1994-06-28 | Hitachi, Ltd. | Semiconductor memory device having bipolar transistor and structure to avoid soft error |
JP3059442B2 (ja) * | 1988-11-09 | 2000-07-04 | 株式会社日立製作所 | 半導体記憶装置 |
JPH1140765A (ja) * | 1997-07-16 | 1999-02-12 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
EP1017097A1 (en) * | 1998-12-29 | 2000-07-05 | STMicroelectronics S.r.l. | Manufacturing method of salicide contacts for non-volatile memory |
JP4084041B2 (ja) * | 1999-06-17 | 2008-04-30 | 株式会社ルネサステクノロジ | 半導体記憶装置及びその製造方法 |
JP4149644B2 (ja) * | 2000-08-11 | 2008-09-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3998930B2 (ja) * | 2001-08-01 | 2007-10-31 | 株式会社半導体エネルギー研究所 | 結晶質半導体膜の作製方法及び製造装置 |
US6737302B2 (en) * | 2001-10-31 | 2004-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for field-effect transistor |
JP2004055826A (ja) * | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2004319587A (ja) * | 2003-04-11 | 2004-11-11 | Sharp Corp | メモリセル、メモリ装置及びメモリセル製造方法 |
US6869844B1 (en) * | 2003-11-05 | 2005-03-22 | Advanced Micro Device, Inc. | Method and structure for protecting NROM devices from induced charge damage during device fabrication |
US7439591B2 (en) * | 2004-10-05 | 2008-10-21 | Infineon Technologies Ag | Gate layer diode method and apparatus |
KR20080095683A (ko) * | 2007-04-25 | 2008-10-29 | 삼성전자주식회사 | 상변화 메모리 소자 및 그 형성 방법 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09115869A (ja) * | 1995-08-10 | 1997-05-02 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JPH11176954A (ja) * | 1997-12-05 | 1999-07-02 | Seiko Epson Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2000031436A (ja) * | 1998-07-09 | 2000-01-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2005310990A (ja) * | 2004-04-20 | 2005-11-04 | Renesas Technology Corp | 半導体装置の製造方法および半導体製造装置 |
WO2006117851A1 (ja) * | 2005-04-27 | 2006-11-09 | Spansion Llc | 半導体装置およびその製造方法 |
JP2007189204A (ja) * | 2005-12-13 | 2007-07-26 | Matsushita Electric Ind Co Ltd | 半導体記憶装置及びその製造方法 |
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US20110021013A1 (en) | 2011-01-27 |
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US7834401B2 (en) | 2010-11-16 |
US8076196B2 (en) | 2011-12-13 |
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