JP2009194797A - Digital agc circuit and angular velocity sensor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact digital AGC circuit requiring no multiplier for operation, such as gain calculation. <P>SOLUTION: The digital AGC circuit comprises: a ΣΔ modulator 61 composed of a D/A conversion means 43 for outputting an amount of charge of at least two levels, an integration means 44 for adding/integrating a signal output from the D/A conversion means 43 and a signal input from the outside to hold an integrated value, a comparison means 45 for comparing the integrated value output from the integration means 44 with a prescribed value, and a D/A switching means 46 for switching the output of the D/A conversion means 43 according to the output of the comparison means 45; an amplitude detection means 71; a gain calculation means 72; and a substitution operation means 73. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention particularly relates to a digital AGC circuit used for vibration control of a sensor element in a sensor device and an angular velocity sensor using the digital AGC circuit.

  A conventional digital AGC circuit of this type will be described below with reference to the drawings.

  FIG. 9 shows a conventional digital AGC circuit.

  In FIG. 9, reference numeral 1 denotes a gain calculating means, which comprises a memory 2, a multiplier 4 and an adder / subtractor 5, for an input signal X obtained by digitizing an analog input signal by A / D conversion. Gain G is determined. Next, the output signal Z is obtained by selecting the gain G currently set from the register B and the input signal X from the register B by the control signals SEL 1 and SEL 2 and multiplying by the multiplier 4.

As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP 7-336174 A

  However, in the above-described conventional configuration, the multiplier 4 is used in the digital AGC circuit or its peripheral circuit in operations such as gain calculation, so that the number of input / output bits and the operation speed of the multiplier 4 increase. It had the problem of becoming a large circuit.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide a small AGC circuit that does not require a multiplier in an operation such as gain calculation and an angular velocity sensor using the same.

  In order to achieve the above object, the present invention has the following configuration.

  The invention according to claim 1 of the present invention adds and integrates a DA converter that outputs charge amounts of at least two levels, a signal output from the DA converter and an externally input signal, An integrating means for holding the integrated value; a comparing means for comparing the integrated value output from the integrating means with a predetermined value; and a DA switching means for switching the output of the DA converting means in accordance with the output of the comparing means. The sigma-delta modulator, the amplitude detection means, the gain calculation means, and the replacement calculation means are configured. According to this configuration, the digital AGC circuit is replaced with the amplitude detection means, the gain calculation means, and the replacement. Since the low-bit pulse density modulation signal output from the ΣΔ modulator is calculated by the replacement calculation unit in the amplitude detection unit and the gain calculation unit By performing the replacement operation, there is an effect that a small-sized and low-cost digital AGC circuit that can be converted into a multi-bit pulse density modulation signal whose gain is controlled without using a multiplier can be provided. Is.

  According to the second aspect of the present invention, the bit calculation unit and the addition calculation unit are provided in the gain calculation unit. According to this configuration, the amplitude information output from the amplitude detection unit is used as a source. In addition, since a gain having an arbitrary gain characteristic can be calculated using only the bit shift calculation means and the addition calculation means without using a multiplier, it is possible to provide a small and low-cost digital AGC circuit. It is what has.

  The invention according to claim 3 of the present invention is particularly configured to input the data stored in the ROM to the gain calculation means. According to this configuration, the data stored in the ROM is used as the gain calculation means. Since it is configured to input, it is possible to change the AGC gain characteristic calculated by the gain calculating means based on data stored in a ROM such as an EEPROM, so that even if the target to be AGC changes, the ROM value It is possible to provide a digital AGC circuit that can be handled only by changing the above.

  According to the fourth aspect of the present invention, in particular, the amplitude detection circuit is provided with a digital filter and a full-wave rectification circuit. According to this configuration, the amplitude detection circuit includes a digital filter and a full-wave rectification circuit. Therefore, the low-bit pulse density modulation signal output from the ΣΔ modulator is converted into multi-bits by removing harmonic noise with a digital filter, rectified with a full-wave rectifier circuit, and further smoothed with a digital filter. As a result, even if the analog signal input to the ΣΔ modulator and the sampling timing in the ΣΔ modulator are asynchronous, it is possible to acquire the amplitude information of the input signal stably, thereby stabilizing the AGC characteristic. It has the effect of.

  According to the fifth aspect of the present invention, in particular, the digital filter is composed of the bit shift operation means and the addition operation means. According to this configuration, the digital filter is composed of the bit shift operation means, the addition operation means, Therefore, it is possible to perform coefficient calculation by bit shift calculation without using a multiplier using the fact that coefficient calculation in the digital filter is calculation with a preset value. The digital AGC circuit using the digital filter can be downsized.

  According to the sixth aspect of the present invention, in particular, a configuration in which a digital filter to which the output signal of the replacement operation means is input and a bit shift operation means to which the output of the digital filter is input is added to the subsequent stage of the digital AGC circuit. According to this configuration, the digital filter to which the output signal of the substitution calculation means is input and the bit shift calculation means to which the output of the digital filter is input are added to the subsequent stage of the digital AGC circuit. In addition, the present invention has an operational effect that a high-accuracy gain control can be performed without using a multiplier and a low-noise digital AGC circuit can be provided.

  According to the seventh aspect of the present invention, in particular, the digital filter is composed of a bit shift operation means and an addition operation means. According to this configuration, the digital filter is composed of a bit shift operation means and an addition operation means. Therefore, it is possible to perform coefficient calculation by bit shift calculation without using a multiplier using the fact that coefficient calculation in the digital filter is calculation with a preset value. The digital AGC circuit using the digital filter has the effect of being small and low cost.

  According to an eighth aspect of the present invention, there is provided a sensor element having a drive electrode, a sense electrode, and a monitor electrode, a drive circuit for driving the sensor element to vibrate with a predetermined amplitude, and the sense electrode in the sensor element. A sense circuit for converting a signal output from the sensor into an angular velocity output signal, the drive circuit including DA conversion means for outputting charge amounts of at least two levels, and a signal output from a monitor electrode in the sensor element; An integration circuit that integrates the charge output from the DA conversion means and holds the integration value; a comparison means that compares the integration value output from the integration circuit with at least one predetermined value; and A ΣΔ modulator configured by DA switching means for switching the output of the DA conversion means according to the output, amplitude detection means, gain calculation means, In this configuration, the digital AGC circuit is provided with an amplitude detecting means, a gain calculating means, and a replacement calculating means. Therefore, the low-bit pulse density modulation signal output from the ΣΔ modulator is replaced with the gain calculated in the amplitude detecting means and the gain calculating means by the replacement calculating means. Since a multi-bit pulse density modulation signal whose gain is controlled without using it is output from the drive circuit, it has an effect that a small and low-cost angular velocity sensor can be obtained.

  In the invention according to claim 9 of the present invention, in particular, the gain calculation means is composed of a bit shift calculation means and an addition calculation means. According to this configuration, the gain calculation means is combined with the bit shift calculation means and the addition calculation means. Therefore, based on the amplitude information output from the amplitude detection means, a gain having an arbitrary gain characteristic can be calculated by using only the bit shift calculation means and the addition calculation means without using a multiplier. It has a working effect.

  The invention according to claim 10 of the present invention is particularly configured to input the data stored in the ROM to the gain calculating means. According to this configuration, the data stored in the ROM is used as the gain calculating means. Since it is configured to input, the AGC gain characteristic calculated by the gain calculation means can be changed based on the data stored in the ROM such as EEPROM, so that depending on the characteristics of the sensor element used and the application of the sensor This has the effect of providing an angular velocity sensor that can appropriately change the value written to the ROM.

  According to the eleventh aspect of the present invention, in particular, the amplitude detection circuit is provided with a digital filter and a full-wave rectification circuit. According to this configuration, the amplitude detection circuit includes a digital filter and a full-wave rectification circuit. Therefore, the low-bit pulse density modulation signal output from the ΣΔ modulator is converted into multi-bits by removing harmonic noise with a digital filter, rectified with a full-wave rectifier circuit, and smoothed with a digital filter. Thus, even if the analog signal input to the ΣΔ modulator and the sampling timing of the ΣΔ modulator are asynchronous, the amplitude information of the input signal can be obtained stably.

  According to the twelfth aspect of the present invention, in particular, the digital filter is composed of a bit shift arithmetic means and an addition arithmetic means. According to this configuration, the digital filter is composed of a bit shift arithmetic means and an addition arithmetic means. Therefore, it is possible to perform coefficient calculation by bit shift calculation without using a multiplier using the fact that coefficient calculation in the digital filter is calculation with a preset value. The digital AGC circuit using the digital filter has the effect of being small and low cost.

  According to the thirteenth aspect of the present invention, in particular, the drive circuit is provided with a DA converter that outputs a multi-bit signal in analog form. According to this configuration, the DA that outputs a multi-bit signal to the drive circuit in analog form is provided. Since the converter is provided, it is possible to control the vibration of the sensor element by analog output of the gain-controlled multi-bit pulse density modulation signal output from the digital AGC circuit to the sensor element. The drive circuit can be configured with a small number of circuits such as a modulator, a digital AGC circuit, and a DA converter.

  According to the fourteenth aspect of the present invention, in particular, a digital filter for filtering the output of the digital AGC circuit and a bit shift operation means for inputting the output of the digital filter are added to the subsequent stage of the digital AGC circuit. According to this configuration, the digital filter for filtering the output of the digital AGC circuit and the bit shift operation means to which the output of the digital filter is input are added to the subsequent stage of the digital AGC circuit. In addition, a high-accuracy gain-controlled signal is obtained without using a multiplier, and at the same time, only the resonance frequency of the sensor element is extracted and the signal from which the noise component is removed is input to the drive circuit, and the drive signal is output As a result, a small and low-cost angular velocity sensor can be obtained. Is shall.

  According to the fifteenth aspect of the present invention, in particular, the digital filter is composed of a bit shift calculation means and an addition calculation means. According to this configuration, the digital filter is composed of a bit shift calculation means, an addition calculation means, Therefore, it is possible to perform coefficient calculation by bit shift calculation without using a multiplier using the fact that coefficient calculation in the digital filter is calculation with a preset value. The digital AGC circuit using the digital filter has the effect of being small and low cost.

  According to the sixteenth aspect of the present invention, in particular, the data stored in the ROM is input to the digital filter. According to this configuration, the data stored in the ROM is input to the digital filter. Since it is configured, it is possible to change the filter characteristics by determining the coefficient value that determines the filter characteristics in the digital filter based on the data stored in the ROM such as EEPROM, and the sensor element characteristics and sensor The filter characteristic can be changed by changing the value written to the ROM according to the application.

  According to the seventeenth aspect of the present invention, particularly, an analog filter for filtering the output signal of the drive circuit is provided. According to this configuration, an analog filter for filtering the output signal of the drive circuit is provided. Therefore, the output signal of the drive circuit is filtered by an analog filter whose frequency characteristic is set so as to remove the unnecessary frequency component having a high resonance gain of the sensor element from the main frequency component of the output signal of the drive circuit. The device can be supplied to the element, thereby having an effect that an angular velocity sensor with less noise can be provided.

  As described above, the digital AGC circuit according to the present invention adds and integrates a DA conversion unit that outputs charge amounts of at least two levels, a signal output from the DA conversion unit, and a signal input from the outside. An integrating means for holding the integrated value; a comparing means for comparing the integrated value output from the integrating means with a predetermined value; and a DA switching means for switching the output of the DA converting means in accordance with the output of the comparing means. Since the ΣΔ modulator, the amplitude detecting means, the gain calculating means, and the replacement calculating means are configured, the low-bit pulse density modulation signal output from the ΣΔ modulator is amplified by the replacement calculating means. The gain calculated by the detection means and the gain calculation means is replaced with a gain, and thereby, a multi-bit whose gain is controlled without using a multiplier. In which an excellent effect of being able to provide a pulse density modulation signal low cost convertible compact to digital AGC circuit.

(Embodiment 1)
Hereinafter, a digital AGC circuit and an angular velocity sensor using the same according to Embodiment 1 of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of an angular velocity sensor using a digital AGC circuit according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 30 denotes a sensor element. The sensor element 30 includes a vibrating body 31, a drive electrode 32 having a piezoelectric body for vibrating the vibrating body 31, and a piezoelectric body that generates an electric charge according to the vibration state. And a pair of sense electrodes having a piezoelectric body that generates an electric charge when an angular velocity is applied to the sensor element 30. Further, the pair of sense electrodes in the sensor element 30 includes a first sense electrode 34 and a second sense electrode 35 that generates charges having a polarity opposite to that of the first sense electrode 34. Reference numeral 41 denotes a drive circuit. The drive circuit 41 includes an input switching means 42, a DA conversion means 43, an integration means 44, a comparison means 45, a DA switching means 46, a digital AGC circuit 47, a digital filter 48, and a drive circuit 49. Has been. Further, the input switching means 42 in the drive circuit 41 is connected to the monitor electrode 33 in the vibrating body 31 and is constituted by an analog switch that operates at the sixth timing Φ6. Further, the DA switching means 46 in the drive circuit 41 has a first reference voltage 50 and a second reference voltage 51, and the first reference voltage 50 and the second reference voltage 51 are changed to the sixth reference voltage 50 and the second reference voltage 51, respectively. Switching is performed by a predetermined signal at timing Φ6. Further, the drive circuit 41 is provided with DA output means 52. The DA output means 52 is connected to the capacitor 53 to which the output signal of the DA switching means 46 is input, and is connected to both ends of the capacitor 53. It is composed of SWs 54 and 55 that operate at the fifth timing Φ5 and discharge the capacitor 53. The DA switching means 46 and the DA output means 52 constitute a DA converting means 43. The DA converting means 43 discharges the electric charge of the capacitor 53 at the fifth timing Φ5, and further the sixth timing. Charges corresponding to the reference voltage output by the DA switching means 46 at Φ6 are input / output. Reference numeral 56 denotes an SW. The outputs of the input switching means 42 and the DA converting means 43 are input to the SW 56 and output at the sixth timing Φ6.

  Reference numeral 44 denotes an integrating means, to which the output of the SW 56 is input. The integrating means 44 comprises an operational amplifier 57 and a capacitor 58 connected to the feedback of the operational amplifier 57. Then, the input signal to the integrating means 44 is integrated by the capacitor 58 at the sixth timing Φ6. Reference numeral 45 denotes a comparison means. The comparison means 45 receives an integration signal output from the integration means 44, and compares the integration signal with a predetermined value. The comparator 59 outputs 1 And a D-type flip-flop 60 to which a bit digital signal is input. The D-type flip-flop 60 latches the 1-bit digital signal and outputs a latch signal at the start of the fifth timing Φ5. The latch signal is a DA switching unit of the DA conversion unit 43. 46, the first reference voltage 50 and the second reference voltage 51 are switched. The input switching means 42, DA converting means 43, integrating means 44, and comparing means 45 constitute a ΣΔ modulator 61.

  The pulse density modulation signal output from the ΣΔ modulator 61 is input to a digital AGC circuit 47. The digital AGC circuit 47 includes an amplitude detection means 71, a gain calculation means 72, and a substitution calculation means 73. The amplitude detection means 71 receives a pulse density modulation signal output from the ΣΔ modulator 61, removes high frequency noise and outputs a multi-bit signal, and a multi-pass signal output from the digital low-pass filter 74. A full-wave rectifier circuit 75 that inputs a bit signal and rectifies and outputs it, and a digital low-pass filter 76 that receives the rectified signal output from the full-wave rectifier circuit 75 and smoothes it to output amplitude information. Composed. Further, the amplitude information output from the amplitude detecting means 71 is input to the gain calculating means 72, and the gain calculating means 72 is composed of a bit shift calculating means 77 and an adding calculating means 78. The gain calculation means 72 calculates a gain information by performing a bit shift operation of a predetermined coefficient value and an addition operation of the predetermined coefficient value for the input amplitude information. Here, the coefficient values used in the bit shift calculation means 77 and the addition calculation means 78 are read from the ROM 79 and supplied. Then, the gain information output from the gain calculating means 72 and the pulse density modulation signal output from the ΣΔ modulator 61 are input to the replacement calculating means 73 and subjected to replacement calculation, whereby gain controlled multi-bit The digital AGC circuit 47 outputs the pulse density modulation signal. Further, the gain-controlled multi-bit pulse density modulation signal output from the digital AGC circuit 47 is input to the digital filter 48.

  A configuration example of the digital filter 48 is shown in FIG. The coefficient values used for the arithmetic processing of the digital filter 48 are read from the ROM 79 and supplied. The multi-bit signal from which high frequency noise due to the ΣΔ modulation by the digital filter 48 is removed, and only the resonance frequency of the sensor element 30 is extracted and the noise component is removed is input to the drive circuit 49.

  The drive circuit 49 includes a digital value output means 80 that holds two values, an addition / integration calculation means 81 that adds and integrates the output signal from the digital filter 48 and the output of the digital value output means 80, and this addition. A value comparison unit 83 for comparing the output from the integral calculation unit 81 with a comparison constant value 82; a value switching unit 84 for switching the digital value output from the digital value output unit 80 in accordance with the output from the value comparison unit 83; It has a digital ΣΔ modulator 86 composed of a flip-flop 85 that latches the output of the value comparison means 83 at a predetermined timing. The multi-bit signal output from the digital filter 48 by the digital ΣΔ modulator 86 is modulated and output to a 1-bit pulse density modulation signal, and this pulse density modulation signal is input to an analog low-pass filter 87, and further sensor elements The frequency component harmful to driving 30 is filtered and output to the sensor element 30. With the above configuration, the vibration of the vibrating body 31 is adjusted so as to have a constant amplitude.

  The PLL circuit 91 multiplies the monitor signal output from the digital low-pass filter 74 in the drive circuit 41, integrates and reduces the phase noise in time, and outputs it. Reference numeral 92 denotes a timing generation circuit. The timing generation circuit 92 is based on a signal obtained by multiplying the monitor signal output from the PLL circuit 91, and the first timing Φ1 and the second timing Φ2 for two periods of the monitor signal. The timing signal is divided into a third timing Φ3 and a fourth timing Φ4, and is output. The PLL circuit 91 and the timing generation circuit 92 constitute a timing control circuit 93. 94 is an input switching means, and this input switching means 94 is connected to the first sense electrode 34 in the sensor element 30 and operates at the second timing Φ2; And an analog switch 96 which is connected to the sense electrode 35 and operates at the fourth timing Φ4. With this configuration, the input switching unit 94 switches and outputs the input signal from the first sense electrode 34 or the second sense electrode 35 at the second timing Φ2 or the fourth timing Φ4. Reference numeral 97 denotes DA switching means. The DA switching means 97 has a first reference voltage 99 and a second reference voltage 100, and the first reference voltage 99 and the second reference voltage 100 are set to a predetermined signal. Is switched by. Reference numeral 101 denotes DA output means. The DA output means 101 is connected to the capacitor 102 to which the output signal of the DA switching means 97 is input, and is connected to both ends of the capacitor 102, and the first timing Φ1 and the third timing. It is composed of SWs 103 and 104 that operate at Φ3 and discharge the electric charge of the capacitor 102. The DA switching means 97 and the DA output means 101 constitute a DA converting means 98, and the DA converting means 98 discharges the electric charge of the capacitor 102 at the first timing Φ1 and the third timing Φ3, Further, charges corresponding to the reference voltage output by the DA switching means 97 are input / output at the second timing Φ2 and the fourth timing Φ4.

  Reference numeral 105 denotes a switch, and the outputs of the input switching means 94 and the DA conversion means 98 are input to the SW 105 and output at the second timing Φ2 and the fourth timing Φ4. Reference numeral 106 denotes an integrating circuit to which the output of the SW 105 is input. The operational amplifier 107, a pair of capacitors 108 and 109 connected in parallel to the feedback of the operational amplifier 107, and this capacitor It is composed of a pair of SWs 110 and 111 connected to 109. Further, the SW 110 operates at the first timing Φ1 and the second timing Φ2, and the input signal to the integrating circuit 106 is integrated into the capacitor 108 and the integrated value is held. Further, the SW 111 operates at the third timing Φ3 and the fourth timing Φ4, and the input signal to the integrating circuit 106 is integrated into the capacitor 109 to hold the integrated value. Reference numeral 113 denotes a comparison means. The comparison means 113 receives the integration signal output from the integration means 112, and compares the integration signal with a predetermined value. The comparator 114 outputs one bit. It comprises a D-type flip-flop 115 to which a digital signal is input. The D-type flip-flop 115 latches the 1-bit digital signal at the start of the second timing Φ2 and the fourth timing Φ4, and outputs a latch signal. The first reference voltage 99 and the second reference voltage 100 are switched by being inputted to the DA switching means 97 of the means 98. The input switching means 94, DA conversion means 98, integrating means 112, and comparing means 113 constitute a ΣΔ modulator 116.

  In addition, the ΣΔ modulator 116 is configured to ΣΔ modulate the electric charges output from the pair of sense electrodes 34 and 35 in the sensor element 30, convert it to a 1-bit digital signal, and output it.

  A latch circuit 117 receives a 1-bit digital signal output from the comparator 114 in the comparator 113 of the ΣΔ modulator 116 and latches the 1-bit digital signal. A flip-flop 119 is used. The D-type flip-flop 118 latches the 1-bit digital signal at the second timing Φ2, and the D-type flip-flop 119 latches the 1-bit digital signal at the fourth timing Φ4. . Reference numeral 120 denotes difference calculation means. The difference calculation means 120 receives a pair of 1-bit digital signals latched and output by the pair of D-type flip-flops 119 in the latch circuit 117, and the pair of 1-bit digital signals. 1-bit difference calculation for calculating the difference between the two is realized by replacement processing. That is, when the pair of 1-bit digital signals input to the difference calculation means 120 are “00”, “01”, “10”, and “11”, they are replaced with “0”, “−1”, “1”, and “0”, respectively. Output. Reference numeral 121 denotes a correction calculation unit. The correction calculation unit 121 receives a 1-bit difference signal output from the difference calculation unit 120, and realizes a correction calculation between the 1-bit difference signal and predetermined correction information by replacement processing. Is. That is, as described above, the 1-bit difference signal input to the correction calculation unit 121 is “0”, “1”, “−1”. For example, when the correction information is “5”, “0” “ The output is replaced with 5 ""-5 ". Reference numeral 122 denotes a digital filter. The digital filter 122 receives the digital difference signal output from the correction calculation means 121 and performs a filtering process to remove noise components. The latch circuit 117, the difference calculation means 120, the correction calculation means 121, and the digital filter 122 constitute a calculation means 123. In addition, the calculation means 123 latches a pair of 1-bit digital signals at the second and fourth timings, performs difference calculation, correction calculation, and filtering processing, and outputs a multi-bit signal. Further, the ΣΔ modulator 116 and the calculation means 123 constitute a sense circuit 124.

  Next, the operation of the angular velocity sensor according to the first embodiment of the present invention configured as described above will be described.

  When a drive signal is applied to the drive electrode 32 of the sensor element 30, the vibrating body 31 resonates and charges are generated at the monitor electrode 33. The charges generated on the monitor electrode 33 are input to the ΣΔ modulator 61 in the drive circuit 41 and converted into a pulse density modulation signal. The pulse density modulation signal output from the ΣΔ modulator 61 is input to the digital AGC circuit 47, and amplitude information of the signal generated from the monitor electrode 33 is obtained by the amplitude detection means 71 of the digital AGC circuit 47. Information is input to the gain calculation means 72, and gain information is obtained by calculation. The gain information output from the gain calculation means 72 and the pulse density modulation signal output from the ΣΔ modulator 61 are input to the replacement calculation means 73, and the multi-bit is gain-controlled so that the vibration of the vibrating body 31 has a constant amplitude. The pulse density modulation signal is output. The gain-controlled multi-bit pulse density modulation signal is input to the digital filter 48, and a multi-bit signal from which only noise components extracted from the resonance frequency of the vibrator 31 are removed is output. The multibit signal output from the digital filter 48 is input to the drive circuit 49, and a drive signal is output from the digital ΣΔ modulator 86 and the analog filter 87 constituting the drive circuit 49 to the drive electrode 32 in the sensor element 30. The vibration body 31 is adjusted so that the vibration has a constant amplitude. The operations of the ΣΔ modulator 61, the digital AGC circuit 47, the digital filter 48, and the drive circuit 49 in this case will be described below.

  The ΣΔ modulator 61 operates by repeating the first timing Φ5 and the second timing Φ6 that are synchronized with the monitor signal output from the timing control circuit 93. At the first timing Φ5, the sensor element 30 is operated. The signal output from the monitor electrode 33 is ΣΔ modulated and converted to a 1-bit digital signal.

  The operation at the above two timings will be described one by one. First, at the first timing Φ5, the 1-bit digital signal output from the comparator 59 of the comparing means 45 that compares the integrated value held in the capacitor 58 in the integrating means 44 is the rising edge of the first timing Φ5. Sometimes it is latched by the D-type flip-flop 60, and this latch signal is input to the DA switching means 46 of the DA converting means 43. Further, SW 54 and SW 55 in the DA output means 52 are turned on, and the electric charge held in the capacitor 53 is discharged.

  Next, at the second timing Φ 6, the reference voltages 50 and 51 are switched in accordance with the latch signal input to the DA switching unit 46 and input to the capacitor 53, and the reference voltage switched by the DA conversion unit 43 is set. The corresponding charge is output. Further, the input switching means 42 is turned on, and the charge generated from the monitor electrode 33 of the sensor element 30 is input. Further, the SW 56 in the integrating unit 44 is turned on, and the charges output from the input switching unit 42 and the DA converting unit 43 are input to the integrating unit 44. As a result, at the second timing Φ6, the capacitor 58 in the integrating means 44 integrates and holds the sum of the charge amount indicated by the hatched portion in FIG. 3A and the charge amount output from the DA converting means 43. It will be.

  The charges output from the monitor electrode 33 of the sensor element 30 are ΣΔ-modulated by the above operation at the first timing Φ5 and the second timing Φ6, and a 1-bit digital signal is generated at the rising edge of the signal at the first timing Φ5. Will be output.

  Next, the operation of the digital AGC circuit 47 will be described. The pulse density modulation signal output from the ΣΔ modulator 61 is input to a digital low-pass filter 74 included in the amplitude detection means 71 to remove high frequency noise and converted into a multi-bit signal shown in FIG. . This multi-bit signal is input to the full-wave rectifier circuit 75 and converted into a rectified signal. At this time, when the input signal is a sine wave signal centered on “0”, full-wave rectification can be realized only by inverting the sign bit. The signal that has been full-wave rectified by the full-wave rectifier circuit 75 in this way is input to the digital low-pass filter 76 and smoothed, so that the amplitude of the signal output from the monitor electrode 33 shown in FIG. Corresponding amplitude information can be obtained. At this time, in FIGS. 4A and 4B, processing is performed at the same sampling rate, but about one point is sufficient for the amplitude information for one monitor signal output from the monitor electrode 33. You may downsample and process. Next, the amplitude information output from the amplitude detector 71 is input to the gain calculator 72, and the gain information is calculated. Here, when the AGC gain characteristic for controlling the vibration amplitude of the sensor element 30 to be constant is shown in FIG. 5, by performing bit shift calculation and addition calculation as shown in (Equation 1), Gain information can be calculated.

  At this time, “+ c” is addition processing of the constant value “B”, and the operation of “A * x” is as shown in (Equation 2) when it is desired to set “A” to “−1.25”. Since they can be re-represented, the bit shift operation and the addition operation and ± can perform the operation of (Expression 2) only by reversing the sign bit.

  As described above, the AGC gain information for controlling the vibration amplitude of the sensor element 30 to be constant is calculated by the bit shift calculation means 77 and the addition calculation means 78 of the gain calculation means 72. At this time, the inclination “A” and the intercept “B” are determined not by fixed values but by values read from the ROM 79, and the shift amount in the bit shift calculation unit 77 and the addition calculation unit 78 add by the determined values. By changing the value of the intercept “B”, the AGC gain characteristic can be easily changed. As a result, it is possible to provide an angular velocity sensor that can change the AGC gain characteristic only by rewriting the ROM value in accordance with the characteristics of the sensor element and the application in which the sensor is used.

  Next, the gain information “G” output from the gain calculation means 72 and the pulse density modulation signal output from the ΣΔ modulator 61 are input to the replacement calculation means 73. Here, since the pulse density modulation signal output from the ΣΔ modulator 61 is a 1-bit signal of “1” or “−1”, it is replaced with gain information “G”, that is, “−1” → “−G”. By substituting “,” “1” → “G”, it is possible to realize an operation of “input signal × G” without using a multiplier. Therefore, the replacement calculation means 73 calculates the gain. Here, the ΣΔ modulator 61 is described as a 1-bit ΣΔ modulator, but even if it is a multiple-bit output ΣΔ modulator, if the output of the ΣΔ modulator is 2 bits, for example, “00, 01, 611” By substituting “00, 01, 611” ⇒ “−G, −G / 2, G / 2, G”, “input signal × G” can be realized with the same configuration as above. It will be. As described above, the digital AGC circuit 47 outputs a multi-bit pulse density modulation signal that is gain-controlled in order to control the vibration amplitude of the sensor element 30 to be constant. It is possible to obtain an effect that it can be realized by a digital circuit at a low cost and with high accuracy without being used.

  Next, the operation of the digital filter 48 to which the gain-controlled multi-bit pulse density modulation signal output from the digital AGC circuit 47 is input will be described. Here, FIG. 2 shows a configuration example of the digital filter 48. In FIG. 2, reference numeral 141 denotes a general IIR configuration of an IIR filter, reference numerals 142 to 146 denote gain calculation units for determining characteristics of the filter, reference numerals 147 and 148 denote addition calculation units, and reference numerals 149 and 150 denote delay units. It is. Here, when the gain coefficients of the gain calculation units 142 to 146 that determine the characteristics of the filter are set to {a0, a1, a2, b0, b1} = {1, 81.71475, −0.75}, for example, The gain can be rewritten as shown in 3), and these gain calculations can be performed by bit shift calculation as described in the gain calculation means.

  Reference numerals 151 to 153 denote bit shift calculation units. By calculating these values as indicated by (Equation 4), c0 is first calculated as +7 bit shift (× 128), and then −7 in c2. By performing bit shift (1/128), it is possible to reduce calculation errors such as rounding error due to bit shift calculation.

  With the above configuration / operation, there is an effect that it is possible to obtain a low-cost digital filter that can perform the filter operation while ensuring the operation accuracy only by the bit shift operation and the addition operation. The gain calculation by the bit shift can also be used in other filter formats such as FIR, and the necessary filter characteristics can be realized by cascading the IIR filter configuration of FIG. It will be. Further, when the sensor element 30 is vibrated only at a predetermined resonance frequency, it is desirable to have a band-pass filter characteristic. Therefore, the pulse density modulation signal output from the digital AGC circuit 47 is input to the digital filter 48, and a multi-bit signal whose noise component is filtered and gain controlled is output.

  Further, the operation when the bit shift operation unit 154 is additionally provided will be described. First, the gain information “G” in the digital AGC circuit 47 is set to a value of “0 to 256” of “128 ± 128”, for example, and the gain coefficient {d2} = {1/128} = {1/2 ^ 7} By performing substitution operation and bit shift as -7 bit shift (1/128), the digital AGC circuit 47 and the digital filter 48 can calculate the variable gain from 0 to 2 times with the resolution of “1/128”. It can be realized while ensuring. Furthermore, the gain resolution and the gain width can be arbitrarily set only by securing a necessary amount of the value that the gain information “G” can take and the bit shift amount of the gain coefficient {d2}.

  By configuring / operating as described above, it is possible to convert to a multi-bit pulse density modulation signal and a multi-bit signal that are gain-controlled without using a multiplier. This has the effect that a digital AGC circuit and a digital filter whose filter characteristics can be easily changed can be realized. Further, by adopting a configuration in which the bit shift amount in the above bit shift operation is determined by the data stored in the ROM 79, the value stored in the ROM 79 for the filter characteristics is rewritten according to the characteristics of the sensor element and the application in which the sensor is used. It is possible to provide an angular velocity sensor that can be changed only by this.

  Next, the operation of the drive circuit 49 will be described. A value switching means for outputting either the multi-bit signal output from the digital filter 48 or the digital value output means 80 holding a predetermined binary value to the addition / integration operation means 81 of the digital ΣΔ modulator 86. The constant value output from 84 is input to the addition / integration calculating means 81 and added and integrated. The integration value output from the addition / calculation calculation means 81 is compared with the comparison constant value 82 by the value comparison means 83, and the comparison result is output. Then, the comparison result is latched and output by the flip-flop 85 at a predetermined timing. The constant value output from the value switching means 84 is switched by the output of the flip-flop 85. At this time, when the output value of the addition / integration calculating means 81 is smaller than the comparison constant value 82, the larger value of the two values of the digital value output means 80 is selected, and in the opposite case, the smaller value is selected. And operate to be output. By repeating this operation, the multi-bit signal output from the digital filter 48 is modulated into a 1-bit pulse density modulation signal and output from the flip-flop 85. Here, when the signal input to the digital ΣΔ modulator 86 is, for example, 10 bits (= ± 9 bits), the comparison constant value 82 is set to “0” and the binary value of the digital value output means 80 is set to “511” “−511”. "It is desirable to set it above.

  With the above configuration, the signal output from the monitor electrode 33 of the sensor element 30 is converted into a pulse density modulation signal by the ΣΔ modulator 61, and the digital AGC circuit 47 controls the vibration of the sensor element 30 to be constant. The amplitude is adjusted by the AGC gain characteristic, and the noise is removed by the digital filter 48 to be multibited. This multi-bit signal whose amplitude has been adjusted is ΣΔ modulated by the digital ΣΔ modulator 86 and converted into a 1-bit pulse density modulation signal, and this signal is output to the drive electrode 32 in the sensor element 30. At this time, the 1-bit pulse density modulation signal includes the frequency component of the signal output from the monitor electrode 33 with the amplitude adjusted by the digital AGC circuit 47, and this signal is output to the sensor element 30. The vibration of the vibrating body 31 vibrates with a constant amplitude at a predetermined resonance frequency. By configuring the drive circuit 49 as described above, it can be realized by most digital circuits without using a high-precision DA converter, so that a low-cost and high-precision angular velocity sensor can be provided. The effect is obtained.

  Note that in ΣΔ modulation, oversampling is performed, and the quantization noise is noise-jumped to a high frequency, so that it includes a noise component of a high frequency component, but the response of the sensor element 30 cannot respond to such a high frequency. It vibrates at a predetermined frequency component oversampled instead of the sampling frequency of the density modulation signal. Further, when the sensor element 30 has a high response gain at a high frequency and noise of such a high frequency component becomes a problem, a setting is made to reduce the problematic frequency component in the output signal of the digital ΣΔ modulator 86. By adding the analog filter 87, it is possible to realize the drive circuit 41 with lower noise and higher accuracy.

  Further, a sine wave signal shown in FIG. 6A is input to the timing control circuit 93 in the sense circuit 124, and the timing generation circuit 92 based on the signal multiplied by the PLL circuit 91 causes the timing generation circuit 92 to change the timing control circuit 93. The first timing Φ1, the second timing Φ2, the third timing Φ3, and the fourth timing Φ4 are formed. Then, this timing signal is input to the ΣΔ modulator 116 and the calculation means 123 as SW switching and latch timing of the latch circuit. Further, the sine wave signal whose phase is shifted by 90 degrees by the phase shifter is input to a voltage comparator (not shown) that compares it with a predetermined reference voltage (not shown), and the output thereof is a logic circuit (not shown). ), It is possible to form the timing signals Φ1, Φ2, Φ3, and Φ4. In this case, however, the voltage noise of the sine wave signal and the voltage noise due to temperature change and power supply fluctuation are in phase. It will appear as noise. The phase noise is a factor that adversely affects the accuracy of signal processing as timing noise for switching the input signal and the integration switching means. However, the phase noise is integrated with time using the PLL circuit 91 to reduce the phase noise. By doing so, switching timing noise can be reduced and the accuracy of signal processing can be increased. When the sensor element 30 is bent and vibrated at a speed V in the driving direction illustrated in FIG. 1, when the sensor element 30 rotates at an angular speed ω around the central axis in the longitudinal direction of the vibrating body 31, A Coriolis force of F = 2 mV × ω is generated in the sensor element 30. Due to this Coriolis force, electric charges are generated in the pair of sense electrodes 34 and 35 of the sensor element 30 as shown in FIGS. 6 (c) and 6 (d). Since the charges generated in the sense electrodes 34 and 35 are generated by Coriolis force, the phase is advanced by 50 degrees from the signal generated in the monitor electrode 33. The output signals generated at the pair of sense electrodes 34 and 35 are in a relationship between a positive polarity signal and a negative polarity signal, as shown in FIGS. 6 (c) and 6 (d).

  The operation of the ΣΔ modulator 116 in this case will be described below. The ΣΔ modulator 116 operates by repeating the first timing Φ1, the second timing Φ2, the third timing Φ3, and the fourth timing Φ4. In the first timing Φ1 and the second timing Φ2, The positive signal output from the first sense electrode 34 in the sensor element 30 is ΣΔ-modulated and converted into a 1-bit digital signal, and from the second sense electrode 35 at the third timing Φ3 and the fourth timing Φ4. The output negative signal is ΣΔ modulated and converted to a 1-bit digital signal.

  The operation at the above four timings will be described one by one. First, at the first timing Φ1, the SW 110 connected to the capacitor 108 in the integrating means 112 is turned on, and the integrated value held in the capacitor 108 is input to the comparator 114 in the comparing means 113, and the comparison result is 1. It is output as a bit digital signal. Further, the SWs 103 and 104 in the DA conversion means 98 are turned on, and the electric charge held in the capacitor 102 is discharged.

  Next, at the second timing Φ2, the 1-bit digital signal output from the comparator 114 of the comparing means 113 is latched in the D-type flip-flop 115 at the rising edge of the second timing Φ2, and this latch signal is converted to the DA converter. This is input to the DA switching means 97 of the means 98. In accordance with the input latch signal, the reference voltage is switched to the first reference voltage 99 or the second reference voltage 100 and input to the capacitor 102, and the charge corresponding to the reference voltage switched by the DA changing means 98 is supplied. Is output. At the same time, the SW 95 is turned on in the input switching means 94, and the electric charge generated from the first sense electrode 34 of the sensor element 30 is output. Further, the SW 105 in the integrating unit 112 is turned on, and the charges output from the input switching unit 94 and the DA converting unit 98 are input to the integrating circuit 106. Accordingly, at the second timing Φ2, the sum of the charge amount indicated by the hatched portion in FIG. 6C and the charge amount output from the DA conversion means 98 is integrated and held in the capacitor 108 in the integration circuit 106. It will be.

  With the above operation at the first timing Φ1 and the second timing Φ2, the charge amount corresponding to half of the amplitude value output from the sense electrode 34 of the sensor element 30 is ΣΔ modulated.

  Similarly to the operation at the first timing Φ1 and the second timing Φ2, at the third timing Φ3 and the fourth timing Φ4, the amplitude value output from the second sense electrode 35 of the sensor element 30 is changed. The charge amount corresponding to half is ΣΔ modulated, converted into a 1-bit digital signal, and output. With the above operation, a charge amount corresponding to half of the amplitude value of the charges output from the pair of sense electrodes 34 and 35 in the sensor element 30 is ΣΔ modulated by one ΣΔ modulator 116 to be converted into a pair of 1-bit digital signals. It is output at the above timing.

  In addition, the electric charges output from the first sense electrode 34 and the second sense electrode 35 in the sensor element 30 are senses whose phase is advanced by 90 degrees from the signal generated in the monitor electrode 33 generated by the Coriolis force due to the angular velocity. Since there is not only a signal but also an unnecessary signal in phase with the monitor signal, a case where a combined signal of the sense signal and the unnecessary signal is output from the first sense electrode 34 and the second sense electrode 35 in the sensor element 30 will be described. . The sense signal generated by the Coriolis force due to the angular velocity is shown in FIGS. 6C and 6D, and as described above, the integration circuit 106 uses the integration circuit 106 in FIG. c) The charge amount indicated by the shaded area in (d), that is, the charge amount corresponding to half of the amplitude value is integrated. Further, unnecessary signals generated from the first sense electrode 34 and the second sense electrode 35 are shown in FIGS. 6E and 6F, and the second timing Φ2 and the fourth timing are the same as the sense signal. In Φ4, the charge amount indicated by the hatched portion in FIGS. 6E and 6F, that is, the charge amount in the section from the maximum value to the minimum value of the amplitude of the unnecessary signal is integrated. This is canceled when integration is performed based on the median value of the amplitude, resulting in a charge amount of “0”. That is, a so-called synchronous detection process in which the unnecessary signal is canceled and the charge amount according to the amplitude of the sense signal is integrated by the operation of the integrating unit 112 at the second timing Φ2 and the fourth timing Φ4 is a pair of inputs. Will be implemented for each of the signals. Therefore, similarly to the description of the operation when there is no unnecessary signal, the signal subjected to the synchronous detection processing is ΣΔ modulated from the ΣΔ modulator 116, converted into a 1-bit digital signal, and output.

  Next, the operation of the calculation means 123 will be described. First, at the second timing Φ 2, the 1-bit digital signal output from the comparator 114 in the comparison unit 113 of the ΣΔ modulator 116 is latched in the D-type flip-flop 118 of the latch circuit 117. At the fourth timing Φ 4, the 1-bit digital signal output from the comparator 114 in the comparison unit 113 of the ΣΔ modulator 116 is latched by the D-type flip-flops 118 and 119 of the latch circuit 117.

  As described above, the pair of 1-bit digital signals latched by the pair of D-type flip-flops 118 and 119 exclude unnecessary signals output from the pair of sense electrodes 34 and 35 in the sensor element 30. The charge amount corresponding to half of the amplitude value is converted into a digital value by ΣΔ modulation. Next, a pair of 1-bit digital signals output from the latch circuit 117 are input to the 1-bit difference calculation means 120, and a difference between the pair of 1-bit digital signals is calculated to output a 1-bit difference signal. Here, the 1-bit difference signal at the first timing Φ1 is the difference between the 1-bit digital signal latched at the second timing Φ2 and the fourth timing Φ4 in the previous cycle, and this 1-bit difference signal The signal is a signal representing an amplitude value excluding unnecessary signals of signals output from the pair of sense electrodes 34 and 35 in the sensor element 30 shown in FIGS. Next, the 1-bit difference signal output from the 1-bit difference calculation unit 120 is input to the correction calculation unit 121, and the correction calculation between the 1-bit difference signal and predetermined correction information is performed by a replacement process. As described above, this correction calculation uses the fact that the 1-bit difference signal is limited to the three values “0”, “1”, and “−1”, for example, when the predetermined correction information is “5”. The 1-bit differential signal “0”, “1”, “−1” input to the correction calculation means is replaced with “0”, “5”, “−5”, respectively, so that multiplication is realized to correct the signal. It is possible.

(Embodiment 2)
Hereinafter, an angular velocity sensor using a digital AGC circuit according to Embodiment 2 of the present invention will be described with reference to the drawings.

  FIG. 7 is a circuit diagram of an angular velocity sensor using a digital AGC circuit according to Embodiment 2 of the present invention. In the second embodiment of the present invention, components having the same configurations as those of the first embodiment of the present invention described above are denoted by the same reference numerals, and description thereof is omitted.

  The drive circuit 49 includes a DA converter 131. At this time, a signal as shown in FIG. 8A is input to the ΣΔ modulator 61 in the drive circuit 41 and converted into a 1-bit pulse density modulation signal shown in FIG. 8B. The 1-bit pulse density modulation signal is input to the digital AGC circuit 47, and gain control is performed by an arbitrary AGC gain characteristic. As shown in FIG. 8C, ± G [LSB] multi-bit pulse density modulation is performed. The multi-bit pulse density modulation signal is directly input to the DA converter 131, and the pulse density modulation signal of G [LSB] as shown in FIG. A drive signal having an amplitude voltage corresponding to the value is output and input to the monitor electrode 33 in the sensor element 30. This drive signal includes a predetermined frequency component of the signal output from the monitor electrode 33, the amplitude of which is adjusted by the digital AGC, and this signal is output to the sensor element 30. The vibration is controlled to vibrate with a constant amplitude at a predetermined resonance frequency. As described above, a drive circuit can be configured with a small number of circuits such as the ΣΔ modulator 61, the digital AGC circuit 47, and the DA converter 131, thereby providing a small and low-cost angular velocity sensor. Is obtained. Further, by adding a digital filter 48 or an analog filter 87 in which frequency characteristics are set so as to remove unnecessary frequency components having a high response gain of the sensor element other than a predetermined frequency to be vibrated and high frequency noise due to ΣΔ modulation. In addition, it is possible to provide an angular velocity sensor having a drive circuit with higher accuracy and lower noise.

  The digital AGC circuit and the angular velocity sensor using the digital AGC circuit according to the present invention have an effect of providing a small AGC circuit that does not require a multiplier and an angular velocity sensor using the same in an operation such as gain calculation. In particular, it is useful as a digital AGC circuit used for vibration control of a sensor element in a sensor device and an angular velocity sensor using the digital AGC circuit.

Circuit diagram of angular velocity sensor using digital AGC circuit in embodiment 1 of the present invention Circuit diagram of digital filter in drive circuit of same angular velocity sensor (A)-(c) The figure which shows the operation state of (SIGMA) delta modulator. (A) (b) The figure which shows the operation state of a digital AGC circuit The figure which shows the AGC gain characteristic of the digital AGC circuit in Embodiment 1 of this invention (A)-(f) The figure which shows the operation state of the angular velocity sensor using the digital AGC circuit Circuit diagram of angular velocity sensor using digital AGC circuit in embodiment 2 of the present invention (A)-(d) The figure which shows the operation state of the same angular velocity sensor Circuit diagram of conventional ΣΔ AD converter

Explanation of symbols

Reference Signs List 30 sensor element 32 drive electrode 33 monitor electrode 34, 35 sense electrode 41 drive circuit 43 DA conversion means 44 integration means 45 comparison means 48, 74, 76 digital filter 49 drive circuit 61 ΣΔ modulator 71 amplitude detection means 72 gain calculation means 73 Replacement arithmetic means 75 Full wave rectifier circuit 77, 151, 152, 153 Bit shift arithmetic means 78, 147, 148 Addition arithmetic means 87 Analog filter

Claims (17)

DA conversion means for outputting charge amounts of at least two levels, integration means for adding and integrating a signal output from the DA conversion means and an externally input signal and holding the integration value, and this integration means An sigma-delta modulator comprising: comparing means for comparing the integral value output from the predetermined value; and DA switching means for switching the output of the DA converting means in accordance with the output of the comparing means; and amplitude detecting means And a digital AGC circuit composed of gain calculating means and replacement calculating means. 2. The digital AGC circuit according to claim 1, wherein the gain calculating means includes a bit shift calculating means and an adding calculating means. 2. The digital AGC circuit according to claim 1, wherein the data stored in the ROM is inputted to the gain calculating means. 2. The digital AGC circuit according to claim 1, wherein the amplitude detecting means is provided with a digital filter and a full-wave rectifier circuit. 5. The digital AGC circuit according to claim 4, wherein the digital filter is composed of a bit shift operation means and an addition operation means. 2. The digital AGC circuit according to claim 1, wherein a digital filter to which an output signal of the replacement operation means is input and a bit shift operation means are added to the subsequent stage of the digital AGC circuit. 7. The digital AGC circuit according to claim 6, wherein the digital filter is composed of a bit shift operation means and an addition operation means. A sensor element having a drive electrode, a sense electrode, and a monitor electrode, a drive circuit that vibrates the sensor element with a predetermined amplitude, and a signal output from the sense electrode in the sensor element is converted into an angular velocity output signal. And a sense circuit, and the drive circuit integrates the DA conversion means for outputting charge amounts of at least two levels, the signal output from the monitor electrode in the sensor element, and the charge output from the DA conversion means. An integration circuit for holding the integration value, a comparison means for comparing the integration value output from the integration circuit with at least one predetermined value, and switching the output of the DA conversion means in accordance with the output of the comparison means Digital equipped with a ΣΔ modulator composed of DA switching means, amplitude detection means, gain calculation means, and replacement calculation means An angular velocity sensor composed of an AGC circuit and a drive circuit. 9. The angular velocity sensor according to claim 8, wherein the gain calculating means is composed of a bit shift calculating means and an adding calculating means. 9. The angular velocity sensor according to claim 8, wherein the data stored in the ROM is inputted to the gain calculating means. 9. The angular velocity sensor according to claim 8, wherein the amplitude detecting means is provided with a digital filter and a full-wave rectifier circuit. 2. The angular velocity sensor according to claim 1, wherein the digital filter is composed of a bit shift calculation means and an addition calculation means. 9. The angular velocity sensor according to claim 8, wherein the drive circuit is constituted by a DA converter that outputs a multi-bit signal in an analog manner. 14. The angular velocity sensor according to claim 13, wherein a digital filter for filtering the output of the digital AGC circuit and a bit shift calculation means are added to the subsequent stage of the digital AGC circuit. 15. The angular velocity sensor according to claim 14, wherein the digital filter is composed of a bit shift calculation means and an addition calculation means. The angular velocity sensor according to claim 14, wherein data stored in the ROM is input to a digital filter. The angular velocity sensor according to claim 8, further comprising an analog filter for filtering an output signal of the drive circuit.

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